mirror of
https://github.com/radareorg/radare2.git
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TriCore Registers Profile fix for arch "tricore" and "tricore.cs" ##arch
* Others TriCore CPU could require some adjustments on special registers.
This commit is contained in:
kcdq
GitHub
parent
4e47b8841d
commit
c0b426bb3c
@ -156,73 +156,81 @@ static bool decode(RArchSession *as, RAnalOp *op, RArchDecodeMask mask) {
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static char *get_reg_profile(RArchSession *as) {
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const char *p =
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"=PC pc\n"
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"=SP a10\n"
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"=BP a11\n"
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"=A0 a4\n"
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"=A1 a5\n"
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"=A2 a6\n"
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"=A3 a7\n"
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"=SN a0\n"
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"gpr p0 .64 0 0\n"
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"gpr a0 .32 0 0\n"
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"gpr a1 .32 4 0\n"
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"gpr p2 .64 8 0\n"
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"gpr a2 .32 8 0\n"
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"gpr a3 .32 12 0\n"
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"gpr p4 .64 16 0\n"
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"gpr a4 .32 16 0\n"
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"gpr a5 .32 20 0\n"
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"gpr p6 .64 24 0\n"
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"gpr a6 .32 24 0\n"
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"gpr a7 .32 28 0\n"
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"gpr p8 .64 32 0\n"
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"gpr a8 .32 32 0\n"
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"gpr a9 .32 36 0\n"
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"gpr p10 .64 40 0\n"
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"gpr sp .64 40 0\n"
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"gpr a10 .64 40 0\n"
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"gpr a11 .32 44 0\n"
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"gpr p12 .64 48 0\n"
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"gpr a12 .32 48 0\n"
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"gpr a13 .32 52 0\n"
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"gpr p14 .64 56 0\n"
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"gpr a14 .32 56 0\n"
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"gpr a15 .32 60 0\n"
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"gpr e0 .64 64 0\n"
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"gpr d0 .32 64 0\n"
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"gpr d1 .32 68 0\n"
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"gpr e2 .64 72 0\n"
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"gpr d2 .32 72 0\n"
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"gpr d3 .32 76 0\n"
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"gpr e4 .64 80 0\n"
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"gpr d4 .32 80 0\n"
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"gpr d5 .32 84 0\n"
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"gpr e6 .64 88 0\n"
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"gpr d6 .32 88 0\n"
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"gpr d7 .32 92 0\n"
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"gpr e8 .64 96 0\n"
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"gpr d8 .32 96 0\n"
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"gpr d9 .32 100 0\n"
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"gpr e10 .64 104 0\n"
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"gpr d10 .32 104 0\n"
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"gpr d11 .32 108 0\n"
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"gpr e12 .64 112 0\n"
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"gpr d12 .32 112 0\n"
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"gpr d13 .32 114 0\n"
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"gpr e14 .64 118 0\n"
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"gpr d14 .32 118 0\n"
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"gpr d15 .32 120 0\n"
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"gpr PSW .32 124 0\n"
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"gpr PCXI .32 128 0\n"
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"gpr FCX .32 132 0\n"
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"gpr LCX .32 136 0\n"
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"gpr ISP .32 140 0\n"
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"gpr ICR .32 144 0\n"
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"gpr PIPN .32 148 0\n"
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"gpr BIV .32 152 0\n"
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"gpr BTV .32 156 0\n"
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"gpr pc .32 160 0\n";
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"=PC pc\n"
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"=SP a10\n"
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"=BP a11\n"
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"=A0 a4\n"
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"=A1 a5\n"
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"=A2 a6\n"
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"=A3 a7\n"
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"=SN a0\n"
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"# General-Purpose Address Registers (A0 - A15)\n"
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"gpr a0 .32 0 0\n"
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"gpr a1 .32 4 0\n"
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"gpr a2 .32 8 0\n"
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"gpr a3 .32 12 0\n"
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"gpr a4 .32 16 0\n"
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"gpr a5 .32 20 0\n"
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"gpr a6 .32 24 0\n"
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"gpr a7 .32 28 0\n"
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"gpr a8 .32 32 0\n"
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"gpr a9 .32 36 0\n"
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"gpr sp .32 40 0\n"
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"gpr a10 .32 40 0\n"
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"gpr a11 .32 44 0\n"
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"gpr a12 .32 48 0\n"
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"gpr a13 .32 52 0\n"
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"gpr a14 .32 56 0\n"
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"gpr a15 .32 60 0\n"
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"# General-Purpose Data Registers (D0 - D15)\n"
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"gpr e0 .64 64 0\n"
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"gpr d0 .32 64 0\n"
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"gpr d1 .32 68 0\n"
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"gpr e2 .64 72 0\n"
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"gpr d2 .32 72 0\n"
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"gpr d3 .32 76 0\n"
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"gpr e4 .64 80 0\n"
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"gpr d4 .32 80 0\n"
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"gpr d5 .32 84 0\n"
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"gpr e6 .64 88 0\n"
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"gpr d6 .32 88 0\n"
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"gpr d7 .32 92 0\n"
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"gpr e8 .64 96 0\n"
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"gpr d8 .32 96 0\n"
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"gpr d9 .32 100 0\n"
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"gpr e10 .64 104 0\n"
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"gpr d10 .32 104 0\n"
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"gpr d11 .32 108 0\n"
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"gpr e12 .64 112 0\n"
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"gpr d12 .32 112 0\n"
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"gpr d13 .32 116 0\n"
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"gpr e14 .64 120 0\n"
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"gpr d14 .32 120 0\n"
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"gpr d15 .32 124 0\n"
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"# Special-Purpose Registers\n"
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"gpr PSW .32 128 0 # Program Status Word\n"
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"gpr PCXI .32 132 0 # Previous Context Information\n"
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"gpr FCX .32 136 0 # Free Context List Pointer\n"
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"gpr LCX .32 140 0 # Last Context Save Pointer\n"
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"gpr ISP .32 144 0 # Interrupt Stack Pointer\n"
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"gpr ICR .32 148 0 # Interrupt Control Register\n"
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"gpr PIPN .32 152 0 # Pending Interrupt Priority Number\n"
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"gpr BIV .32 156 0 # Base Interrupt Vector\n"
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"gpr BTV .32 160 0 # Base Trap Vector\n"
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"gpr pc .32 164 0 # Program Counter\n"
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"# System Control and Configuration Registers\n"
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"gpr SYSCON .32 168 0 # System Configuration Register\n"
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"gpr DCON2 .32 172 0 # Debug Control Register 2\n"
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"gpr CSP .32 176 0 # Context Save Pointer\n"
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"gpr MMUCON .32 180 0 # Memory Management Unit Control\n"
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"gpr CPU_ID .32 184 0 # CPU Identification Register\n"
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"gpr PSWEN .32 188 0 # Program Status Word Enable Register\n"
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"gpr CCUDR .32 192 0 # Cache Control Unit Debug Register\n"
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"gpr IECON .32 196 0 # Interrupt Enable Configuration Register\n"
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"gpr TRAPV .32 200 0 # Trap Vector Register\n"
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"gpr BBR .32 204 0 # Base Boundary Register (Optional, depending on use)\n"
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"gpr DBGSR .32 208 0 # Debug Status Register (Optional, depending on use)\n"
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"gpr PCON .32 212 0 # Peripheral Control Register (Optional, depending on use)\n";
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return strdup (p);
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}
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@ -333,75 +333,84 @@ static bool fini(RArchSession *as) {
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return true;
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}
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// Registers profile perfectly suitable for TC1767 CPU. Others CPU can require minor adjustments.
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static char *regs(RArchSession *as) {
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const char *p =
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"=PC pc\n"
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"=SP a10\n"
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"=BP a11\n"
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"=A0 a4\n"
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"=A1 a5\n"
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"=A2 a6\n"
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"=A3 a7\n"
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"=SN a0\n"
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"gpr p0 .64 0 0\n"
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"gpr a0 .32 0 0\n"
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"gpr a1 .32 4 0\n"
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"gpr p2 .64 8 0\n"
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"gpr a2 .32 8 0\n"
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"gpr a3 .32 12 0\n"
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"gpr p4 .64 16 0\n"
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"gpr a4 .32 16 0\n"
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"gpr a5 .32 20 0\n"
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"gpr p6 .64 24 0\n"
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"gpr a6 .32 24 0\n"
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"gpr a7 .32 28 0\n"
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"gpr p8 .64 32 0\n"
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"gpr a8 .32 32 0\n"
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"gpr a9 .32 36 0\n"
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"gpr sp .64 40 0\n"
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"gpr p10 .64 40 0\n"
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"gpr a10 .32 40 0\n"
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"gpr a11 .32 44 0\n"
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"gpr p12 .64 48 0\n"
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"gpr a12 .32 48 0\n"
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"gpr a13 .32 52 0\n"
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"gpr p14 .64 56 0\n"
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"gpr a14 .32 56 0\n"
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"gpr a15 .32 60 0\n"
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"gpr e0 .64 64 0\n"
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"gpr d0 .32 64 0\n"
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"gpr d1 .32 68 0\n"
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"gpr e2 .64 72 0\n"
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"gpr d2 .32 72 0\n"
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"gpr d3 .32 76 0\n"
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"gpr e4 .64 80 0\n"
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"gpr d4 .32 80 0\n"
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"gpr d5 .32 84 0\n"
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"gpr e6 .64 88 0\n"
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"gpr d6 .32 88 0\n"
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"gpr d7 .32 92 0\n"
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"gpr e8 .64 96 0\n"
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"gpr d8 .32 96 0\n"
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"gpr d9 .32 100 0\n"
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"gpr e10 .64 104 0\n"
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"gpr d10 .32 104 0\n"
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"gpr d11 .32 108 0\n"
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"gpr e12 .64 112 0\n"
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"gpr d12 .32 112 0\n"
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"gpr d13 .32 114 0\n"
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"gpr e14 .64 118 0\n"
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"gpr d14 .32 118 0\n"
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"gpr d15 .32 120 0\n"
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"gpr PSW .32 124 0\n"
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"gpr PCXI .32 128 0\n"
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"gpr FCX .32 132 0\n"
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"gpr LCX .32 136 0\n"
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"gpr ISP .32 140 0\n"
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"gpr ICR .32 144 0\n"
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"gpr PIPN .32 148 0\n"
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"gpr BIV .32 152 0\n"
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"gpr BTV .32 156 0\n"
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"gpr pc .32 160 0\n";
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"=PC pc\n"
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"=SP a10\n"
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"=BP a11\n"
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"=A0 a4\n"
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"=A1 a5\n"
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"=A2 a6\n"
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"=A3 a7\n"
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"=SN a0\n"
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"# General-Purpose Address Registers (A0 - A15)\n"
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"gpr a0 .32 0 0\n"
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"gpr a1 .32 4 0\n"
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"gpr a2 .32 8 0\n"
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"gpr a3 .32 12 0\n"
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"gpr a4 .32 16 0\n"
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"gpr a5 .32 20 0\n"
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"gpr a6 .32 24 0\n"
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"gpr a7 .32 28 0\n"
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"gpr a8 .32 32 0\n"
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"gpr a9 .32 36 0\n"
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"gpr sp .32 40 0\n"
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"gpr a10 .32 40 0\n"
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"gpr a11 .32 44 0\n"
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"gpr a12 .32 48 0\n"
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"gpr a13 .32 52 0\n"
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"gpr a14 .32 56 0\n"
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"gpr a15 .32 60 0\n"
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"# General-Purpose Data Registers (D0 - D15)\n"
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"gpr e0 .64 64 0\n"
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"gpr d0 .32 64 0\n"
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"gpr d1 .32 68 0\n"
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"gpr e2 .64 72 0\n"
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"gpr d2 .32 72 0\n"
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"gpr d3 .32 76 0\n"
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"gpr e4 .64 80 0\n"
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"gpr d4 .32 80 0\n"
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"gpr d5 .32 84 0\n"
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"gpr e6 .64 88 0\n"
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"gpr d6 .32 88 0\n"
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"gpr d7 .32 92 0\n"
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"gpr e8 .64 96 0\n"
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"gpr d8 .32 96 0\n"
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"gpr d9 .32 100 0\n"
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"gpr e10 .64 104 0\n"
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"gpr d10 .32 104 0\n"
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"gpr d11 .32 108 0\n"
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"gpr e12 .64 112 0\n"
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"gpr d12 .32 112 0\n"
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"gpr d13 .32 116 0\n"
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"gpr e14 .64 120 0\n"
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"gpr d14 .32 120 0\n"
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"gpr d15 .32 124 0\n"
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"# Special-Purpose Registers\n"
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"gpr PSW .32 128 0 # Program Status Word\n"
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"gpr PCXI .32 132 0 # Previous Context Information\n"
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"gpr FCX .32 136 0 # Free Context List Pointer\n"
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"gpr LCX .32 140 0 # Last Context Save Pointer\n"
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"gpr ISP .32 144 0 # Interrupt Stack Pointer\n"
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"gpr ICR .32 148 0 # Interrupt Control Register\n"
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"gpr PIPN .32 152 0 # Pending Interrupt Priority Number\n"
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"gpr BIV .32 156 0 # Base Interrupt Vector\n"
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"gpr BTV .32 160 0 # Base Trap Vector\n"
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"gpr pc .32 164 0 # Program Counter\n"
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"# System Control and Configuration Registers\n"
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"gpr SYSCON .32 168 0 # System Configuration Register\n"
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"gpr DCON2 .32 172 0 # Debug Control Register 2\n"
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"gpr CSP .32 176 0 # Context Save Pointer\n"
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"gpr MMUCON .32 180 0 # Memory Management Unit Control\n"
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"gpr CPU_ID .32 184 0 # CPU Identification Register\n"
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"gpr PSWEN .32 188 0 # Program Status Word Enable Register\n"
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"gpr CCUDR .32 192 0 # Cache Control Unit Debug Register\n"
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"gpr IECON .32 196 0 # Interrupt Enable Configuration Register\n"
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"gpr TRAPV .32 200 0 # Trap Vector Register\n"
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"gpr BBR .32 204 0 # Base Boundary Register (Optional, depending on use)\n"
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"gpr DBGSR .32 208 0 # Debug Status Register (Optional, depending on use)\n"
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"gpr PCON .32 212 0 # Peripheral Control Register (Optional, depending on use)\n";
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return strdup (p);
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}
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@ -50,73 +50,81 @@ NAME=TriCore return_0.elf
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FILE=bins/tricore/return_0.elf
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CMDS=drp
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EXPECT=<<EOF
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=PC pc
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=SP a10
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=BP a11
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=A0 a4
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=A1 a5
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=A2 a6
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=A3 a7
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=SN a0
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gpr p0 .64 0 0
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gpr a0 .32 0 0
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gpr a1 .32 4 0
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gpr p2 .64 8 0
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gpr a2 .32 8 0
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gpr a3 .32 12 0
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gpr p4 .64 16 0
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gpr a4 .32 16 0
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gpr a5 .32 20 0
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gpr p6 .64 24 0
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gpr a6 .32 24 0
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gpr a7 .32 28 0
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gpr p8 .64 32 0
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gpr a8 .32 32 0
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gpr a9 .32 36 0
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gpr p10 .64 40 0
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gpr sp .64 40 0
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gpr a10 .64 40 0
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gpr a11 .32 44 0
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gpr p12 .64 48 0
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gpr a12 .32 48 0
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gpr a13 .32 52 0
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gpr p14 .64 56 0
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gpr a14 .32 56 0
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gpr a15 .32 60 0
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gpr e0 .64 64 0
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gpr d0 .32 64 0
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gpr d1 .32 68 0
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gpr e2 .64 72 0
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gpr d2 .32 72 0
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gpr d3 .32 76 0
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gpr e4 .64 80 0
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gpr d4 .32 80 0
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gpr d5 .32 84 0
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gpr e6 .64 88 0
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gpr d6 .32 88 0
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gpr d7 .32 92 0
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gpr e8 .64 96 0
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gpr d8 .32 96 0
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gpr d9 .32 100 0
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gpr e10 .64 104 0
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gpr d10 .32 104 0
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gpr d11 .32 108 0
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gpr e12 .64 112 0
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gpr d12 .32 112 0
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gpr d13 .32 114 0
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gpr e14 .64 118 0
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gpr d14 .32 118 0
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gpr d15 .32 120 0
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gpr PSW .32 124 0
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gpr PCXI .32 128 0
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gpr FCX .32 132 0
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gpr LCX .32 136 0
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gpr ISP .32 140 0
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gpr ICR .32 144 0
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gpr PIPN .32 148 0
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gpr BIV .32 152 0
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gpr BTV .32 156 0
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gpr pc .32 160 0
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=PC pc
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=SP a10
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=BP a11
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=A0 a4
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=A1 a5
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=A2 a6
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=A3 a7
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=SN a0
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# General-Purpose Address Registers (A0 - A15)
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gpr a0 .32 0 0
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gpr a1 .32 4 0
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gpr a2 .32 8 0
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gpr a3 .32 12 0
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gpr a4 .32 16 0
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gpr a5 .32 20 0
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gpr a6 .32 24 0
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gpr a7 .32 28 0
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gpr a8 .32 32 0
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gpr a9 .32 36 0
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gpr sp .32 40 0
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gpr a10 .32 40 0
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gpr a11 .32 44 0
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gpr a12 .32 48 0
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gpr a13 .32 52 0
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gpr a14 .32 56 0
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gpr a15 .32 60 0
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# General-Purpose Data Registers (D0 - D15)
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gpr e0 .64 64 0
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gpr d0 .32 64 0
|
||||
gpr d1 .32 68 0
|
||||
gpr e2 .64 72 0
|
||||
gpr d2 .32 72 0
|
||||
gpr d3 .32 76 0
|
||||
gpr e4 .64 80 0
|
||||
gpr d4 .32 80 0
|
||||
gpr d5 .32 84 0
|
||||
gpr e6 .64 88 0
|
||||
gpr d6 .32 88 0
|
||||
gpr d7 .32 92 0
|
||||
gpr e8 .64 96 0
|
||||
gpr d8 .32 96 0
|
||||
gpr d9 .32 100 0
|
||||
gpr e10 .64 104 0
|
||||
gpr d10 .32 104 0
|
||||
gpr d11 .32 108 0
|
||||
gpr e12 .64 112 0
|
||||
gpr d12 .32 112 0
|
||||
gpr d13 .32 116 0
|
||||
gpr e14 .64 120 0
|
||||
gpr d14 .32 120 0
|
||||
gpr d15 .32 124 0
|
||||
# Special-Purpose Registers
|
||||
gpr PSW .32 128 0 # Program Status Word
|
||||
gpr PCXI .32 132 0 # Previous Context Information
|
||||
gpr FCX .32 136 0 # Free Context List Pointer
|
||||
gpr LCX .32 140 0 # Last Context Save Pointer
|
||||
gpr ISP .32 144 0 # Interrupt Stack Pointer
|
||||
gpr ICR .32 148 0 # Interrupt Control Register
|
||||
gpr PIPN .32 152 0 # Pending Interrupt Priority Number
|
||||
gpr BIV .32 156 0 # Base Interrupt Vector
|
||||
gpr BTV .32 160 0 # Base Trap Vector
|
||||
gpr pc .32 164 0 # Program Counter
|
||||
# System Control and Configuration Registers
|
||||
gpr SYSCON .32 168 0 # System Configuration Register
|
||||
gpr DCON2 .32 172 0 # Debug Control Register 2
|
||||
gpr CSP .32 176 0 # Context Save Pointer
|
||||
gpr MMUCON .32 180 0 # Memory Management Unit Control
|
||||
gpr CPU_ID .32 184 0 # CPU Identification Register
|
||||
gpr PSWEN .32 188 0 # Program Status Word Enable Register
|
||||
gpr CCUDR .32 192 0 # Cache Control Unit Debug Register
|
||||
gpr IECON .32 196 0 # Interrupt Enable Configuration Register
|
||||
gpr TRAPV .32 200 0 # Trap Vector Register
|
||||
gpr BBR .32 204 0 # Base Boundary Register (Optional, depending on use)
|
||||
gpr DBGSR .32 208 0 # Debug Status Register (Optional, depending on use)
|
||||
gpr PCON .32 212 0 # Peripheral Control Register (Optional, depending on use)
|
||||
|
||||
EOF
|
||||
RUN
|
||||
|
||||
Loading…
Reference in New Issue
Block a user