Magic-Mirror/radare2
1
0
Fork 0
mirror of https://github.com/radareorg/radare2.git synced 2025-02-26 09:06:02 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

Improve anal and parse plugins for Thumb ##anal (#14120)

Browse Source
This commit is contained in:
radare 2019-05-21 09:52:11 +02:00 committed by GitHub
parent fdcae93d3e
commit d73483ae0d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 21 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
libr/anal/p/anal_arm_cs.c
View File

@ -986,6 +986,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
break;
case ARM64_INS_ADD:
case ARM64_INS_ADC: // Add with carry.
//case ARM64_INS_ADCS: // Add with carry.
OPCALL("+");
break;
case ARM64_INS_SUB:
@ -1489,6 +1490,9 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
case ARM_INS_IT:
r_strbuf_appendf (&op->esil, "%d,pc,+=", op->fail);
break;
case ARM_INS_BKPT:
r_strbuf_setf (&op->esil, "%d,%d,TRAP", IMM (0), IMM (0));
break;
case ARM_INS_NOP:
r_strbuf_setf (&op->esil, ",");
break;
@ -1514,6 +1518,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
break;
case ARM_INS_ADDW:
case ARM_INS_ADD:
case ARM_INS_ADC:
MATH32("+");
break;
case ARM_INS_SSUB16:
@ -2350,6 +2355,7 @@ static void anop64 (csh handle, RAnalOp *op, cs_insn *insn) {
op->cycles = 1;
/* fallthru */
case ARM64_INS_ADC:
//case ARM64_INS_ADCS:
case ARM64_INS_UMADDL:
case ARM64_INS_SMADDL:
case ARM64_INS_FMADD:
@ -2722,6 +2728,10 @@ jmp $$ + 4 + ( [delta] * 2 )
op->fail = lookahead (handle, addr + insn->size, buf + insn->size, len - insn->size, distance);
break;
}
case ARM_INS_BKPT:
op->type = R_ANAL_OP_TYPE_TRAP;
op->cycles = 4;
break;
case ARM_INS_NOP:
op->type = R_ANAL_OP_TYPE_NOP;
op->cycles = 1;
@ -2767,6 +2777,7 @@ jmp $$ + 4 + ( [delta] * 2 )
op->type = R_ANAL_OP_TYPE_SUB;
break;
case ARM_INS_ADD:
case ARM_INS_ADC:
op->type = R_ANAL_OP_TYPE_ADD;
if (REGID(0) == ARM_REG_PC) {
op->type = R_ANAL_OP_TYPE_UJMP;
@ -2837,9 +2848,11 @@ jmp $$ + 4 + ( [delta] * 2 )
case ARM_INS_VMOV:
op->type = R_ANAL_OP_TYPE_MOV;
op->family = R_ANAL_OP_FAMILY_FPU;
op->cycles = 2;
break;
case ARM_INS_UDF:
op->type = R_ANAL_OP_TYPE_TRAP;
op->cycles = 4;
break;
case ARM_INS_SVC:
op->type = R_ANAL_OP_TYPE_SWI;
@ -2885,6 +2898,7 @@ jmp $$ + 4 + ( [delta] * 2 )
break;
case ARM_INS_PUSH:
case ARM_INS_STM:
case ARM_INS_STMDA:
case ARM_INS_STMDB:
op->type = R_ANAL_OP_TYPE_PUSH;
// 0x00008160 04202de5 str r2, [sp, -4]!

8
libr/parse/p/parse_arm_pseudo.c
View File

@ -56,11 +56,17 @@ static int replace(int argc, const char *argv[], char *newstr) {
{ 0, "tst", "if (# == #)", { 1, 2 } },
{ 0, "dvf", "# = # / #", { 1, 2, 3 } },
{ 0, "eor", "# = # ^ #", { 1, 2, 3 } },
{ 1, "bkpt", "breakpoint #", { 1 } },
{ 1, "udf", "undefined #", { 1 } },
{ 2, "sxtb", "# = (char) #", { 1, 2 } },
{ 2, "sxth", "# = (short) #", { 1, 2 } },
{ 0, "fdv", "# = # / #", { 1, 2, 3 } },
{ 0, "fml", "# = # * #", { 1, 2, 3 } },
{ 2, "ldr", "# = #", { 1, 2 } },
{ 2, "ldrh", "# = (word)#", { 1, 2 } },
{ 2, "ldrh", "# = (word) #", { 1, 2 } },
{ 3, "ldrh", "# = (word) # + #", { 1, 2, 3 } },
{ 2, "ldrb", "# = (byte) #", { 1, 2 } },
{ 3, "ldrb", "# = (byte) # + #", { 1, 2, 3 } },
{ 2, "ldrsb", "# = (byte) #", { 1, 2 } },
{ 2, "ldr.w", "# = #", { 1, 2 } },
{ 2, "ldrsw", "# = #", { 1, 2 } },