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Initial import of asm.tricore disassembler plugin

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This commit is contained in:
pancake 2016-01-30 02:47:17 +01:00
parent d30b2f4894
commit d7a244f010
13 changed files with 5352 additions and 1 deletions
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1
libr/asm/arch/include/dis-asm.h
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@ -225,6 +225,7 @@ typedef struct disassemble_info
target address. Return number of octets processed. */
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
extern int print_insn_tricore (bfd_vma, disassemble_info *);
extern int print_insn_aarch64 (bfd_vma, disassemble_info *);
extern int print_insn_alpha (bfd_vma, disassemble_info *);
extern int print_insn_avr (bfd_vma, disassemble_info *);

2
libr/asm/arch/include/mybfd.h
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@ -1999,6 +1999,8 @@ enum bfd_architecture
#define bfd_mach_xc16xs 3
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_tricore,
#define bfd_mach_tricore 4
bfd_arch_maxq, /* Dallas MAXQ 10/20 */
#define bfd_mach_maxq10 10
#define bfd_mach_maxq20 20

445
libr/asm/arch/include/opcode/tricore.h Normal file
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@ -0,0 +1,445 @@
/* Definitions dealing with TriCore/PCP opcodes and core registers.
Copyright (C) 1998-2003 Free Software Foundation, Inc.
Contributed by Michael Schumacher (mike@hightec-rt.com).
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
/* Supported TriCore and PCP instruction set architectures. */
typedef enum _tricore_opcode_arch_val
{
TRICORE_GENERIC = 0x00000000,
TRICORE_RIDER_A = 0x00000001,
TRICORE_RIDER_B = 0x00000002,
TRICORE_RIDER_D = TRICORE_RIDER_B,
TRICORE_V2 = 0x00000004,
TRICORE_PCP = 0x00000010,
TRICORE_PCP2 = 0x00000020
} tricore_isa;
#define bfd_mach_rider_a 0x0001
#define bfd_mach_rider_b 0x0002
#define bfd_mach_rider_c 0x0003
#define bfd_mach_rider_2 0x0004
#define bfd_mach_rider_d 0x0002
#define bfd_mach_rider_mask 0x000f
#define SEC_ARCH_BIT_0 0x008
/* Some handy definitions for upward/downward compatibility of insns. */
#define TRICORE_V2_UP TRICORE_V2
#define TRICORE_RIDER_D_UP (TRICORE_RIDER_D | TRICORE_V2_UP)
#define TRICORE_RIDER_B_UP (TRICORE_RIDER_B | TRICORE_RIDER_D_UP)
#define TRICORE_RIDER_B_DN TRICORE_RIDER_B
#define TRICORE_RIDER_D_DN (TRICORE_RIDER_D | TRICORE_RIDER_B_DN)
#define TRICORE_V2_DN (TRICORE_V2 | TRICORE_RIDER_D_DN)
/* The various instruction formats of the TriCore architecture. */
typedef enum _tricore_fmt
{
/* 32-bit formats */
TRICORE_FMT_ABS,
TRICORE_FMT_ABSB,
TRICORE_FMT_B,
TRICORE_FMT_BIT,
TRICORE_FMT_BO,
TRICORE_FMT_BOL,
TRICORE_FMT_BRC,
TRICORE_FMT_BRN,
TRICORE_FMT_BRR,
TRICORE_FMT_RC,
TRICORE_FMT_RCPW,
TRICORE_FMT_RCR,
TRICORE_FMT_RCRR,
TRICORE_FMT_RCRW,
TRICORE_FMT_RLC,
TRICORE_FMT_RR,
TRICORE_FMT_RR1,
TRICORE_FMT_RR2,
TRICORE_FMT_RRPW,
TRICORE_FMT_RRR,
TRICORE_FMT_RRR1,
TRICORE_FMT_RRR2,
TRICORE_FMT_RRRR,
TRICORE_FMT_RRRW,
TRICORE_FMT_SYS,
/* 16-bit formats */
TRICORE_FMT_SB,
TRICORE_FMT_SBC,
TRICORE_FMT_SBR,
TRICORE_FMT_SBRN,
TRICORE_FMT_SC,
TRICORE_FMT_SLR,
TRICORE_FMT_SLRO,
TRICORE_FMT_SR,
TRICORE_FMT_SRC,
TRICORE_FMT_SRO,
TRICORE_FMT_SRR,
TRICORE_FMT_SRRS,
TRICORE_FMT_SSR,
TRICORE_FMT_SSRO,
TRICORE_FMT_MAX /* Sentinel. */
} tricore_fmt;
#if defined(__STDC__) || defined(ALMOST_STDC)
# define F(x) TRICORE_FMT_ ## x
#else
# define F(x) TRICORE_FMT_/**/x
#endif
/* Opcode masks for the instruction formats above. */
extern unsigned long tricore_mask_abs;
extern unsigned long tricore_mask_absb;
extern unsigned long tricore_mask_b;
extern unsigned long tricore_mask_bit;
extern unsigned long tricore_mask_bo;
extern unsigned long tricore_mask_bol;
extern unsigned long tricore_mask_brc;
extern unsigned long tricore_mask_brn;
extern unsigned long tricore_mask_brr;
extern unsigned long tricore_mask_rc;
extern unsigned long tricore_mask_rcpw;
extern unsigned long tricore_mask_rcr;
extern unsigned long tricore_mask_rcrr;
extern unsigned long tricore_mask_rcrw;
extern unsigned long tricore_mask_rlc;
extern unsigned long tricore_mask_rr;
extern unsigned long tricore_mask_rr1;
extern unsigned long tricore_mask_rr2;
extern unsigned long tricore_mask_rrpw;
extern unsigned long tricore_mask_rrr;
extern unsigned long tricore_mask_rrr1;
extern unsigned long tricore_mask_rrr2;
extern unsigned long tricore_mask_rrrr;
extern unsigned long tricore_mask_rrrw;
extern unsigned long tricore_mask_sys;
extern unsigned long tricore_mask_sb;
extern unsigned long tricore_mask_sbc;
extern unsigned long tricore_mask_sbr;
extern unsigned long tricore_mask_sbrn;
extern unsigned long tricore_mask_sc;
extern unsigned long tricore_mask_slr;
extern unsigned long tricore_mask_slro;
extern unsigned long tricore_mask_sr;
extern unsigned long tricore_mask_src;
extern unsigned long tricore_mask_sro;
extern unsigned long tricore_mask_srr;
extern unsigned long tricore_mask_srrs;
extern unsigned long tricore_mask_ssr;
extern unsigned long tricore_mask_ssro;
extern unsigned long tricore_opmask[];
extern void tricore_init_arch_vars PARAMS ((unsigned long));
/* This structure describes TriCore opcodes. */
struct tricore_opcode
{
const char *name; /* The opcode's mnemonic name. */
const int len32; /* 1 if it's a 32-bit insn. */
const unsigned long opcode; /* The binary code of this opcode. */
const unsigned long lose; /* Mask for bits that must not be set. */
const tricore_fmt format; /* The instruction format. */
const int nr_operands; /* The number of operands. */
const unsigned char *args; /* Kinds of operands (see below). */
const unsigned char *fields; /* Where to put the operands (see below). */
const tricore_isa isa; /* Instruction set architecture. */
int insind; /* The insn's index (computed at runtime). */
int inslast; /* Index of last insn w/ that name (dito). */
};
extern struct tricore_opcode tricore_opcodes[];
extern const int tricore_numopcodes;
extern unsigned long tricore_opmask[];
/* This structure describes PCP/PCP2 opcodes. */
struct pcp_opcode
{
const char *name; /* The opcode's mnemonic name. */
const int len32; /* 1 if it's a 32-bit insn. */
const unsigned long opcode; /* The binary code of this opcode. */
const unsigned long lose; /* Mask for bits that must not be set. */
const int fmt_group; /* The group ID of the instruction format. */
const int ooo; /* 1 if operands may be given out of order. */
const int nr_operands; /* The number of operands. */
const unsigned char *args; /* Kinds of operands (see below), */
const tricore_isa isa; /* PCP instruction set architecture. */
int insind; /* The insn's index (computed at runtime). */
int inslast; /* Index of last insn w/ that name (dito). */
};
extern struct pcp_opcode pcp_opcodes[];
extern const int pcp_numopcodes;
/* This structure describes TriCore core registers (SFRs). */
struct tricore_core_register
{
const char *name; /* The name of the register ($-prepended). */
const unsigned long addr; /* The memory address of the register. */
const tricore_isa isa; /* Instruction set architecture. */
};
extern const struct tricore_core_register tricore_sfrs[];
extern const int tricore_numsfrs;
/* Kinds of operands for TriCore instructions:
d A simple data register (%d0-%d15).
g A simple data register with an 'l' suffix.
G A simple data register with an 'u' suffix.
- A simple data register with an 'll' suffix.
+ A simple data register with an 'uu' suffix.
l A simple data register with an 'lu' suffix.
L A simple data register with an 'ul' suffix.
D An extended data register (d-register pair; %e0, %e2, ..., %e14).
i Implicit data register %d15.
a A simple address register (%a0-%a15).
A An extended address register (a-register pair; %a0, %a2, ..., %a14).
I Implicit address register %a15.
P Implicit stack register %a10.
c A core register ($psw, $pc etc.).
1 A 1-bit zero-extended constant.
2 A 2-bit zero-extended constant.
3 A 3-bit zero-extended constant.
4 A 4-bit sign-extended constant.
f A 4-bit zero-extended constant.
5 A 5-bit zero-extended constant.
F A 5-bit sign-extended constant.
v A 5-bit zero-extended constant with bit 0 == 0 (=> 4bit/2).
6 A 6-bit zero-extended constant with bits 0,1 == 0 (=> 4bit/4).
8 A 8-bit zero-extended constant.
9 A 9-bit sign-extended constant.
n A 9-bit zero-extended constant.
k A 10-bit zero-extended constant with bits 0,1 == 0 (=> 8bit/4).
0 A 10-bit sign-extended constant.
q A 15-bit zero-extended constant.
w A 16-bit sign-extended constant.
W A 16-bit zero-extended constant.
M A 32-bit memory address.
m A 4-bit PC-relative offset (zero-extended, /2).
r A 4-bit PC-relative offset (one-extended, /2).
x A 5-bit PC-relative offset (zero-extended, /2).
R A 8-bit PC-relative offset (sign-extended, /2).
o A 15-bit PC-relative offset (sign-extended, /2).
O A 24-bit PC-relative offset (sign-extended, /2).
t A 18-bit absolute memory address (segmented).
T A 24-bit absolute memory address (segmented, /2).
U A symbol whose value isn't known yet.
@ Register indirect ([%an]).
& SP indirect ([%sp] or [%a10]).
< Pre-incremented register indirect ([+%an]).
> Post-incremented register indirect ([%an+]).
* Circular address mode ([%An+c]).
# Bitreverse address mode ([%An+r]).
? Indexed address mode ([%An+i]).
S Implicit base ([%a15]).
*/
/* The instruction fields where operands are stored. */
#define FMT_ABS_NONE '0'
#define FMT_ABS_OFF18 '1'
#define FMT_ABS_S1_D '2'
#define FMT_ABSB_NONE '0'
#define FMT_ABSB_OFF18 '1'
#define FMT_ABSB_B '2'
#define FMT_ABSB_BPOS3 '3'
#define FMT_B_NONE '0'
#define FMT_B_DISP24 '1'
#define FMT_BIT_NONE '0'
#define FMT_BIT_D '1'
#define FMT_BIT_P2 '2'
#define FMT_BIT_P1 '3'
#define FMT_BIT_S2 '4'
#define FMT_BIT_S1 '5'
#define FMT_BO_NONE '0'
#define FMT_BO_OFF10 '1'
#define FMT_BO_S2 '2'
#define FMT_BO_S1_D '3'
#define FMT_BOL_NONE '0'
#define FMT_BOL_OFF16 '1'
#define FMT_BOL_S2 '2'
#define FMT_BOL_S1_D '3'
#define FMT_BRC_NONE '0'
#define FMT_BRC_DISP15 '1'
#define FMT_BRC_CONST4 '2'
#define FMT_BRC_S1 '3'
#define FMT_BRN_NONE '0'
#define FMT_BRN_DISP15 '1'
#define FMT_BRN_N '2'
#define FMT_BRN_S1 '3'
#define FMT_BRR_NONE '0'
#define FMT_BRR_DISP15 '1'
#define FMT_BRR_S2 '2'
#define FMT_BRR_S1 '3'
#define FMT_RC_NONE '0'
#define FMT_RC_D '1'
#define FMT_RC_CONST9 '2'
#define FMT_RC_S1 '3'
#define FMT_RCPW_NONE '0'
#define FMT_RCPW_D '1'
#define FMT_RCPW_P '2'
#define FMT_RCPW_W '3'
#define FMT_RCPW_CONST4 '4'
#define FMT_RCPW_S1 '5'
#define FMT_RCR_NONE '0'
#define FMT_RCR_D '1'
#define FMT_RCR_S3 '2'
#define FMT_RCR_CONST9 '3'
#define FMT_RCR_S1 '4'
#define FMT_RCRR_NONE '0'
#define FMT_RCRR_D '1'
#define FMT_RCRR_S3 '2'
#define FMT_RCRR_CONST4 '3'
#define FMT_RCRR_S1 '4'
#define FMT_RCRW_NONE '0'
#define FMT_RCRW_D '1'
#define FMT_RCRW_S3 '2'
#define FMT_RCRW_W '3'
#define FMT_RCRW_CONST4 '4'
#define FMT_RCRW_S1 '5'
#define FMT_RLC_NONE '0'
#define FMT_RLC_D '1'
#define FMT_RLC_CONST16 '2'
#define FMT_RLC_S1 '3'
#define FMT_RR_NONE '0'
#define FMT_RR_D '1'
#define FMT_RR_N '2'
#define FMT_RR_S2 '3'
#define FMT_RR_S1 '4'
#define FMT_RR1_NONE '0'
#define FMT_RR1_D '1'
#define FMT_RR1_N '2'
#define FMT_RR1_S2 '3'
#define FMT_RR1_S1 '4'
#define FMT_RR2_NONE '0'
#define FMT_RR2_D '1'
#define FMT_RR2_S2 '2'
#define FMT_RR2_S1 '3'
#define FMT_RRPW_NONE '0'
#define FMT_RRPW_D '1'
#define FMT_RRPW_P '2'
#define FMT_RRPW_W '3'
#define FMT_RRPW_S2 '4'
#define FMT_RRPW_S1 '5'
#define FMT_RRR_NONE '0'
#define FMT_RRR_D '1'
#define FMT_RRR_S3 '2'
#define FMT_RRR_N '3'
#define FMT_RRR_S2 '4'
#define FMT_RRR_S1 '5'
#define FMT_RRR1_NONE '0'
#define FMT_RRR1_D '1'
#define FMT_RRR1_S3 '2'
#define FMT_RRR1_N '3'
#define FMT_RRR1_S2 '4'
#define FMT_RRR1_S1 '5'
#define FMT_RRR2_NONE '0'
#define FMT_RRR2_D '1'
#define FMT_RRR2_S3 '2'
#define FMT_RRR2_S2 '3'
#define FMT_RRR2_S1 '4'
#define FMT_RRRR_NONE '0'
#define FMT_RRRR_D '1'
#define FMT_RRRR_S3 '2'
#define FMT_RRRR_S2 '3'
#define FMT_RRRR_S1 '4'
#define FMT_RRRW_NONE '0'
#define FMT_RRRW_D '1'
#define FMT_RRRW_S3 '2'
#define FMT_RRRW_W '3'
#define FMT_RRRW_S2 '4'
#define FMT_RRRW_S1 '5'
#define FMT_SYS_NONE '0'
#define FMT_SYS_S1_D '1'
#define FMT_SB_NONE '0'
#define FMT_SB_DISP8 '1'
#define FMT_SBC_NONE '0'
#define FMT_SBC_CONST4 '1'
#define FMT_SBC_DISP4 '2'
#define FMT_SBR_NONE '0'
#define FMT_SBR_S2 '1'
#define FMT_SBR_DISP4 '2'
#define FMT_SBRN_NONE '0'
#define FMT_SBRN_N '1'
#define FMT_SBRN_DISP4 '2'
#define FMT_SC_NONE '0'
#define FMT_SC_CONST8 '1'
#define FMT_SLR_NONE '0'
#define FMT_SLR_S2 '1'
#define FMT_SLR_D '2'
#define FMT_SLRO_NONE '0'
#define FMT_SLRO_OFF4 '1'
#define FMT_SLRO_D '2'
#define FMT_SR_NONE '0'
#define FMT_SR_S1_D '1'
#define FMT_SRC_NONE '0'
#define FMT_SRC_CONST4 '1'
#define FMT_SRC_S1_D '2'
#define FMT_SRO_NONE '0'
#define FMT_SRO_S2 '1'
#define FMT_SRO_OFF4 '2'
#define FMT_SRR_NONE '0'
#define FMT_SRR_S2 '1'
#define FMT_SRR_S1_D '2'
#define FMT_SRRS_NONE '0'
#define FMT_SRRS_S2 '1'
#define FMT_SRRS_S1_D '2'
#define FMT_SRRS_N '3'
#define FMT_SSR_NONE '0'
#define FMT_SSR_S2 '1'
#define FMT_SSR_S1 '2'
#define FMT_SSRO_NONE '0'
#define FMT_SSRO_OFF4 '1'
#define FMT_SSRO_S1 '2'
/* Kinds of operands for PCP instructions:
a Condition code 0-7 (CONDCA).
b Condition code 8-15 (CONDCB).
c CNC=[0,1,2].
d DST{+,-}.
e A constant expression.
E An indirect constant expression.
f SIZE=[8,16,32].
g ST=[0,1].
h EC=[0,1].
i INT=[0,1].
j EP=[0,1].
k SET (const value 1).
l CLR (const value 0).
m DAC=[0,1].
n CNT0=[1..8] for COPY, or [2,4,8] for BCOPY.
o RTA=[0,1].
p EDA=[0,1].
q SDB=[0,1].
r A direct register (R0-R7).
R An indirect register ([R0]-[R7]).
s SRC{+,-}.
u A direct symbol whose value isn't known yet.
U An indirect symbol whose value isn't known yet.
*/
/* End of tricore.h. */

2
libr/asm/arch/tricore/README.md Normal file
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@ -0,0 +1,2 @@
Based on code from https://www.hightec-rt.com/en/downloads/sources/14-sources-for-tricore-v3-3-7-9-binutils-1.html

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libr/asm/arch/tricore/gnu/cpu-tricore.c Normal file
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@ -0,0 +1,318 @@
/* BFD support for Infineon's TriCore architecture.
Copyright (C) 1998-2003 Free Software Foundation, Inc.
Contributed by Michael Schumacher (mike@hightec-rt.com).
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include <string.h>
#include <sys/types.h>
#include <stdbool.h>
//#include "bfd.h"
#include "sysdep.h"
#include "dis-asm.h"
//#include "libbfd.h"
#include "opcode/tricore.h"
/* Opcode masks for TriCore's various instruction formats. */
unsigned long tricore_mask_abs;
unsigned long tricore_mask_absb;
unsigned long tricore_mask_b;
unsigned long tricore_mask_bit;
unsigned long tricore_mask_bo;
unsigned long tricore_mask_bol;
unsigned long tricore_mask_brc;
unsigned long tricore_mask_brn;
unsigned long tricore_mask_brr;
unsigned long tricore_mask_rc;
unsigned long tricore_mask_rcpw;
unsigned long tricore_mask_rcr;
unsigned long tricore_mask_rcrr;
unsigned long tricore_mask_rcrw;
unsigned long tricore_mask_rlc;
unsigned long tricore_mask_rr;
unsigned long tricore_mask_rr1;
unsigned long tricore_mask_rr2;
unsigned long tricore_mask_rrpw;
unsigned long tricore_mask_rrr;
unsigned long tricore_mask_rrr1;
unsigned long tricore_mask_rrr2;
unsigned long tricore_mask_rrrr;
unsigned long tricore_mask_rrrw;
unsigned long tricore_mask_sys;
unsigned long tricore_mask_sb;
unsigned long tricore_mask_sbc;
unsigned long tricore_mask_sbr;
unsigned long tricore_mask_sbrn;
unsigned long tricore_mask_sc;
unsigned long tricore_mask_slr;
unsigned long tricore_mask_slro;
unsigned long tricore_mask_sr;
unsigned long tricore_mask_src;
unsigned long tricore_mask_sro;
unsigned long tricore_mask_srr;
unsigned long tricore_mask_srrs;
unsigned long tricore_mask_ssr;
unsigned long tricore_mask_ssro;
unsigned long tricore_opmask[TRICORE_FMT_MAX];
int
bfd_default_scan (info, string)
const bfd_arch_info_type *info;
const char *string;
{
return true;
}
const bfd_arch_info_type *
bfd_default_compatible (a, b)
const bfd_arch_info_type *a;
const bfd_arch_info_type *b;
{
if (a->arch != b->arch)
return NULL;
if (a->bits_per_word != b->bits_per_word)
return NULL;
if (a->mach > b->mach)
return a;
if (b->mach > a->mach)
return b;
return a;
}
void tricore_init_arch_vars PARAMS ((unsigned long));
/* Describe the various flavours of the TriCore architecture. */
static const bfd_arch_info_type arch_info_struct[] =
{
/* Rider-A ISA. */
{
32, /* 32 bits per word. */
32, /* 32 bits per address. */
8, /* 8 bits per byte. */
bfd_arch_tricore, /* Architecture type. */
bfd_mach_rider_a, /* Machine type. */
"tricore", /* Name of architecture (internal use). */
"TriCore:Rider-A", /* Name of architecture to print. */
3, /* Align sections on 8 byte boundaries. */
false, /* No, this is ain't the default arch type. */
bfd_default_compatible, /* We're compatible with ourselves. */
bfd_default_scan, /* Let BFD find the default arch. */
&arch_info_struct[1] /* Next TriCore architecture. */
},
/* Rider-D ISA. */
{
32, /* 32 bits per word. */
32, /* 32 bits per address. */
8, /* 8 bits per byte. */
bfd_arch_tricore, /* Architecture type. */
bfd_mach_rider_d, /* Machine type. */
"tricore", /* Name of architecture (internal use). */
"TriCore:Rider-D", /* Name of architecture to print. */
3, /* Align sections on 8 byte boundaries. */
false, /* No, this is ain't the default arch type. */
bfd_default_compatible, /* We're compatible with ourselves. */
bfd_default_scan, /* Let BFD find the default arch. */
&arch_info_struct[2] /* Next TriCore architecture. */
},
/* TriCore V2 ISA. */
{
32, /* 32 bits per word. */
32, /* 32 bits per address. */
8, /* 8 bits per byte. */
bfd_arch_tricore, /* Architecture type. */
bfd_mach_rider_2, /* Machine type. */
"tricore", /* Name of architecture (internal use). */
"TriCore:V2", /* Name of architecture to print. */
3, /* Align sections on 8 byte boundaries. */
false, /* No, this is ain't the default arch type. */
bfd_default_compatible, /* We're compatible with ourselves. */
bfd_default_scan, /* Let BFD find the default arch. */
(bfd_arch_info_type *) 0 /* No more arch types for TriCore. */
}
};
const bfd_arch_info_type bfd_tricore_arch =
{
/* Rider-B ISA. */
32, /* 32 bits per word. */
32, /* 32 bits per address. */
8, /* 8 bits per byte. */
bfd_arch_tricore, /* Architecture type. */
bfd_mach_rider_b, /* Machine type. */
"tricore", /* Name of architecture (internal use). */
"TriCore:Rider-B", /* Name of architecture to print. */
3, /* Align sections on 8 byte boundaries. */
true, /* Yes, this is the default arch type. */
bfd_default_compatible, /* We're compatible with ourselves. */
bfd_default_scan, /* Let BFD find the default arch. */
&arch_info_struct[0] /* Next arch type for TriCore. */
};
/* Initialize the architecture-specific variables. This must be called
by the assembler and disassembler prior to encoding/decoding any
TriCore instructions; the linker (or more precisely, the specific
back-end, bfd/elf32-tricore.c:tricore_elf32_relocate_section) will
also have to call this if it ever accesses the variables below, but
it currently doesn't. */
void
tricore_init_arch_vars (mach)
unsigned long mach;
{
switch (mach & bfd_mach_rider_mask)
{
case bfd_mach_rider_a:
tricore_mask_abs = 0x0c0000ff;
tricore_mask_absb = 0x0c0000ff;
tricore_mask_b = 0x000000ff;
tricore_mask_bit = 0x006000ff;
tricore_mask_bo = 0x0fc000ff;
tricore_mask_bol = 0x000000ff;
tricore_mask_brc = 0x800000ff;
tricore_mask_brn = 0x8000007f;
tricore_mask_brr = 0x800000ff;
tricore_mask_rc = 0x0fe000ff;
tricore_mask_rcpw = 0x006000ff;
tricore_mask_rcr = 0x00e000ff;
tricore_mask_rcrr = 0x00e000ff;
tricore_mask_rcrw = 0x00e000ff;
tricore_mask_rlc = 0x000000ff;
tricore_mask_rr = 0x0ff000ff;
tricore_mask_rrpw = 0x006000ff;
tricore_mask_rrr = 0x00f000ff;
tricore_mask_rrr1 = 0x00fc00ff;
tricore_mask_rrr2 = 0x00ff00ff;
tricore_mask_rrrr = 0x00e000ff;
tricore_mask_rrrw = 0x00e000ff;
tricore_mask_sys = 0x07c000ff;
tricore_mask_sb = 0x00ff;
tricore_mask_sbc = 0x00ff;
tricore_mask_sbr = 0x00ff;
tricore_mask_sbrn = 0x007f;
tricore_mask_sc = 0x00ff;
tricore_mask_slr = 0x00ff;
tricore_mask_slro = 0x00ff;
tricore_mask_sr = 0xf0ff;
tricore_mask_src = 0x00ff;
tricore_mask_sro = 0x00ff;
tricore_mask_srr = 0x00ff;
tricore_mask_srrs = 0x003f;
tricore_mask_ssr = 0x00ff;
tricore_mask_ssro = 0x00ff;
break;
case bfd_mach_rider_b: /* Same as bfd_mach_rider_d! */
case bfd_mach_rider_2:
tricore_mask_abs = 0x0c0000ff;
tricore_mask_absb = 0x0c0000ff;
tricore_mask_b = 0x000000ff;
tricore_mask_bit = 0x006000ff;
tricore_mask_bo = 0x0fc000ff;
tricore_mask_bol = 0x000000ff;
tricore_mask_brc = 0x800000ff;
tricore_mask_brn = 0x8000007f;
tricore_mask_brr = 0x800000ff;
tricore_mask_rc = 0x0fe000ff;
tricore_mask_rcpw = 0x006000ff;
tricore_mask_rcr = 0x00e000ff;
tricore_mask_rcrr = 0x00e000ff;
tricore_mask_rcrw = 0x00e000ff;
tricore_mask_rlc = 0x000000ff;
tricore_mask_rr = 0x0ff300ff;
tricore_mask_rr1 = 0x0ffc00ff;
tricore_mask_rr2 = 0x0fff00ff;
tricore_mask_rrpw = 0x006000ff;
tricore_mask_rrr = 0x00f300ff;
tricore_mask_rrr1 = 0x00fc00ff;
tricore_mask_rrr2 = 0x00ff00ff;
tricore_mask_rrrr = 0x00e000ff;
tricore_mask_rrrw = 0x00e000ff;
if ((mach & bfd_mach_rider_mask) == bfd_mach_rider_2)
tricore_mask_sys = 0x0fc000ff;
else
tricore_mask_sys = 0x07c000ff;
tricore_mask_sb = 0x00ff;
tricore_mask_sbc = 0x00ff;
tricore_mask_sbr = 0x00ff;
tricore_mask_sbrn = 0x00ff;
tricore_mask_sc = 0x00ff;
tricore_mask_slr = 0x00ff;
tricore_mask_slro = 0x00ff;
tricore_mask_sr = 0xf0ff;
tricore_mask_src = 0x00ff;
tricore_mask_sro = 0x00ff;
tricore_mask_srr = 0x00ff;
tricore_mask_srrs = 0x003f;
tricore_mask_ssr = 0x00ff;
tricore_mask_ssro = 0x00ff;
break;
}
/* Now fill in tricore_opmask[]. */
tricore_opmask[TRICORE_FMT_ABS] = tricore_mask_abs;
tricore_opmask[TRICORE_FMT_ABSB] = tricore_mask_absb;
tricore_opmask[TRICORE_FMT_B] = tricore_mask_b;
tricore_opmask[TRICORE_FMT_BIT] = tricore_mask_bit;
tricore_opmask[TRICORE_FMT_BO] = tricore_mask_bo;
tricore_opmask[TRICORE_FMT_BOL] = tricore_mask_bol;
tricore_opmask[TRICORE_FMT_BRC] = tricore_mask_brc;
tricore_opmask[TRICORE_FMT_BRN] = tricore_mask_brn;
tricore_opmask[TRICORE_FMT_BRR] = tricore_mask_brr;
tricore_opmask[TRICORE_FMT_RC] = tricore_mask_rc;
tricore_opmask[TRICORE_FMT_RCPW] = tricore_mask_rcpw;
tricore_opmask[TRICORE_FMT_RCR] = tricore_mask_rcr;
tricore_opmask[TRICORE_FMT_RCRR] = tricore_mask_rcrr;
tricore_opmask[TRICORE_FMT_RCRW] = tricore_mask_rcrw;
tricore_opmask[TRICORE_FMT_RLC] = tricore_mask_rlc;
tricore_opmask[TRICORE_FMT_RR] = tricore_mask_rr;
tricore_opmask[TRICORE_FMT_RR1] = tricore_mask_rr1;
tricore_opmask[TRICORE_FMT_RR2] = tricore_mask_rr2;
tricore_opmask[TRICORE_FMT_RRPW] = tricore_mask_rrpw;
tricore_opmask[TRICORE_FMT_RRR] = tricore_mask_rrr;
tricore_opmask[TRICORE_FMT_RRR1] = tricore_mask_rrr1;
tricore_opmask[TRICORE_FMT_RRR2] = tricore_mask_rrr2;
tricore_opmask[TRICORE_FMT_RRRR] = tricore_mask_rrrr;
tricore_opmask[TRICORE_FMT_RRRW] = tricore_mask_rrrw;
tricore_opmask[TRICORE_FMT_SYS] = tricore_mask_sys;
tricore_opmask[TRICORE_FMT_SB] = tricore_mask_sb;
tricore_opmask[TRICORE_FMT_SBC] = tricore_mask_sbc;
tricore_opmask[TRICORE_FMT_SBR] = tricore_mask_sbr;
tricore_opmask[TRICORE_FMT_SBRN] = tricore_mask_sbrn;
tricore_opmask[TRICORE_FMT_SC] = tricore_mask_sc;
tricore_opmask[TRICORE_FMT_SLR] = tricore_mask_slr;
tricore_opmask[TRICORE_FMT_SLRO] = tricore_mask_slro;
tricore_opmask[TRICORE_FMT_SR] = tricore_mask_sr;
tricore_opmask[TRICORE_FMT_SRC] = tricore_mask_src;
tricore_opmask[TRICORE_FMT_SRO] = tricore_mask_sro;
tricore_opmask[TRICORE_FMT_SRR] = tricore_mask_srr;
tricore_opmask[TRICORE_FMT_SRRS] = tricore_mask_srrs;
tricore_opmask[TRICORE_FMT_SSR] = tricore_mask_ssr;
tricore_opmask[TRICORE_FMT_SSRO] = tricore_mask_ssro;
}
/* End of cpu-tricore.c. */

1923
libr/asm/arch/tricore/gnu/tricore-dis.c Normal file
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File diff suppressed because it is too large Load Diff

2514
libr/asm/arch/tricore/gnu/tricore-opc.c Normal file
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File diff suppressed because it is too large Load Diff

4
libr/asm/arch/xtensa/gnu/xtensa-isa.c
View File

@ -19,6 +19,9 @@
MA 02110-1301, USA. */
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "dis-asm.h"
#include "sysdep.h"
//#include "bfd.h"
@ -26,6 +29,7 @@
#include "xtensa-isa.h"
#include "xtensa-isa-internal.h"
extern int filename_cmp (const char *s1, const char *s2);
xtensa_isa_status xtisa_errno;
char xtisa_error_msg[1024];

126
libr/asm/p/asm_tricore.c Normal file
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@ -0,0 +1,126 @@
/* radare2 - LGPL - Copyright 2016 - pancake */
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <r_types.h>
#include <r_lib.h>
#include <r_util.h>
#include <r_asm.h>
#include "dis-asm.h"
static unsigned long Offset = 0;
static char *buf_global = NULL;
static unsigned char bytes[32];
static int tricore_buffer_read_memory (bfd_vma memaddr, bfd_byte *myaddr, ut32 length, struct disassemble_info *info) {
memcpy (myaddr, bytes, length);
return 0;
}
static int symbol_at_address(bfd_vma addr, struct disassemble_info * info) {
return 0;
}
static void memory_error_func(int status, bfd_vma memaddr, struct disassemble_info *info) {
//--
}
static void print_address(bfd_vma address, struct disassemble_info *info) {
char tmp[64];
if (buf_global == NULL) {
return;
}
sprintf(tmp, "0x%08"PFMT64x, (ut64)address);
strcat(buf_global, tmp);
}
static int buf_fprintf(void *stream, const char *format, ...) {
int flen, glen;
char *escaped = NULL;
va_list ap;
char *tmp;
va_start (ap, format);
if (buf_global == NULL) {
return 0;
}
flen = strlen (format);
glen = strlen (buf_global);
tmp = malloc (flen + glen + 2);
if (tmp) {
if (strchr (buf_global, '%')) {
char *buf_local = strdup (buf_global);
escaped = r_str_replace (buf_local, "%", "%%", true);
} else {
escaped = strdup (buf_global);
}
glen = strlen (escaped);
}
if (escaped) {
memcpy (tmp, escaped, glen);
memcpy (tmp+glen, format, flen);
tmp[flen+glen] = 0;
free (escaped);
/* this code can produce a buffer overflow or a format string */
#define IN_CASE_OF_SEGFAULT 0
#if IN_CASE_OF_SEGFAULT
strcpy (buf_global, tmp);
#else
vsprintf (buf_global, tmp, ap);
#endif
free (tmp);
va_end (ap);
return 0;
}
va_end (ap);
return -1;
}
static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
struct disassemble_info disasm_obj;
buf_global = op->buf_asm;
Offset = a->pc;
memcpy (bytes, buf, R_MIN (len, 8)); // TODO handle thumb
/* prepare disassembler */
memset (&disasm_obj, '\0', sizeof (struct disassemble_info));
disasm_obj.disassembler_options=(a->bits==64)?"64":"";
disasm_obj.buffer = bytes;
disasm_obj.read_memory_func = &tricore_buffer_read_memory;
disasm_obj.symbol_at_address_func = &symbol_at_address;
disasm_obj.memory_error_func = &memory_error_func;
disasm_obj.print_address_func = &print_address;
disasm_obj.endian = !a->big_endian;
disasm_obj.fprintf_func = &buf_fprintf;
disasm_obj.stream = stdout;
disasm_obj.mach = 2; // select CPU TYPE
op->size = print_insn_tricore ((bfd_vma)Offset, &disasm_obj);
if (op->size == -1)
strncpy (op->buf_asm, " (data)", R_ASM_BUFSIZE);
return op->size;
}
RAsmPlugin r_asm_plugin_tricore = {
.name = "tricore",
.arch = "tricore",
.license = "GPL3",
.bits = 32,
.desc = "TriCore CPU",
.disassemble = &disassemble,
0
};
#ifndef CORELIB
struct r_lib_struct_t radare_plugin = {
.type = R_LIB_TYPE_ASM,
.data = &r_asm_plugin_tricore,
.version = R2_VERSION
};
#endif

2
libr/asm/p/asm_xtensa.c
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@ -87,7 +87,7 @@ RAsmPlugin r_asm_plugin_xtensa = {
.name = "xtensa",
.arch = "xtensa",
.license = "GPL3",
.bits = 32 | 64,
.bits = 32,
.desc = "XTensa CPU",
.disassemble = &disassemble,
0

14
libr/asm/p/tricore.mk Normal file
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@ -0,0 +1,14 @@
OBJ_TRICORE=asm_tricore.o
OBJ_TRICORE+=../arch/tricore/gnu/tricore-dis.o
OBJ_TRICORE+=../arch/tricore/gnu/tricore-opc.o
OBJ_TRICORE+=../arch/tricore/gnu/cpu-tricore.o
STATIC_OBJ+=${OBJ_TRICORE}
TARGET_TRICORE=asm_tricore.${EXT_SO}
ifeq ($(WITHPIC),1)
ALL_TARGETS+=${TARGET_TRICORE}
${TARGET_TRICORE}: ${OBJ_TRICORE}
${CC} $(call libname,asm_tricore) ${LDFLAGS} ${CFLAGS} -o asm_tricore.${EXT_SO} ${OBJ_TRICORE}
endif

1
libr/include/r_asm.h
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@ -223,6 +223,7 @@ extern RAsmPlugin r_asm_plugin_lm32;
extern RAsmPlugin r_asm_plugin_riscv;
extern RAsmPlugin r_asm_plugin_vax;
extern RAsmPlugin r_asm_plugin_xtensa;
extern RAsmPlugin r_asm_plugin_tricore;
#endif
#ifdef __cplusplus

1
plugins.def.cfg
View File

@ -62,6 +62,7 @@ asm.i4004
asm.i8080
asm.java
asm.lm32
asm.tricore
asm.xtensa
asm.m68k
asm.m68k_cs