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Extend arm64 regprofile for 16 and 8bit registers
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parent
bf6f4c5477
commit
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@ -9,19 +9,19 @@
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#define IMM64(x) insn->detail->arm64.operands[x].imm
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/* arm32 */
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#define REG(x) cs_reg_name (*handle, insn->detail->arm.operands[x].reg)
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#define REG64(x) cs_reg_name (*handle, insn->detail->arm64.operands[x].reg)
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#define REG(x) r_str_get (cs_reg_name (*handle, insn->detail->arm.operands[x].reg))
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#define REG64(x) r_str_get (cs_reg_name (*handle, insn->detail->arm64.operands[x].reg))
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#define REGID64(x) insn->detail->arm64.operands[x].reg
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#define REGID(x) insn->detail->arm.operands[x].reg
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#define IMM(x) (ut32)(insn->detail->arm.operands[x].imm)
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#define IMM64(x) insn->detail->arm64.operands[x].imm
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#define MEMBASE(x) cs_reg_name(*handle, insn->detail->arm.operands[x].mem.base)
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#define MEMBASE64(x) cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.base)
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#define MEMBASE(x) r_str_get (cs_reg_name(*handle, insn->detail->arm.operands[x].mem.base))
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#define MEMBASE64(x) r_str_get (cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.base))
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#define REGBASE(x) insn->detail->arm.operands[x].mem.base
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#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base
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// s/index/base|reg/
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#define MEMINDEX(x) cs_reg_name(*handle, insn->detail->arm.operands[x].mem.index)
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#define MEMINDEX64(x) cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.index)
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#define MEMINDEX(x) r_str_get (cs_reg_name(*handle, insn->detail->arm.operands[x].mem.index))
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#define MEMINDEX64(x) r_str_get (cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.index))
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#define HASMEMINDEX64(x) insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID
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#define MEMDISP(x) insn->detail->arm.operands[x].mem.disp
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#define MEMDISP64(x) insn->detail->arm64.operands[x].mem.disp
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@ -145,13 +145,13 @@ static const char *arg(RAnal *a, csh *handle, cs_insn *insn, char *buf, int n) {
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if (ISSHIFTED (n)) {
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sprintf (buf, "%u,%s,%s",
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LSHIFT2 (n),
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cs_reg_name (*handle,
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insn->detail->arm.operands[n].reg),
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r_str_get (cs_reg_name (*handle,
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insn->detail->arm.operands[n].reg)),
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DECODE_SHIFT (n));
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} else {
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sprintf (buf, "%s",
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cs_reg_name (*handle,
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insn->detail->arm.operands[n].reg));
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r_str_get (cs_reg_name (*handle,
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insn->detail->arm.operands[n].reg)));
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}
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break;
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case ARM_OP_IMM:
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@ -1451,6 +1451,72 @@ static char *get_reg_profile(RAnal *anal) {
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"=CF cf\n"
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"=SN x0\n"
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/* 8bit sub-registers */
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"gpr b0 .8 0 0\n"
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"gpr b1 .8 8 0\n"
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"gpr b2 .8 16 0\n"
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"gpr b3 .8 24 0\n"
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"gpr b4 .8 32 0\n"
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"gpr b5 .8 40 0\n"
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"gpr b6 .8 48 0\n"
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"gpr b7 .8 56 0\n"
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"gpr b8 .8 64 0\n"
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"gpr b9 .8 72 0\n"
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"gpr b10 .8 80 0\n"
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"gpr b11 .8 88 0\n"
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"gpr b12 .8 96 0\n"
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"gpr b13 .8 104 0\n"
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"gpr b14 .8 112 0\n"
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"gpr b15 .8 120 0\n"
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"gpr b16 .8 128 0\n"
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"gpr b17 .8 136 0\n"
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"gpr b18 .8 144 0\n"
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"gpr b19 .8 152 0\n"
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"gpr b20 .8 160 0\n"
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"gpr b21 .8 168 0\n"
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"gpr b22 .8 176 0\n"
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"gpr b23 .8 184 0\n"
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"gpr b24 .8 192 0\n"
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"gpr b25 .8 200 0\n"
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"gpr b26 .8 208 0\n"
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"gpr b27 .8 216 0\n"
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"gpr b28 .8 224 0\n"
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"gpr b29 .8 232 0\n"
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"gpr b30 .8 240 0\n"
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/* 16bit sub-registers */
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"gpr h0 .16 0 0\n"
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"gpr h1 .16 8 0\n"
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"gpr h2 .16 16 0\n"
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"gpr h3 .16 24 0\n"
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"gpr h4 .16 32 0\n"
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"gpr h5 .16 40 0\n"
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"gpr h6 .16 48 0\n"
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"gpr h7 .16 56 0\n"
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"gpr h8 .16 64 0\n"
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"gpr h9 .16 72 0\n"
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"gpr h10 .16 80 0\n"
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"gpr h11 .16 88 0\n"
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"gpr h12 .16 96 0\n"
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"gpr h13 .16 104 0\n"
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"gpr h14 .16 112 0\n"
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"gpr h15 .16 120 0\n"
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"gpr h16 .16 128 0\n"
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"gpr h17 .16 136 0\n"
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"gpr h18 .16 144 0\n"
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"gpr h19 .16 152 0\n"
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"gpr h20 .16 160 0\n"
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"gpr h21 .16 168 0\n"
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"gpr h22 .16 176 0\n"
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"gpr h23 .16 184 0\n"
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"gpr h24 .16 192 0\n"
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"gpr h25 .16 200 0\n"
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"gpr h26 .16 208 0\n"
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"gpr h27 .16 216 0\n"
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"gpr h28 .16 224 0\n"
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"gpr h29 .16 232 0\n"
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"gpr h30 .16 240 0\n"
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/* 32bit sub-registers */
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"gpr w0 .32 0 0\n"
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"gpr w1 .32 8 0\n"
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@ -779,9 +779,7 @@ R_API char *r_str_word_get_first(const char *text) {
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}
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R_API const char *r_str_get(const char *str) {
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if (str == NULL)
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return nullstr_c;
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return str;
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return str? str: nullstr_c;
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}
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R_API char *r_str_ndup(const char *ptr, int len) {
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