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Remove trailing spaces (#19460)

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$ git grep ' $' | grep -v ^test/ | cut -d : -f 1 | sort -u > /tmp/trailing
$ for a in `cat /tmp/trailing` ; do sed -i -e 's/ *$//' $a ; done
This commit is contained in:
pancake 2021-12-02 17:39:59 +01:00 committed by GitHub
parent 7b23114f9f
commit e6f2cd0b2a
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2
.github/upload.sh vendored
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@ -4,7 +4,7 @@ set +x # Do not leak information
# Exit immediately if one of the files given as arguments is not there
# because we don't want to delete the existing release if we don't have
# the new files that should be uploaded
# the new files that should be uploaded
for file in "$@"
do
if [ ! -e "$file" ]

2
.github/workflows/ci.yml vendored
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@ -190,7 +190,7 @@ jobs:
with:
name: radare2-${{ steps.r2v.outputs.branch }}-static.tar.xz
path: r2-static.tar.xz
- name: Static static r2 with meson
- name: Static static r2 with meson
run: |
sudo apt-get --assume-yes install python3-wheel python3-setuptools cabextract gperf
sudo pip3 install meson ninja

2
.github/workflows/codeql-analysis.yml vendored
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@ -25,7 +25,7 @@ jobs:
# the head of the pull request instead of the merge commit.
- run: git checkout HEAD^2
if: ${{ github.event_name == 'pull_request' }}
# Initializes the CodeQL tools for scanning.
- name: Initialize CodeQL
uses: github/codeql-action/init@v1

2
Makefile
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@ -171,7 +171,7 @@ ifneq ($(USE_ZIP),NO)
$(ZIP) -r "${ZIPNAME}" "radare2-${WINBITS}-${VERSION}"
endif
clean:
clean:
rm -f libr/libr.a libr/libr.dylib libr/include/r_version.h
rm -rf libr/.libr
for DIR in shlr libr binr ; do $(MAKE) -C "$$DIR" clean ; done

2
configure-plugins
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@ -37,7 +37,7 @@ if [ ! -f "$cfg" ]; then
fi
load () {
if [ -e $cfg ]; then
if [ -e $cfg ]; then
echo "configure-plugins: Loading $cfg .."
. $cfg
else

2
dist/maemo/description.txt vendored
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@ -1,2 +1,2 @@
Advanced command line debugger and hexadecimal editor
It is composed by an hexadecimal editor (radare) with a wrapped IO layer supporting multiple backends for local/remote files, accessing filesystems, debugger (osx,bsd,linux,w32), stream analyzer, assembler/disassembler (rasm) for x86,arm,ppc,m68k,java,msil,sparc code analysis modules and scripting facilities. A bindiffer named radiff, base converter (rax), shellcode development helper (rasc), a binary information extractor supporting (pe, mach0, elf, class, ...) named rabin, and a block-based hash utility called rahash.
It is composed by an hexadecimal editor (radare) with a wrapped IO layer supporting multiple backends for local/remote files, accessing filesystems, debugger (osx,bsd,linux,w32), stream analyzer, assembler/disassembler (rasm) for x86,arm,ppc,m68k,java,msil,sparc code analysis modules and scripting facilities. A bindiffer named radiff, base converter (rax), shellcode development helper (rasc), a binary information extractor supporting (pe, mach0, elf, class, ...) named rabin, and a block-based hash utility called rahash.

12
dist/snapcraft/snapcraft.yaml vendored
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@ -3,12 +3,12 @@ version: '4.5.0'
base: core18
summary: Radare2 reverse engineering framework and tool
description: |
Radare2 (also known as r2) is a complete framework for reverse-engineering
and analyzing binaries; composed of a set of small utilities
that can be used together or independently from the command line.
Built around a disassembler for computer software which generates
assembly language source code from machine-executable code,
it supports a variety of executable formats for different processors
Radare2 (also known as r2) is a complete framework for reverse-engineering
and analyzing binaries; composed of a set of small utilities
that can be used together or independently from the command line.
Built around a disassembler for computer software which generates
assembly language source code from machine-executable code,
it supports a variety of executable formats for different processors
and operating systems.
grade: devel # Development version, can only publish to beta/candidate channels.

4
doc/android.md
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@ -21,11 +21,11 @@ To compile for android-x86
To package:
mkdir
mkdir
make install DESTDIR=/usr
Build farm, see `sys/android-shell.sh` and `sys/android-build.sh`
sys/android-shell.sh sys/android-build.sh arm-static
Environment:

2
doc/avr.md
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@ -3,7 +3,7 @@ AVR (arduino, atmega128, ..)
Install JTAG serial driver:
http://www.wch.cn/download/CH341SER_MAC_ZIP.html
http://www.wch.cn/download/CH341SER_MAC_ZIP.html
Install SDK from Arduino:

2
doc/brainfuck.md
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@ -16,7 +16,7 @@ To debug a brainfuck program:
The debugger creates virtual sections for code, data, screen and input.
TODO
TODO
----
- add support for comments, ignore invalid instructions as nops
- enhance io and debugger plugins to generate sections and set arch opts

2
doc/capstone.md
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@ -1,7 +1,7 @@
Capstone
========
Capstone Engine is the disassembler engine used by radare2 by default for
Capstone Engine is the disassembler engine used by radare2 by default for
some architectures.
R2 supports capstone 3, 4 and 5.

14
doc/debug-internals.md
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@ -139,13 +139,13 @@ following files:
// architecture-specific debugger code
libr/debug/p/native/arm.c // unused?
// code for handling backtracing
libr/debug/p/native/bt.c
libr/debug/p/native/bt/fuzzy-all.c
libr/debug/p/native/bt/generic-x64.c
libr/debug/p/native/bt/generic-x86.c
// architecture-specific register handling
libr/debug/p/native/drx.c // x86-specific debug registers
libr/debug/p/native/reg.c // cute include of the files below
@ -155,11 +155,11 @@ following files:
libr/debug/p/native/reg/netbsd-x86.h
libr/debug/p/native/reg/windows-x64.h
libr/debug/p/native/reg/windows-x86.h
// platform-specific debugger code on Linux
libr/debug/p/native/linux/linux_debug.c // main linux-specific debugging code
libr/debug/p/native/linux/linux_debug.h // including cute penguin ascii art
// architecture-specific register handling on Linux (?? what is this format??)
libr/debug/p/native/linux/reg/linux-arm.h
libr/debug/p/native/linux/reg/linux-arm64.h
@ -168,13 +168,13 @@ following files:
libr/debug/p/native/linux/reg/linux-x64.h
libr/debug/p/native/linux/reg/linux-x64-32.h
libr/debug/p/native/linux/reg/linux-x86.h
// platform-specific debugger code on Windows
libr/debug/p/native/w32.c // !! not used by anything else
libr/debug/p/native/maps/windows.c // platform-specific memory map handling
libr/debug/p/native/windows/windows_debug.c // main code for win32 debugger plugin
libr/debug/p/native/windows/windows_debug.h // including cute windows ascii art
// platform-specific debugger code on XNU (OSX/iOS/etc)
libr/debug/p/native/darwin.c // !! not used by anything else
libr/debug/p/native/maps/darwin.c // platform-specific memory map handling
@ -185,7 +185,7 @@ following files:
libr/debug/p/native/xnu/xnu_excthreads.c // additional XNU thread handling
libr/debug/p/native/xnu/xnu_threads.c // XNU thread and register handling
libr/debug/p/native/xnu/xnu_threads.h
// architecture-specific register handling on XNU (?? what is this format??)
libr/debug/p/native/xnu/reg/darwin-x86.h
libr/debug/p/native/xnu/reg/darwin-arm.h

44
doc/dospart
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@ -22,7 +22,7 @@
0a OS/2 Boot ManagerOS/2 is the operating system designed by Microsoft and IBM to be
0a Coherent swap partition
0a OPUSOpen Parallel Unisys Server.
0b WIN95 OSR2 FAT32Partitions up to 2047GB. See
0b WIN95 OSR2 FAT32Partitions up to 2047GB. See
0c WIN95 OSR2 FAT32, LBA-mappedExtended-INT13 equivalent of 0b.
0e WIN95: DOS 16-bit FAT, LBA-mapped
0f WIN95: Extended partition, LBA-mappedWindows 95 uses 0e and 0f as the extended-INT13 equivalents
@ -31,7 +31,7 @@
11 Leading Edge DOS 3.x
12 Configuration/diagnostics partitionID 12 (decimal 18) is used by Compaq for their configuration utility
14 Hidden DOS 16-bit FAT <32M(Ralf Brown's interrupt list adds: `ID 14 resulted from using Novell
14 AST DOS with
14 AST DOS with
16 Hidden DOS 16-bit FAT >=32M
17 Hidden IFS (e.g., HPFS)
18 AST SmartSleep PartitionAscentia laptops have a `Zero Volt Suspend Partition'
@ -40,18 +40,18 @@
1c Hidden WIN95 OSR2 FAT32, LBA-mappedSometimes a hidden IBM rescue partition.
1e Hidden WIN95 16-bit FAT, LBA-mapped
20 UnusedRumoured to be used by Willowsoft Overture File System (OFS1),
21 Reserved(according to
21 Reserved(according to
21 UnusedClaimed for FSo2 (Oxygen File System) by Dave Poirier
22 UnusedClaimed for Oxygen Extended Partition Table by ekstazya@sprint.ca.
23 Reserved
24 NEC DOS 3.xThis is NEC MS-DOS 3.30
24 NEC DOS 3.xThis is NEC MS-DOS 3.30
26 Reserved
27 PQserviceAcer laptop hidden rescue partition. Must be FAT32.
27 Windows RE hidden partitionOn MBR disks, type 0x27. On GPT disks, GUID:
27 MirOS partition
27 RouterBOOT kernel partitionSee
2a AtheOS File System (AFS)AtheOS is an open source operating system written by Kurt Skauen.
2b SyllableSecure (SylStor)A variation on AthFS is
2b SyllableSecure (SylStor)A variation on AthFS is
31 Reserved
32 NOSSimon Butcher (simonb@alien.net.au) writes:
33 Reserved
@ -64,7 +64,7 @@
3a THEOS ver 4 4gb partition
3b THEOS ver 4 extended partitionTHEOS is a multiuser multitasking OS for PCs founded by Timothy Williams
3c PartitionMagic recovery partitionCody Batt (codyb@powerquest.com) writes:
3d Hidden NetWareAccording to
3d Hidden NetWareAccording to
40 Venix 80286A very old Unix-like operating system for PCs.
40 PICKRoss Stell writes:
41 Linux/MINIX (sharing disk with DRDOS)Very old FAQs recommended to use 41 etc instead of 81 etc
@ -76,18 +76,18 @@
43 Linux native (sharing disk with DRDOS)
44 GoBack partition
45 Boot-US boot managerUlrich Straub (ustraub@boot-us.de) writes:
45 PriamAccording to
45 EUMEL/Elan
46 EUMEL/Elan
47 EUMEL/Elan
45 PriamAccording to
45 EUMEL/Elan
46 EUMEL/Elan
47 EUMEL/Elan
48 EUMEL/Elan Eumel, and later Ergos L3, are multiuser multitasking systems
4a Mark Aitchison's ALFS/THIN lightweight filesystem for DOSAccording to
4a Mark Aitchison's ALFS/THIN lightweight filesystem for DOSAccording to
4a AdaOS Aquila (Withdrawn)Nick Roberts at some point in time announced that he would use 4a
4c Oberon partitionSee
4c Oberon partitionSee
4d QNX4.x
4e QNX4.x 2nd part
4f QNX4.x 3rd partQNX is a POSIX-certified, microkernel, distributed, fault-tolerant
4f Oberon partitionSee
4f Oberon partitionSee
50 OnTrack Disk Manager (older versions) RODisk Manager is a program of OnTrack, to enable people to use
50 Lynx RTOS"Beginning with version 3.0, LynxOS gives users the ability to
50 Native Oberon (alt)
@ -124,14 +124,14 @@
76 Reserved
77 M2FS/M2CS partitionJeff Merkey writes: 77 is one we are using internally for M2FS/M2CS partitions.
77 VNDI Partition(According to disk.c in the Netware source. Not in actual use.)
78 XOSL FSXOSL Bootloader filesystem, see
78 XOSL FSXOSL Bootloader filesystem, see
7e UnusedClaimed for F.I.X. by gruberr@kapsch.net. See dejanews.
7f UnusedProposed for the
7f UnusedProposed for the
80 MINIX until 1.4a
81 MINIX since 1.4b, early LinuxMinix is a Unix-like operating system written by Andy Tanenbaum
81 Mitac disk manager
82 Prime
82 Solaris x86Solaris creates a single partition with id 0x82, then uses Sun disk labels
82 Solaris x86Solaris creates a single partition with id 0x82, then uses Sun disk labels
82 Linux swap
83 Linux native partitionLinux is a Unix-like operating system written by Linus Torvalds
84 OS/2 hidden C: driveOS/2-renumbered type 04 partition.
@ -145,7 +145,7 @@
8b Legacy Fault Tolerant FAT32 volume
8c Legacy Fault Tolerant FAT32 volume using BIOS extd INT 13h
8d Free FDISK 0.96+ hidden Primary DOS FAT12 partitition
8e Linux Logical Volume Manager partitionSee
8e Linux Logical Volume Manager partitionSee
90 Free FDISK 0.96+ hidden Primary DOS FAT16 partitition
91 Free FDISK 0.96+ hidden DOS extended partitition
92 Free FDISK 0.96+ hidden Primary DOS large FAT16 partitition
@ -156,7 +156,7 @@
96 CHRP ISO-9660 filesystem
97 Free FDISK 0.96+ hidden Primary DOS FAT32 partitition
98 Free FDISK 0.96+ hidden Primary DOS FAT32 partitition (LBA)
98 Datalight ROM-DOS Super-Boot PartitionSee
98 Datalight ROM-DOS Super-Boot PartitionSee
99 DCE376 logical driveNo, it's not a hibernation partition; it's closest to a DOS extended
9a Free FDISK 0.96+ hidden Primary DOS FAT16 partitition (LBA)
9b Free FDISK 0.96+ hidden DOS extended partitition (LBA)
@ -200,7 +200,7 @@ c0 REAL/32 secure small partitionSee d0 below.
c0 NTFT PartitionAccording to disk.c in the Netware source.
c0 DR-DOS/Novell DOS secured partitionDR-DOS 7.02+ / OpenDOS 7.01 / Novell DOS 7 secured partition.
c1 DRDOS/secured (FAT-12)
c2 UnusedAccording to
c2 UnusedAccording to
c2 Hidden Linux
c3 Hidden Linux swapBenedict Chong (bchong@blueskyinnovations.com) writes:
c4 DRDOS/secured (FAT-16, < 32M)
@ -214,7 +214,7 @@ c9 Reserved for DR-DOS 8.0+
ca Reserved for DR-DOS 8.0+
cb DR-DOS 7.04+ secured FAT32 (CHS)/
cc DR-DOS 7.04+ secured FAT32 (LBA)/
cd CTOS Memdump?
cd CTOS Memdump?
ce DR-DOS 7.04+ FAT16X (LBA)/
cf DR-DOS 7.04+ secured EXT DOS (LBA)/
d0 REAL/32 secure big partitionREAL/32 is a continuation of DR Multiuser DOS.
@ -229,11 +229,11 @@ da Powercopy BackupPowercopy Backup (shielded disk),
db Digital Research CP/M, Concurrent CP/M, Concurrent DOS
db CTOS (Convergent Technologies OS -Unisys)
db KDG Telemetry SCPU bootMark Morgan Lloyd (markMLl.in@telemetry.co.uk) writes:
dd Hidden CTOS Memdump?
dd Hidden CTOS Memdump?
de Dell PowerEdge Server utilities (FAT fs)
df DG/UX virtual disk manager partitionGlenn Steen (glenn.steen@ap1.se) writes:
df BootIt EMBRMThe boot manager BootIt manages its own partition table,
e0 Reserved by
e0 Reserved by
e1 DOS access or SpeedStor 12-bit FAT extended partitionKevin Cummings reports in alt.os.linux:
e3 DOS R/O or SpeedStor
e4 SpeedStor 16-bit FAT extended partition < 1024 cyl.

2
doc/emscripten.md
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@ -19,7 +19,7 @@ Building for the browser
export CC="emcc --ignore-dynamic-linking"
./configure --prefix=/usr --disable-shared --enable-static --disable-debugger --with-compiler=emscripten --without-pic --with-nonpic
emmake make -j4
emmake make -j4
cd binr/radare2
emcc ../../libr/*/*.o radare2.c -I ../../libr/include/ -DR2_BIRTH=\"pop\" -DR2_GITTIP=\"123\" ../../libr/db/sdb/src/*.o

2
doc/esil.md
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@ -43,7 +43,7 @@ Conditionals are expressed with the '?' char at the beginning of the expression.
cmp eax, 123 -> 123,eax,==,$z,zf,=
jz eax -> zf,?{,eax,eip,=,}
So.. if you want to run more than one expression under a conditional, you'll have to write it
So.. if you want to run more than one expression under a conditional, you'll have to write it
zf,?{,eip,esp,=[],eax,eip,=,$r,esp,-=,}

6
doc/gdb.md
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@ -36,7 +36,7 @@ Supported Commands
- read registers
Reading registers is currently implemented through the <g> packet of the gdb protocol.
It returns the whole register profile at once.
It returns the whole register profile at once.
- write registers
@ -51,7 +51,7 @@ Supported Packets:
- `g` : Reads the whole register Profile at once
- `G` : Writes the whole register Profile at once
- `m` : Reads memory
- `m` : Reads memory
- `M` : Writes memory
- `vCont,v` : continues execution of the binary
- `P` : Write one register
@ -59,7 +59,7 @@ Supported Packets:
TODO
----
- Implement GDBserver to allow other apps use r2 debugger
- Implement GDBserver to allow other apps use r2 debugger
- Fix that usese the gdb internal stepping version
- Fix softstep, that it finally recoils correct (it just have to reset the eip/rip)
- Add Breakpoints (should be an easy add of the function, because its already implemented in the gdb lib)

18
doc/iocache
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@ -1,20 +1,20 @@
io cache and write changes
[0x000018a0]> wc?
[0x000018a0]> wc?
Usage: wc[ir*?]
wc list all write changes
wc* "" in radare commands
wcr reset all write changes in cache
wci commit write cache
NOTE: Needs io.cache=true
[0x000018a0]> e io.cache=true
[0x000018a0]> wx 9090
[0x000018a0]> wc
[0x000018a0]> e io.cache=true
[0x000018a0]> wx 9090
[0x000018a0]> wc
addr=0x000018a0 size=2
[0x000018a0]> wc*
[0x000018a0]> wc*
wx 9090 @ 0x000018a0
[0x000018a0]> wci
[0x000018a0]> wci
r_io_write: cannot write on fd 3
[0x000018a0]> wcr
[0x000018a0]> wc
[0x000018a0]>
[0x000018a0]> wcr
[0x000018a0]> wc
[0x000018a0]>

6
doc/iphone.md
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@ -43,7 +43,7 @@ Setup SDK for ARMv6
5) Get the varinclude tarball
wget lolcathost.org/b/varinclude.tar.gz
wget lolcathost.org/b/varinclude.tar.gz
tar xzvf varinclude.tar.gz -C /
Compilation
@ -67,7 +67,7 @@ Building with the ARMv7 SDK
From coolstar repo we get the ios toolchain
apt-get coreutils install wget inetutils
apt-get install basename git make expat
apt-get install basename git make expat
apt-get install org.coolstar.iostoolchain
* Copy crt1.o and dylib1.o from your iOS SDK into /usr/lib
@ -80,7 +80,7 @@ From coolstar repo we get the ios toolchain
cd /usr/bin
ln -fs clang gcc
Build
-----
export CC=clang

2
doc/lang-plugins
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@ -7,7 +7,7 @@ interface from each method hook.
We should define a common and simple way to design those inter-
language communications.
With this interface properly defined we can get some more fun and
With this interface properly defined we can get some more fun and
write the language bindings using the same lang-C api.
A simple perl script can be used to parse function signatures and

6
doc/license.md
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@ -1,6 +1,6 @@
# Licensing
Before you try to statically link r2, you should know about the licenses that go along with it,
Before you try to statically link r2, you should know about the licenses that go along with it,
http://stackoverflow.com/questions/10130143/gpl-lgpl-and-static-linking
@ -8,7 +8,7 @@ Also this stackoverflow page explains the legal case of using it via r2pipe,
http://stackoverflow.com/questions/1394623/can-i-dynamically-call-a-lgpl-gpl-software-in-my-closed-source-application
LGPLv3 keeps the freedom to the user to switch to a different version of the r2 libraries, so static linking is not permitted unless the privative software is distributed with the object files needed to do the full static link, so the users will be able to upgrade or modify r2 libraries even if
LGPLv3 keeps the freedom to the user to switch to a different version of the r2 libraries, so static linking is not permitted unless the privative software is distributed with the object files needed to do the full static link, so the users will be able to upgrade or modify r2 libraries even if
r2 is licensed under the LGPL license, which permits statically linking, but forces you to liberate the object files and a way to allow users to link them.
@ -52,7 +52,7 @@ Please refer to the radare2-webui repository for a detailed list of all the java
## Non-LGPL code shipped in r2
Some parts of r2 are not under the LGPL license, this is a list of them sorted
Some parts of r2 are not under the LGPL license, this is a list of them sorted
### GPL: More restrictive than LGPL

2
doc/maemo.md
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@ -1,7 +1,7 @@
Build for maemo6 (Harmattan) N9 - N950
======================================
1. Install QtSDK
1. Install QtSDK
http://qt.nokia.com/downloads/

2
doc/oo.md
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@ -26,7 +26,7 @@ Global picture
- simplify code
A library implements a set of functionalities, those ones are mainly
the lifecycle of the class containing the state of
the lifecycle of the class containing the state of
Plugins are singletons. Or we will have to create factories for every class.

24
doc/pdb/index.js
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@ -60,14 +60,14 @@ var extract_pdb_file = function (archive_name, dbg_fname) {
console.log('check if cabextract is installed');
process.exit(1);
});
cab_extractor_cmd.on('exit', function (code) {
if (code != 0) {
console.log("Failed to extract with code: " + code);
} else {
fs.unlink(archive_name);
console.log("File " + archive_name + " has been uncompressed successfully");
}
}
});
};
@ -75,14 +75,14 @@ var curl_start = function(guid, dbg_fname) {
var archive_name = dbg_fname;
var link_end = '';
var spawn = require('child_process').spawn;
archive_name = archive_name.substring(0, archive_name.length - 1) + '_';
archive_name = archive_name.substring(0, archive_name.length - 1) + '_';
link_end = '/' + dbg_fname + '/' + guid + '/' + archive_name;
var stream = fs.createWriteStream(archive_name, {flags:'a'});
console.log("downloading file: " + archive_name);
var curl_ = new curl(DOWNLOABLE_LINK + link_end, {RAW:0}, function(err) {
console.info(this);
return;
@ -95,13 +95,13 @@ var curl_start = function(guid, dbg_fname) {
stream.write(chunk);
return chunk.length;
});
curl_.on('error', function(e) {
console.log('File: ' + archive_name + 'has not been downloaded successfully');
curl_.close();
return;
});
curl_.on('end', function() {
console.log('File ' + archive_name + 'has been downloaded and saved successfully');
console.log('Decompress of file: ' + archive_name);
@ -125,13 +125,13 @@ var downloader = function (currentValue, index, array) {
if (currentValue.indexOf('pdb') != -1) {
return;
}
rabin2_cmd.stdout.on('error', function (err) {
console.log('check if rabin is installed');
process.exit(1);
});
rabin2_cmd.stdout.on('data', function (data) {
rabin2_cmd.stdout.on('data', function (data) {
data.toString().split(EOL).map(function (str) {
var parts = str.split(' ');
@ -171,7 +171,7 @@ walk(IN_FOLDER, function(err, results) {
console.log('Error while walking the directory.Error: ' + err);
process.exit(1);
}
results.forEach(downloader);
});

2
doc/r2s/r2-5.5.0.r2s
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@ -38,7 +38,7 @@ is then taken by the text before '.vasm'
This is an optional feature, so it's also optional to test it unless you
are looking for modiying binaries for the supported architectures.
Supported archs:
Supported archs:
* arm.vasm, 6502.vasm, 6809, c16x, jagrisc, m68k,
* pdp11, ppc, qnice, tr3200, vidcore, x86, z80"

2
doc/rap.md
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@ -72,7 +72,7 @@ This is how are constructed the packets:
<< 84
RAP_CLOSE
>> 05 FD=(4 bytes)
>> 05 FD=(4 bytes)
<< 85 RET=(4 bytes)
RAP_SYSTEM

2
doc/sandbox/rabin2.sb
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@ -34,6 +34,6 @@
#"^/usr/lib/system/*"
#"^/usr/lib/libr*"
#"^/usr/bin/rabin2"
)
)
)
(deny default)

2
doc/sandbox/radare2.sb
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@ -37,6 +37,6 @@
#"^/usr/lib/libr*"
#"^/usr/bin/r2"
#"^/bin/ls"
)
)
)
(deny default)

2
doc/sdb_ordinal.md
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@ -1,6 +1,6 @@
# Cannot find R2PATH/format/dll/DLLNAME.sdb
1. Execute `rabin2 -rs DLLNAME.dll | grep -i DLLNAME | grep -v Ordi |grep ^k| cut -d / -f 4- > DLLNAME.sdb.txt`
1. Execute `rabin2 -rs DLLNAME.dll | grep -i DLLNAME | grep -v Ordi |grep ^k| cut -d / -f 4- > DLLNAME.sdb.txt`
2. Upload file `DLLNAME.sdb.txt` in https://github.com/radareorg/radare2/tree/master/libr/bin/d/dll
3. Change the following [Makefile](https://github.com/radareorg/radare2/blob/master/libr/bin/d/Makefile#L14)
4. Create a Pull Request to Master

32
doc/snap.md
View File

@ -1,25 +1,25 @@
Installing the snap package of radare2
======================================
radare2 is also available as a snap package and can be installed on a system that supports snap packages. See [Installing snapd](https://snapcraft.io/docs/installing-snapd) to setup your system to support snap packages.
radare2 is also available as a snap package and can be installed on a system that supports snap packages. See [Installing snapd](https://snapcraft.io/docs/installing-snapd) to setup your system to support snap packages.
Status of snap package support
------------------------------
Currently, radare2 is available as a _beta_ snap package that works in _devmode_ security confinement (developer mode). Refer back to this section for updated instructions when radare2 is out of _beta/devmode_.
Currently, radare2 is available as a _beta_ snap package that works in _devmode_ security confinement (developer mode). Refer back to this section for updated instructions when radare2 is out of _beta/devmode_.
Currently, you need to prepend `radare2.` to each command you want to run. For example, use `radare2.rabin2` to run `rabin2`.
Currently, you need to prepend `radare2.` to each command you want to run. For example, use `radare2.rabin2` to run `rabin2`.
Snap packages that work in _devmode_ security confinement do not appear in search results, when you search for them in the Snap Store. To find information about this snap package, run `snap info radare2`. See the section below on this.
Installing radare2
-----------------
This command installs the `radare2` snap package from the _beta_ channel, using the _devmode_ (developer mode) security confinement type. The _devmode_ security confinement disables any restrictions that are applied to typical snap packages. _devmode_ makes a package to work similar to APT and RPM packages.
This command installs the `radare2` snap package from the _beta_ channel, using the _devmode_ (developer mode) security confinement type. The _devmode_ security confinement disables any restrictions that are applied to typical snap packages. _devmode_ makes a package to work similar to APT and RPM packages.
$ sudo snap install radare2 --channel=beta --devmode
Running commands
----------------
Currently, the radare2 commands can be invoked with the following names:
Currently, the radare2 commands can be invoked with the following names:
- `radare2` or `radare2.radare2`: The `r2`/`radare2` command.
- `radare2.r2pm` : The `r2pm` command.
@ -43,12 +43,12 @@ Run the following command to get info about the radare2 snap package. You can se
$ snap info radare2
...
description: |
Radare2 (also known as r2) is a complete framework for reverse-engineering
and analyzing binaries; composed of a set of small utilities
that can be used together or independently from the command line.
Built around a disassembler for computer software which generates
assembly language source code from machine-executable code,
it supports a variety of executable formats for different processors
Radare2 (also known as r2) is a complete framework for reverse-engineering
and analyzing binaries; composed of a set of small utilities
that can be used together or independently from the command line.
Built around a disassembler for computer software which generates
assembly language source code from machine-executable code,
it supports a variety of executable formats for different processors
and operating systems.
commands:
@ -79,11 +79,11 @@ Updating radare2
----------------
The snap packages that are installed in _devmode_ are not updated automatically.
You can update manually:
You can update manually:
$ sudo snap refresh radare2
See the section above on how to get info about the radare2 snap package and how to determine whether there is an updated version available.
See the section above on how to get info about the radare2 snap package and how to determine whether there is an updated version available.
Uninstalling radare2
--------------------
@ -106,7 +106,7 @@ Troubleshooting
---------------
- _error: snap "radare2" is not available on stable_: When installing the snap package of radare2, you currently need to specify the _beta_ channel. Append `--channel=beta` on the installation command line.
- _error: The publisher of snap "radare2" has indicated that they do not consider this revision to be of production quality_: When installing the snap package of radare2, you currently need to specify the _devmode_ confinement. Append `--devmode` on the installation command line.
- _How can I download the snap package for offline use?_: Use the command `snap download radare2 --channel=beta`. You can then run `sudo snap install` to install the `.snap` package that was just downloaded.
- _error: The publisher of snap "radare2" has indicated that they do not consider this revision to be of production quality_: When installing the snap package of radare2, you currently need to specify the _devmode_ confinement. Append `--devmode` on the installation command line.
- _How can I download the snap package for offline use?_: Use the command `snap download radare2 --channel=beta`. You can then run `sudo snap install` to install the `.snap` package that was just downloaded.
- _Do I need to use "sudo" with snap commands?_: You need to prepend `sudo` when you run most snap commands that perform privileged actions. However, if you log in into the Snap Store using `sudo snap login`, then you do not need anymore to prepend `sudo`.

8
libr/anal/class.c
View File

@ -1205,7 +1205,7 @@ R_API void r_anal_class_list_vtables(RAnal *anal, const char *class_name) {
static void list_all_functions_at_vtable_offset(RAnal *anal, const char *class_name, ut64 offset) {
RVTableContext vtableContext;
r_anal_vtable_begin (anal, &vtableContext);
ut8 function_ptr_size = vtableContext.word_size;
ut8 function_ptr_size = vtableContext.word_size;
ut64 func_address;
RVector *vtables = r_anal_class_vtable_get_all (anal, class_name);
@ -1252,10 +1252,10 @@ R_API void r_anal_class_list_vtable_offset_functions(RAnal *anal, const char *cl
}
/**
* @brief Creates RGraph from class inheritance information where
* @brief Creates RGraph from class inheritance information where
* each node has RGraphNodeInfo as generic data
*
* @param anal
*
* @param anal
* @return RGraph* NULL if failure
*/
R_API RGraph *r_anal_class_get_inheritance_graph(RAnal *anal) {

6
libr/anal/esil.c
View File

@ -7,7 +7,7 @@
#ifdef __wasi__
#define FE_OVERFLOW 0
#define feclearexcept(x)
#define feclearexcept(x)
#endif
// should these be here?
#include <math.h>
@ -598,7 +598,7 @@ R_API bool r_anal_esil_signext(RAnalEsil *esil, bool assign) {
}
//Make sure the other bits are 0
src &= UT64_MAX >> (64 - dst);
src &= UT64_MAX >> (64 - dst);
ut64 m = 0;
if (dst < 64) {
@ -1737,7 +1737,7 @@ static void mult64to128(ut64 op1, ut64 op2, ut64 *hi, ut64 *lo) {
static bool esil_long_mul(RAnalEsil *esil) {
bool ret = false;
ut64 s, d;
ut64 s, d;
ut64 hi, lo;
char *dst = r_anal_esil_pop (esil);
char *src = r_anal_esil_pop (esil);

2
libr/anal/global.c
View File

@ -31,7 +31,7 @@ R_API bool r_anal_global_add(RAnal *anal, ut64 addr, const char *type_name, cons
r_flag_item_set_type (fi, fmtstr);
}
r_meta_set (anal, R_META_TYPE_FORMAT, addr, fmtsize, fmtstr);
// implicit
// implicit
r_type_set_link (anal->sdb_types, fmtstr, addr);
return true;
}

66
libr/anal/p/anal_arm_cs.c
View File

@ -1040,10 +1040,10 @@ static void vector64_append(RStrBuf *sb, csh *handle, cs_insn *insn, int n, int
size_t s = sizeof (bitmask_by_width) / sizeof (*bitmask_by_width);
int width = size > 0? (size - 1) % s: 0;
if (shift > 0) {
r_strbuf_appendf (sb, "0x%"PFMT64x",%d,%s%s,>>,&",
r_strbuf_appendf (sb, "0x%"PFMT64x",%d,%s%s,>>,&",
bitmask_by_width[width], shift, REG64 (n), regc);
} else {
r_strbuf_appendf (sb, "0x%"PFMT64x",%s%s,&",
r_strbuf_appendf (sb, "0x%"PFMT64x",%s%s,&",
bitmask_by_width[width], REG64 (n), regc);
}
} else {
@ -1080,11 +1080,11 @@ static void vector64_dst_append(RStrBuf *sb, csh *handle, cs_insn *insn, int n,
}
if (shift > 0 && shift < 64) {
r_strbuf_appendf (sb, "%d,SWAP,0x%"PFMT64x",&,<<,%s%s,0x%"PFMT64x",&,|,%s%s",
r_strbuf_appendf (sb, "%d,SWAP,0x%"PFMT64x",&,<<,%s%s,0x%"PFMT64x",&,|,%s%s",
shift, mask, REG64 (n), regc, VEC64_MASK (shift, size), REG64 (n), regc);
} else {
int dimsize = size % 64;
r_strbuf_appendf (sb, "0x%"PFMT64x",&,%s%s,0x%"PFMT64x",&,|,%s%s",
r_strbuf_appendf (sb, "0x%"PFMT64x",&,%s%s,0x%"PFMT64x",&,|,%s%s",
mask, REG64 (n), regc, VEC64_MASK (shift, dimsize), REG64 (n), regc);
}
} else {
@ -1098,13 +1098,13 @@ static ut64 shifted_imm64(csh *handle, cs_insn *insn, int n, int sz) {
cs_arm64_op op = INSOP64 (n);
int sft = op.shift.value;
switch (op.shift.type) {
case ARM64_SFT_MSL:
case ARM64_SFT_MSL:
return (IMM64 (n) << sft) | ((1 << sft) - 1);
case ARM64_SFT_LSL:
return IMM64 (n) << sft;
case ARM64_SFT_LSR:
return IMM64 (n) >> sft;
case ARM64_SFT_ROR:
case ARM64_SFT_ROR:
return (IMM64 (n) >> sft)|(IMM64 (n) << (sz - sft));
case ARM64_SFT_ASR:
switch (sz) {
@ -1224,7 +1224,7 @@ static void arm64fpmath(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int le
cs_arm64_op dst = INSOP64 (0);
int start = -1;
int end = 0;
int end = 0;
int convert = size == 64 ? 0 : 1;
if (dst.vas) {
start = 0;
@ -1462,7 +1462,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
cs_arm64_op src = INSOP64 (1);
if (dst.vas && src.vas) {
r_strbuf_setf (&op->esil, "%sh,%sh,=,%sl,%sl,=",
r_strbuf_setf (&op->esil, "%sh,%sh,=,%sl,%sl,=",
REG64 (1), REG64 (0), REG64 (1), REG64 (0));
} else {
ARG64_APPEND (&op->esil, 1);
@ -1477,7 +1477,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
case ARM64_INS_FCCMP:
case ARM64_INS_FCCMPE:
if (ISREG64 (1)) {
r_strbuf_setf (&op->esil,
r_strbuf_setf (&op->esil,
"%d,%s,F2D,NAN,%d,%s,F2D,NAN,|,vf,:="
",%d,%s,F2D,%d,%s,F2D,F==,vf,|,zf,:="
",%d,%s,F2D,%d,%s,F2D,F<,vf,|,nf,:=",
@ -1486,7 +1486,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
REGBITS64 (1), REG64 (1), REGBITS64 (1), REG64 (0)
);
} else {
r_strbuf_setf (&op->esil,
r_strbuf_setf (&op->esil,
"%d,%s,F2D,NAN,vf,:="
",0,I2D,%d,%s,F2D,F==,vf,|,zf,:="
",0,I2D,%d,%s,F2D,F<,vf,|,nf,:=",
@ -1504,7 +1504,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
}
break;
case ARM64_INS_FCVT:
r_strbuf_setf (&op->esil, "%d,%d,%s,F2D,D2F,%s,=",
r_strbuf_setf (&op->esil, "%d,%d,%s,F2D,D2F,%s,=",
REGBITS64 (0), REGBITS64 (1), REG64 (1), REG64 (0));
break;
case ARM64_INS_SCVTF:
@ -1565,17 +1565,17 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
REGBITS64 (1), REG64 (1), REG64 (0));
break;
case ARM64_INS_FNEG:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,-F,D2F,%s,=",
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1), REG64 (0));
break;
case ARM64_INS_FMIN:
r_strbuf_setf (&op->esil, "%d,%s,F2D,%d,%s,F2D,F<,?{,%s,}{,%s,},%s,=",
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,%s,F2D,%d,%s,F2D,F<,?{,%s,}{,%s,},%s,=",
REGBITS64 (2), REG64 (2),
REGBITS64 (1), REG64 (1), REG64 (1), REG64 (2), REG64 (0));
break;
case ARM64_INS_FMAX:
r_strbuf_setf (&op->esil, "%d,%s,F2D,%d,%s,F2D,F<,!,?{,%s,}{,%s,},%s,=",
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,%s,F2D,%d,%s,F2D,F<,!,?{,%s,}{,%s,},%s,=",
REGBITS64 (2), REG64 (2),
REGBITS64 (1), REG64 (1), REG64 (1), REG64 (2), REG64 (0));
break;
case ARM64_INS_FADD:
@ -1591,26 +1591,26 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
FPOPCALL_NEGATE("*");
break;
case ARM64_INS_FMADD:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,%d,%s,F2D,F+,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,%d,%s,F2D,F+,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
REGBITS64 (3), REG64 (3), REG64 (0));
break;
case ARM64_INS_FNMADD:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,-F,%d,%s,F2D,F+,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,-F,%d,%s,F2D,F+,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
REGBITS64 (3), REG64 (3), REG64 (0));
break;
case ARM64_INS_FMSUB:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,%d,%s,F2D,F-,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,%d,%s,F2D,F-,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
REGBITS64 (3), REG64 (3), REG64 (0));
break;
case ARM64_INS_FNMSUB:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,-F,%d,%s,F2D,F-,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1),
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,-F,%d,%s,F2D,F-,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
REGBITS64 (3), REG64 (3), REG64 (0));
break;
@ -1624,7 +1624,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
/* TODO: support WZR XZR to specify 32, 64bit op */
OPCALL("/");
break;
#if CS_API_MAJOR > 4
#if CS_API_MAJOR > 4
case ARM64_INS_BRAA:
case ARM64_INS_BRAAZ:
case ARM64_INS_BRAB:
@ -1640,7 +1640,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
case ARM64_INS_BL:
r_strbuf_setf (&op->esil, "pc,lr,=,%"PFMT64d",pc,=", IMM64 (0));
break;
#if CS_API_MAJOR > 4
#if CS_API_MAJOR > 4
case ARM64_INS_BLRAA:
case ARM64_INS_BLRAAZ:
case ARM64_INS_BLRAB:
@ -1738,7 +1738,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
if (HASMEMINDEX64 (1)) {
if (LSHIFT2_64 (1) || EXT64 (1)) {
ARG64_APPEND (&op->esil, 1);
r_strbuf_appendf (&op->esil, ",%s,+,[%d],%s,=",
r_strbuf_appendf (&op->esil, ",%s,+,[%d],%s,=",
MEMBASE64 (1), size, REG64 (0));
} else {
r_strbuf_appendf (&op->esil, "%s,%s,+,[%d],%s,=",
@ -1902,7 +1902,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
ARG64_APPEND(&op->esil, 1);
COMMA(&op->esil);
ARG64_APPEND(&op->esil, 0);
r_strbuf_appendf (&op->esil, ",==,$z,zf,:=,%d,$s,nf,:=,%d,$b,!,cf,:=,%d,$o,vf,:=",
r_strbuf_appendf (&op->esil, ",==,$z,zf,:=,%d,$s,nf,:=,%d,$b,!,cf,:=,%d,$o,vf,:=",
REGBITS64 (0) - 1, REGBITS64 (0), REGBITS64 (0) -1);
if (insn->id == ARM64_INS_CCMP || insn->id == ARM64_INS_CCMN) {
@ -2159,7 +2159,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
break;
case ARM64_INS_RBIT:
// slightly shorter expression to reverse bits
r_strbuf_setf (&op->esil, "0,tmp,=,0,DUP,DUP,DUP,%d,-,%s,>>,1,&,<<,tmp,+=,%d,-,?{,++,4,GOTO,},tmp,%s,=",
r_strbuf_setf (&op->esil, "0,tmp,=,0,DUP,DUP,DUP,%d,-,%s,>>,1,&,<<,tmp,+=,%d,-,?{,++,4,GOTO,},tmp,%s,=",
REGBITS64 (1)-1, REG64 (1), REGBITS64 (1)-1, REG64 (0));
break;
case ARM64_INS_MVN:
@ -2169,7 +2169,7 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
cs_arm64_op src = INSOP64 (1);
if (dst.vas && src.vas) {
r_strbuf_setf (&op->esil, "%sh,-1,^,%sh,=,%sl,-1,^,%sl,=",
r_strbuf_setf (&op->esil, "%sh,-1,^,%sh,=,%sl,-1,^,%sl,=",
REG64 (1), REG64 (0), REG64 (1), REG64 (0));
} else {
ARG64_APPEND (&op->esil, 1);

2
libr/anal/p/anal_arm_regprofile.inc
View File

@ -322,7 +322,7 @@ static char *get_reg_profile(RAnal *anal) {
"fpu v30h .64 776 0\n"
"fpu v31h .64 792 0\n"
// this sucks but q* is a valid alias
// this sucks but q* is a valid alias
// for the vector registers in arm64
/* 128 bit vector */

80
libr/anal/p/anal_arm_v35.c
View File

@ -501,13 +501,13 @@ static ut64 shifted_imm64(Instruction *insn, int n, int sz) {
InstructionOperand op = INSOP64 (n);
int sft = op.shiftValue;
switch (op.shiftType) {
case ShiftType_MSL:
case ShiftType_MSL:
return (GETIMM64 (n) << sft) | ((1 << sft) - 1);
case ShiftType_LSL:
return GETIMM64 (n) << sft;
case ShiftType_LSR:
return GETIMM64 (n) >> sft;
case ShiftType_ROR:
case ShiftType_ROR:
return (GETIMM64 (n) >> sft)|(GETIMM64 (n) << (sz - sft));
case ShiftType_ASR:
switch (sz) {
@ -554,10 +554,10 @@ static void vector64_append(RStrBuf *sb, Instruction *insn, int n, int i) {
size_t s = sizeof (bitmask_by_width) / sizeof (*bitmask_by_width);
int width = size > 0? (size - 1) % s: 0;
if (shift > 0) {
r_strbuf_appendf (sb, "0x%"PFMT64x",%d,%s%s,>>,&",
r_strbuf_appendf (sb, "0x%"PFMT64x",%d,%s%s,>>,&",
bitmask_by_width[width], shift, REG64 (n), regc);
} else {
r_strbuf_appendf (sb, "0x%"PFMT64x",%s%s,&",
r_strbuf_appendf (sb, "0x%"PFMT64x",%s%s,&",
bitmask_by_width[width], REG64 (n), regc);
}
} else {
@ -590,10 +590,10 @@ static void vector64_dst_append(RStrBuf *sb, Instruction *insn, int n, int i) {
}
if (shift > 0 && shift < 64) {
r_strbuf_appendf (sb, "%d,SWAP,0x%"PFMT64x",&,<<,%s%s,0x%"PFMT64x",&,|,%s%s",
r_strbuf_appendf (sb, "%d,SWAP,0x%"PFMT64x",&,<<,%s%s,0x%"PFMT64x",&,|,%s%s",
shift, mask, REG64 (n), regc, VEC64_MASK (shift, size), REG64 (n), regc);
} else {
r_strbuf_appendf (sb, "0x%"PFMT64x",&,%s%s,0x%"PFMT64x",&,|,%s%s",
r_strbuf_appendf (sb, "0x%"PFMT64x",&,%s%s,0x%"PFMT64x",&,|,%s%s",
mask, REG64 (n), regc, VEC64_MASK (shift, size), REG64 (n), regc);
}
} else {
@ -692,7 +692,7 @@ static void arm64fpmath(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int le
InstructionOperand dst = INSOP64 (0);
int start = -1;
int end = 0;
int end = 0;
int convert = size == 64 ? 0 : 1;
int count = vas_count(dst.arrSpec);
if (count) {
@ -1064,7 +1064,7 @@ static void anop64(RAnal *a, RAnalOp *op, Instruction *insn) {
op->stackop = R_ANAL_STACK_INC;
op->stackptr = -GETIMM64 (2);
}
if (0) { // REGID64(0) == REG_PC) { v35 has no REG_PC?
if (0) { // REGID64(0) == REG_PC) { v35 has no REG_PC?
op->type = R_ANAL_OP_TYPE_UJMP;
/*if (insn->detail->arm.cc != ARM_CC_AL) {
//op->type = R_ANAL_OP_TYPE_MCJMP;
@ -1302,8 +1302,8 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
break;
case ARM64_SUBS:
OPCALL("-");
r_strbuf_appendf (&op->esil,
",$z,zf,:=,%d,$s,nf,:=,%d,$b,!,cf,:=,%d,$o,vf,:=",
r_strbuf_appendf (&op->esil,
",$z,zf,:=,%d,$s,nf,:=,%d,$b,!,cf,:=,%d,$o,vf,:=",
REGBITS64 (0) - 1, REGBITS64 (0), REGBITS64 (0) -1);
break;
@ -1414,7 +1414,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
case ARM64_FMOV:
{
if (0) {
r_strbuf_setf (&op->esil, "%sh,%sh,=,%sl,%sl,=",
r_strbuf_setf (&op->esil, "%sh,%sh,=,%sl,%sl,=",
REG64 (1), REG64 (0), REG64 (1), REG64 (0));
} else {
ARG64_APPEND (&op->esil, 1);
@ -1429,7 +1429,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
case ARM64_FCCMP:
case ARM64_FCCMPE:
if (ISREG64 (1)) {
r_strbuf_setf (&op->esil,
r_strbuf_setf (&op->esil,
"%d,%s,F2D,NAN,%d,%s,F2D,NAN,|,vf,:="
",%d,%s,F2D,%d,%s,F2D,F==,vf,|,zf,:="
",%d,%s,F2D,%d,%s,F2D,F<,vf,|,nf,:=",
@ -1438,7 +1438,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
REGBITS64 (1), REG64 (1), REGBITS64 (1), REG64 (0)
);
} else {
r_strbuf_setf (&op->esil,
r_strbuf_setf (&op->esil,
"%d,%s,F2D,NAN,vf,:="
",0,I2D,%d,%s,F2D,F==,vf,|,zf,:="
",0,I2D,%d,%s,F2D,F<,vf,|,nf,:=",
@ -1456,7 +1456,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
}
break;
case ARM64_FCVT:
r_strbuf_setf (&op->esil, "%d,%d,%s,F2D,D2F,%s,=",
r_strbuf_setf (&op->esil, "%d,%d,%s,F2D,D2F,%s,=",
REGBITS64 (0), REGBITS64 (1), REG64 (1), REG64 (0));
break;
case ARM64_SCVTF:
@ -1521,23 +1521,23 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
REGBITS64 (1), REG64 (1), REG64 (0));
break;
case ARM64_FNEG:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,-F,D2F,%s,=",
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1), REG64 (0));
break;
case ARM64_FSQRT:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,SQRT,D2F,%s,=",
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,SQRT,D2F,%s,=",
REGBITS64 (1), REG64 (1), REG64 (0));
break;
case ARM64_FMINNM:
case ARM64_FMIN:
r_strbuf_setf (&op->esil, "%d,%s,F2D,%d,%s,F2D,F<,?{,%s,}{,%s,},%s,=",
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,%s,F2D,%d,%s,F2D,F<,?{,%s,}{,%s,},%s,=",
REGBITS64 (2), REG64 (2),
REGBITS64 (1), REG64 (1), REG64 (1), REG64 (2), REG64 (0));
break;
case ARM64_FMAXNM:
case ARM64_FMAX:
r_strbuf_setf (&op->esil, "%d,%s,F2D,%d,%s,F2D,F<,!,?{,%s,}{,%s,},%s,=",
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,%s,F2D,%d,%s,F2D,F<,!,?{,%s,}{,%s,},%s,=",
REGBITS64 (2), REG64 (2),
REGBITS64 (1), REG64 (1), REG64 (1), REG64 (2), REG64 (0));
break;
case ARM64_FADD:
@ -1553,26 +1553,26 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
FPOPCALL_NEGATE("*");
break;
case ARM64_FMADD:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,%d,%s,F2D,F+,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,%d,%s,F2D,F+,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
REGBITS64 (3), REG64 (3), REG64 (0));
break;
case ARM64_FNMADD:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,-F,%d,%s,F2D,F+,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,-F,%d,%s,F2D,F+,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
REGBITS64 (3), REG64 (3), REG64 (0));
break;
case ARM64_FMSUB:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,%d,%s,F2D,F-,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,%d,%s,F2D,F-,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
REGBITS64 (3), REG64 (3), REG64 (0));
break;
case ARM64_FNMSUB:
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,-F,%d,%s,F2D,F-,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1),
r_strbuf_setf (&op->esil, "%d,DUP,%s,F2D,%d,%s,F2D,F*,-F,%d,%s,F2D,F-,-F,D2F,%s,=",
REGBITS64 (1), REG64 (1),
REGBITS64 (2), REG64 (2),
REGBITS64 (3), REG64 (3), REG64 (0));
break;
@ -1775,7 +1775,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
if (ISMEM64 (1)) {
if (HASMEMINDEX64 (1)) {
ARG64_APPEND (&op->esil, 1);
r_strbuf_appendf (&op->esil, ",%s,+,[%d],%s,=",
r_strbuf_appendf (&op->esil, ",%s,+,[%d],%s,=",
MEMBASE64 (1), size, REG64 (0));
} else {
if (LSHIFT2_64 (1)) {
@ -1935,7 +1935,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
ARG64_APPEND(&op->esil, 1);
COMMA(&op->esil);
ARG64_APPEND(&op->esil, 0);
r_strbuf_appendf (&op->esil, ",==,$z,zf,:=,%d,$s,nf,:=,%d,$b,!,cf,:=,%d,$o,vf,:=",
r_strbuf_appendf (&op->esil, ",==,$z,zf,:=,%d,$s,nf,:=,%d,$b,!,cf,:=,%d,$o,vf,:=",
REGBITS64 (0) - 1, REGBITS64 (0), REGBITS64 (0) -1);
if (insn->operation == ARM64_CCMP || insn->operation == ARM64_CCMN) {
@ -1980,7 +1980,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
r_strbuf_appendf (&op->esil, "%s,}{,1,%s,+,},%s,=", REG64 (1), REG64 (2), REG64 (0));
postfix = "";
break;
case ARM64_CINV:
case ARM64_CINV:
if ISCOND64(1) {
v35arm_prefix_cond (op, insn->operands[1].cond);
}
@ -1994,7 +1994,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
r_strbuf_appendf (&op->esil, "%s,}{,-1,%s,^,},%s,=", REG64 (1), REG64 (2), REG64 (0));
postfix = "";
break;
case ARM64_CNEG:
case ARM64_CNEG:
if ISCOND64(1) {
v35arm_prefix_cond (op, insn->operands[1].cond);
}
@ -2027,13 +2027,13 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
{
int size = REGSIZE64 (0);
switch (insn->operation) {
case ARM64_STRB:
case ARM64_STRB:
case ARM64_STURB:
case ARM64_STTRB:
{
size = 1;
break;
}
}
case ARM64_STRH:
case ARM64_STURH:
case ARM64_STTRH:
@ -2246,14 +2246,14 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
break;
case ARM64_RBIT:
// slightly shorter expression to reverse bits
r_strbuf_setf (&op->esil, "0,tmp,=,0,DUP,DUP,DUP,%d,-,%s,>>,1,&,<<,tmp,+=,%d,-,?{,++,4,GOTO,},tmp,%s,=",
r_strbuf_setf (&op->esil, "0,tmp,=,0,DUP,DUP,DUP,%d,-,%s,>>,1,&,<<,tmp,+=,%d,-,?{,++,4,GOTO,},tmp,%s,=",
REGBITS64 (1)-1, REG64 (1), REGBITS64 (1)-1, REG64 (0));
break;
case ARM64_MVN:
case ARM64_MOVN:
{
if (0) {
r_strbuf_setf (&op->esil, "%sh,-1,^,%sh,=,%sl,-1,^,%sl,=",
r_strbuf_setf (&op->esil, "%sh,-1,^,%sh,=,%sl,-1,^,%sl,=",
REG64 (1), REG64 (0), REG64 (1), REG64 (0));
} else {
ARG64_APPEND (&op->esil, 1);
@ -2418,7 +2418,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
case ARM64_SVC:
r_strbuf_setf (&op->esil, "%" PFMT64u ",$", GETIMM64 (0));
break;
default:
default:
break;
}

16
libr/anal/p/anal_dalvik.c
View File

@ -235,7 +235,7 @@ static void format51l(int len, const unsigned char* data, ut32* dst, st64* src)
#define OPCALL(x, y, z) dalvik_math_op(op, data, len, mask, x, y, z)
static void dalvik_math_op(RAnalOp* op, const unsigned char* data, int len,
static void dalvik_math_op(RAnalOp* op, const unsigned char* data, int len,
RAnalOpMask mask, char* operation, unsigned int optype, OperandType ot) {
ut32 vA = 0, vB = 0, vC = 0;
@ -275,7 +275,7 @@ static void dalvik_math_op(RAnalOp* op, const unsigned char* data, int len,
} else if (ot == OP_FLOAT) {
esilprintf (op, "32,32,v%u,F2D,32,v%u,F2D,F%s,D2F,v%u,=", vC, vB, operation, vA);
} else if (ot == OP_DOUBLE) {
esilprintf (op, GETWIDE "," GETWIDE ",F%s," SETWIDE,
esilprintf (op, GETWIDE "," GETWIDE ",F%s," SETWIDE,
vC+1, vC, vB+1, vB, operation, vA, vA+1);
}
}
@ -302,7 +302,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
vC = data[3];
}
switch (data[0]) {
case 0x00:
case 0x00:
op->type = R_ANAL_OP_TYPE_NOP;
if (mask & R_ANAL_OP_MASK_ESIL) {
esilprintf (op, ",");
@ -784,8 +784,8 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
case 0xeb: // sput-wide-volatile
case 0xf5: // iput-quick
case 0xf6:
case 0xfc:
case 0xfe:
case 0xfc:
case 0xfe:
op->type = R_ANAL_OP_TYPE_STORE;
vC = len > 3?(data[3] << 8) | data[2] : 0;
op->ptr = anal->binb.get_offset (anal->binb.bin, 'f', vC);
@ -858,7 +858,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
op->type = R_ANAL_OP_TYPE_CAST;
format12x(len, data, &vA, &vB);
// do all the casting here
// do all the casting here
if (mask & R_ANAL_OP_MASK_ESIL) {
// op->refptr = 0;
// many of these might need sign extensions
@ -878,7 +878,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
case 0x85:
esilprintf (op, "32," GETWIDE ",I2D,D2F,v%u,=", vB+1, vB, vA);
break;
case 0x86:
case 0x86:
esilprintf (op, GETWIDE ",I2D," SETWIDE, vB+1, vB, vA, vA+1);
break;
case 0x87:
@ -906,7 +906,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
case 0x8f:
esilprintf (op, "v%u,0xffff,&,v%u,=", vB, vA);
break;
default:
default:
break;
}
}

2
libr/anal/p/anal_gb.c
View File

@ -717,7 +717,7 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len
op->type = R_ANAL_OP_TYPE_ILL;
op->size = 0;
return 0;
}
}
if (mask & R_ANAL_OP_MASK_DISASM) {
char mn[32];
memset (mn, '\0', sizeof (char) * sizeof (mn));

8
libr/anal/p/anal_mips_cs.c
View File

@ -790,7 +790,7 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
case MIPS_INS_LBU:
case MIPS_INS_LBUX:
op->refptr = 1;
/* fallthrough */
/* fallthrough */
case MIPS_INS_LW:
case MIPS_INS_LWC1:
case MIPS_INS_LWC2:
@ -800,7 +800,7 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
if (!op->refptr) {
op->refptr = 4;
}
/* fallthrough */
/* fallthrough */
case MIPS_INS_LD:
case MIPS_INS_LDC1:
case MIPS_INS_LDC2:
@ -860,7 +860,7 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
op->jump = t9_pre;
t9_pre = UT64_MAX;
op->type = R_ANAL_OP_TYPE_RCALL;
}
}
break;
case MIPS_INS_JAL:
case MIPS_INS_JALS:
@ -918,7 +918,7 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
op->type = R_ANAL_OP_TYPE_ADD;
if (REGID(0) == MIPS_REG_T9) {
t9_pre += IMM(2);
}
}
if (REGID(0) == MIPS_REG_SP) {
op->stackop = R_ANAL_STACK_INC;
op->stackptr = -IMM(2);

10
libr/anal/p/anal_mips_gnu.c
View File

@ -829,7 +829,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, gnu_insn*insn) {
break;
case MIPS_INS_J:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_J ("%s"), J_REG (jump));
case MIPS_INS_B:
case MIPS_INS_B:
// jump to address with conditional
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_J ("%s"), I_REG (jump));
break;
@ -872,7 +872,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, gnu_insn*insn) {
I_REG (rs), I_REG (jump));
break;
case MIPS_INS_BLTZAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_D ("%s") ",}",
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_D ("%s") ",}",
I_REG (rs), I_REG (jump));
break;
case MIPS_INS_BLTZ:
@ -917,7 +917,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, gnu_insn*insn) {
case MIPS_INS_NEGU:
break;
/** signed -- sets overflow flag */
case MIPS_INS_ADD:
case MIPS_INS_ADD:
ES_ADD_CK32_OVERF(R_REG (rs), R_REG (rt), R_REG (rd));
break;
case MIPS_INS_ADDI:
@ -947,7 +947,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, gnu_insn*insn) {
case MIPS_INS_LUI:
r_strbuf_appendf (&op->esil, "%s0000,%s,=",I_REG (imm), I_REG (rt));
break;
case MIPS_INS_LB:
case MIPS_INS_LB:
op->sign = true; //To load a byte from memory as a signed value
/* fallthrough */
case MIPS_INS_LBU:
@ -1372,7 +1372,7 @@ static int mips_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len, R
snprintf ((char *)insn.i_reg.imm, REG_BUF_MAX, "%"PFMT32d, imm);
switch (optype) {
case 1:
case 1:
switch (rt) {
case 0: //bltz
insn.id = MIPS_INS_BLTZ;

2
libr/anal/p/anal_riscv.c
View File

@ -445,7 +445,7 @@ static int riscv_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
} else if (!strncmp (name, "csrrc", 5)) {
// Ands the inverse of rs1 with CSR, places old value in rd
esilprintf (op, "%s,0,+,%s,1,+,0,-,%s,&=,%s,=", ARG (1), ARG (1), ARG (2), ARG (0));
}
}
// stores
else if (!strcmp (name, "sd") || !strcmp (name, "sdsp")) {
esilprintf (op, "%s,%s,%s,+,=[8]", ARG (0), ARG (2), ARG (1));

2
libr/anal/p/anal_vax.c
View File

@ -72,7 +72,7 @@ static int vax_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
op->size = 7;
op->type = R_ANAL_OP_TYPE_MOV;
break;
case 0xd4: //
case 0xd4: //
op->size = 3;
op->type = R_ANAL_OP_TYPE_NOP;
break;

10
libr/anal/p/anal_x86_cs.c
View File

@ -1673,12 +1673,12 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
op->sign = true;
if (!arg2 && !arg1) {
// TODO: IDIV rbx not implemented. this is just a workaround
//
//
// http://www.tptp.cc/mirrors/siyobik.info/instruction/IDIV.html
// Divides (signed) the value in the AX, DX:AX, or EDX:EAX registers (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size (dividend/divisor), as shown in the following table:
// IDIV RBX == RDX:RAX /= RBX
//
//
if (arg0) {
int width = INSOP(0).size;
const char *r_quot = (width==1)?"al": (width==2)?"ax": (width==4)?"eax":"rax";
@ -1725,7 +1725,7 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
if (arg2) {
multiplier = arg2;
}
esilprintf (op, "%d,%s,~,%d,%s,~,*,DUP,%s,=,%d,%s,~,-,!,!,DUP,cf,:=,of,:=",
esilprintf (op, "%d,%s,~,%d,%s,~,*,DUP,%s,=,%d,%s,~,-,!,!,DUP,cf,:=,of,:=",
width*8, multiplier, width*8, arg1, arg0, width*8, arg0);
} else {
if (arg0) {
@ -1733,12 +1733,12 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
const char *r_rema = (width==1)?"ah": (width==2)?"dx": (width==4)?"edx":"rdx";
const char *r_nume = (width==1)?"ax": r_quot;
if (width == 8) { // TODO still needs to be fixed to handle correct signed 128 bit value
if (width == 8) { // TODO still needs to be fixed to handle correct signed 128 bit value
esilprintf (op, "%s,%s,L*,%s,=,DUP,%s,=,!,!,DUP,cf,:=,of,:=", // flags will be sometimes wrong
arg0, r_nume, r_nume, r_rema);
} else {
esilprintf (op, "%d,%s,~,%d,%s,~,*,DUP,DUP,%s,=,%d,SWAP,>>,%s,=,%d,%s,~,-,!,!,DUP,cf,:=,of,:=",
width*8, arg0, width*8, r_nume, r_nume, width*8, r_rema, width*8, r_nume);
width*8, arg0, width*8, r_nume, r_nume, width*8, r_rema, width*8, r_nume);
}
}
}

2
libr/anal/p/arm_v35.mk
View File

@ -16,7 +16,7 @@ TARGET_ARM_V35=$(N).${LIBEXT}
ALL_TARGETS+=$(TARGET_ARM_V35)
$(TARGET_ARM_V35):
$(TARGET_ARM_V35):
# $(STATIC_OBJ)
${CC} $(V35ARM64_CFLAGS) ${CFLAGS} $(call libname,$(N)) \
-lr_util -lr_search \

26
libr/anal/type_pdb.c
View File

@ -13,8 +13,8 @@ static bool is_parsable_type(const ELeafType type) {
/**
* @brief Create a type name from offset
*
* @param offset
*
* @param offset
* @return char* Name or NULL if error
*/
static char *create_type_name_from_offset(ut64 offset) {
@ -26,7 +26,7 @@ static char *create_type_name_from_offset(ut64 offset) {
/**
* @brief Parses class/struct/union member
*
*
* @param type_info Current type info (member)
* @param types List of all types
* @return RAnalStructMember* parsed member, NULL if fail
@ -60,10 +60,10 @@ cleanup:
/**
* @brief Parse enum case
*
*
* @param type_info Current type info (enum case)
* @param types List of all types
* @return RAnalEnumCase* parsed enum case, NULL if fail
* @return RAnalEnumCase* parsed enum case, NULL if fail
*/
static RAnalEnumCase *parse_enumerate(STypeInfo *type_info, RList *types) {
r_return_val_if_fail (type_info && types && type_info->leaf_type == eLF_ENUMERATE, NULL);
@ -88,10 +88,10 @@ cleanup:
/**
* @brief Parses enum into BaseType and saves it into SDB
*
* @param anal
*
* @param anal
* @param type Current type
* @param types List of all types
* @param types List of all types
*/
static void parse_enum(const RAnal *anal, SType *type, RList *types) {
r_return_if_fail (anal && type && types);
@ -152,8 +152,8 @@ cleanup:
/**
* @brief Parses classes, unions and structures into BaseType and saves them into SDB
*
* @param anal
*
* @param anal
* @param type Current type
* @param types List of all types
*/
@ -215,8 +215,8 @@ cleanup:
/**
* @brief Delegate the type parsing to appropriate function
*
* @param anal
*
* @param anal
* @param type Current type
* @param types List of all types
*/
@ -249,7 +249,7 @@ static void parse_type (const RAnal *anal, SType *type, RList *types) {
/**
* @brief Saves PDB types from TPI stream into the SDB
*
*
* @param anal
* @param pdb PDB information
*/

2
libr/anal/var.c
View File

@ -1147,7 +1147,7 @@ R_API void r_anal_extract_rarg(RAnal *anal, RAnalOp *op, RAnalFunction *fcn, int
if (callee) {
callee_rargs = R_MIN (max_count, r_type_func_args_count (TDB, callee));
}
callee_rargs = callee_rargs
callee_rargs = callee_rargs
? callee_rargs
: r_anal_var_count (anal, f, R_ANAL_VAR_KIND_REG, 1);
callee_rargs_l = r_anal_var_list (anal, f, R_ANAL_VAR_KIND_REG);

2
libr/asm/arch/arc/gnu/arc-ext.h
View File

@ -4,7 +4,7 @@
Copyright 2008-2012 Synopsys Inc.
This file is part of libopcodes.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)

2
libr/asm/arch/arc/gnu/arc-opc.c
View File

@ -4444,7 +4444,7 @@ arc_opcode_lookup_dis (unsigned int insn)
}
/* START ARC LOCAL */
int
int
arc_test_wb (void)
{
return addrwb_p;

2
libr/asm/arch/arc/gnu/arc.h
View File

@ -356,7 +356,7 @@ struct arc_operand {
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged.
REG is non-NULL when inserting a register value.
REG is non-NULL when inserting a register value.
extend is only meaningful for extended length instructions
and the special fields that use them.
*/

2
libr/asm/arch/arm/aarch64/aarch64-tbl.h
View File

@ -3965,7 +3965,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("ldff1sw", 0xc540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xc560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xc520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0x85006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0x85206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, F_OD(1), 0),

42
libr/asm/arch/arm/armass.c
View File

@ -1698,7 +1698,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
default:
return -1;
}
} else
} else
if (( m = opmask (ao->op, "blx", 0) )) {
ut64 argt = thumb_selector (ao->a);
switch (argt) {
@ -2596,10 +2596,10 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
}
if (ldrsel == 0) {
ao->o = 0x50f80009;
} else
} else
if (ldrsel == B_BIT) {
ao->o = 0x10f80009;
} else
} else
if (ldrsel == H_BIT) {
ao->o = 0x30f80009;
} else {
@ -2626,10 +2626,10 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
}
if (ldrsel == 0) {
ao->o = 0x50f8000d;
} else
} else
if (ldrsel == B_BIT) {
ao->o = 0x10f8000d;
} else
} else
if (ldrsel == H_BIT) {
ao->o = 0x30f8000d;
} else {
@ -3102,7 +3102,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
default:
return -1;
}
} else
} else
if ((m = opmask (ao->op, "mrc", TWO_BIT))) {
ut64 argt = thumb_selector (ao->a);
switch (argt) {
@ -3198,7 +3198,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
default:
return -1;
}
} else
} else
if ((m = opmask (ao->op, "msr", 0))) {
ut64 argt = thumb_selector (ao->a);
switch (argt) {
@ -3360,7 +3360,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
default:
return -1;
}
} else
} else
if ((m = opmask (ao->op, "orr", S_BIT))) {
ut64 argt = thumb_selector (ao->a);
switch (argt) {
@ -3407,7 +3407,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
default:
return -1;
}
} else
} else
if ((m = opmask (ao->op, "pkh", BT_BIT | TB_BIT))) {
ut64 argt = thumb_selector (ao->a);
switch (argt) {
@ -4844,10 +4844,10 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
if (strsel == 0) {
ao->o = 0x40f80009;
} else
} else
if (strsel == B_BIT) {
ao->o = 0x00f80009;
} else
} else
if (strsel == H_BIT) {
ao->o = 0x20f80009;
} else {
@ -4874,10 +4874,10 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
if (strsel == 0) {
ao->o = 0x40f8000d;
} else
} else
if (strsel == B_BIT) {
ao->o = 0x00f8000d;
} else
} else
if (strsel == H_BIT) {
ao->o = 0x20f8000d;
} else {
@ -4931,10 +4931,10 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
if (strsel == 0) {
ao->o = 0x40f80000;
} else
} else
if (strsel == B_BIT) {
ao->o = 0x00f80000;
} else
} else
if (strsel == H_BIT) {
ao->o = 0x20f80000;
} else {
@ -5097,7 +5097,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
}
break;
}
} else
} else
if ((m = opmask (ao->op, "sub", S_BIT | W_BIT))) {
ut64 argt = thumb_selector (ao->a);
switch (argt) {
@ -5539,7 +5539,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
case THUMB_REG_REG_REG: {
if (sufsel == EIGHT_BIT) {
ao->o = 0x80fa60f0;
} else
} else
if (sufsel == SIXTEEN_BIT) {
ao->o = 0x90fa60f0;
} else {
@ -5599,7 +5599,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
case THUMB_REG_REG_REG: {
if (sufsel == EIGHT_BIT) {
ao->o = 0xc0fa60f0;
} else
} else
if (sufsel == SIXTEEN_BIT) {
ao->o = 0xd0fa60f0;
} else {
@ -5699,7 +5699,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
case THUMB_REG_REG_REG: {
if (sufsel == EIGHT_BIT) {
ao->o = 0x80fa50f0;
} else
} else
if (sufsel == SIXTEEN_BIT) {
ao->o = 0x90fa50f0;
} else {
@ -5758,7 +5758,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
case THUMB_REG_REG_REG: {
if (sufsel == EIGHT_BIT) {
ao->o = 0xc0fa50f0;
} else
} else
if (sufsel == SIXTEEN_BIT) {
ao->o = 0xd0fa50f0;
} else {
@ -5889,7 +5889,7 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
case THUMB_REG_REG_REG: {
if (sufsel == EIGHT_BIT) {
ao->o = 0xc0fa40f0;
} else
} else
if (sufsel == SIXTEEN_BIT) {
ao->o = 0xd0fa40f0;
} else {

2
libr/asm/arch/arm/armass64.c
View File

@ -349,7 +349,7 @@ static ut32 cmp(ArmOp *op) {
} else if (op->operands[0].type & ARM_GPR && op->operands[1].type & ARM_CONSTANT) {
if (op->operands[0].reg_type & ARM_REG64) {
k = 0x1f0000f1;
} else {
} else {
k = 0x1f000071;
}
k |= ( op->operands[1].immediate * 4 ) << 16 ;

6
libr/asm/arch/arm/gnu/floatformat.c
View File

@ -449,7 +449,7 @@ get_field (const unsigned char *data, enum floatformat_byteorders order,
lo_bit = start % FLOATFORMAT_CHAR_BIT;
hi_bit = min (lo_bit + len, FLOATFORMAT_CHAR_BIT);
do
{
unsigned int shifted = *(data + cur_byte) >> lo_bit;
@ -466,7 +466,7 @@ get_field (const unsigned char *data, enum floatformat_byteorders order,
return result;
}
/* Convert from FMT to a double.
FROM is the address of the extended float.
Store the double in *TO. */
@ -591,7 +591,7 @@ put_field (unsigned char *data, enum floatformat_byteorders order,
lo_bit = start % FLOATFORMAT_CHAR_BIT;
hi_bit = min (lo_bit + len, FLOATFORMAT_CHAR_BIT);
do
{
unsigned char *byte_ptr = data + cur_byte;

2
libr/asm/arch/arm/winedbg/be_arm.c
View File

@ -871,7 +871,7 @@ int arm_disasm_one_insn(struct winedbg_arm_insn *arminsn) {
}
else {
t2_ptr->func(arminsn, inst);
}
}
arminsn->str_hex = r_str_appendf (arminsn->str_hex, "%02x%02x%02x%02x",
*((ut8*)(&inst)), *((ut8*)(&inst)+1), *((ut8*)(&inst)+2), *((ut8*)(&inst)+3));
return size;

16
libr/asm/arch/avr/avr_disasm.c
View File

@ -16,7 +16,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* avr_disasm.c - AVR instruction disassembly into disassembledInstruction structure.
*
@ -155,8 +155,8 @@ static int lookupInstruction(uint16_t opcode, int offset) {
/* We want to mask out all of the operands. We don't count up to
* instructionSet[insidx].numOperands because some instructions,
* such as clr R16, are actually encoded with two operands (so as eor R16,R16),
* and we want to screen out both operands to get the most simplest form of
* the instruction. */
* and we want to screen out both operands to get the most simplest form of
* the instruction. */
for (i = 0; i < AVR_MAX_NUM_OPERANDS; i++) {
if (instructionSet[insidx].operandTypes[i] == OPERAND_REGISTER_GHOST) {
/* Grab the first operand */
@ -167,7 +167,7 @@ static int lookupInstruction(uint16_t opcode, int offset) {
operandTemp)
ghostRegisterConfirmed = 0;
}
}
}
opcodeSearch &= ~(instructionSet[insidx].operandMasks[i]);
}
/* If we encountered a ghost register and were unable confirm that
@ -176,11 +176,11 @@ static int lookupInstruction(uint16_t opcode, int offset) {
if (ghostRegisterConfirmed == 0)
continue;
if (opcodeSearch == instructionSet[insidx].opcodeMask)
if (opcodeSearch == instructionSet[insidx].opcodeMask)
break;
}
/* It's impossible not to find an instruction, because the last instruction ".DW",
* specifies a word of data at the addresses, instead of an instruction.
* specifies a word of data at the addresses, instead of an instruction.
* Its operand 2 mask, 0x0000, will set opcode search to 0x0000, and this will always
* match with the opcodeMask of 0x0000. */
return insidx;
@ -211,7 +211,7 @@ static int disassembleOperands(disassembledInstruction *dInstruction) {
* by two. */
/* Next, we check for the signed bit (MSB), which would indicate a
* negative. If the number is signed, we would reverse the two's
* complement (invert bits, add 1, and then only use the 7 bits that
* complement (invert bits, add 1, and then only use the 7 bits that
* matter), otherwise, the number represents a positive distance and
* no bit manipulation is necessary. */
dInstruction->operands[i] <<= 1;
@ -238,7 +238,7 @@ static int disassembleOperands(disassembledInstruction *dInstruction) {
* by two. */
/* Next, we check for the signed bit (MSB), which would indicate a
* negative. If the number is signed, we would reverse the two's
* complement (invert bits, add 1, and then only use the 12 bits that
* complement (invert bits, add 1, and then only use the 12 bits that
* matter), otherwise, the number represents a positive distance and
* no bit manipulation is necessary. */
dInstruction->operands[i] <<= 1;

6
libr/asm/arch/avr/avr_disasm.h
View File

@ -16,9 +16,9 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* avr_disasm.h - Header file for AVR instruction disassembly into
* avr_disasm.h - Header file for AVR instruction disassembly into
* disassembledInstruction structure.
*
*/
@ -52,7 +52,7 @@ typedef struct _assembledInstruction assembledInstruction;
/* The disassembled/decoded instruction. */
struct _disassembledInstruction {
uint32_t address;
/* A convenient pointer to the instructionSet, so we can refer
/* A convenient pointer to the instructionSet, so we can refer
* the general details of the instruction stored in there. */
instructionInfo *instruction;
/* Notice that operands can be signed!

12
libr/asm/arch/avr/avr_instructionset.c
View File

@ -16,7 +16,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* avrinstructionset.c - AVR instruction set data structure stored in an
* array of instruction info structures, as defined in avrdisasm.h.
@ -29,7 +29,7 @@
/* I decided to have the operand masks and types here in the
* main instruction set data structure of the disassembler for clean
* opcode recognition and operand extraction. It's much more straight
* forward to work with numbers (duh) then manipulating ugly operand
* forward to work with numbers (duh) then manipulating ugly operand
* strings such as "000011rdddddrrrr" for the add instruction. */
/* This was my first disassembler, and my program ended evolving with this
* data structure. Turns out it makes code quite clear, and it generalizes the
@ -37,9 +37,9 @@
* instead of hard coding the disassembly for different types of operands. */
/* But this disassembler model can be applied to virtually any 16-bit
* or less opcode architecture, making it very flexible in nature--I don't
* have to rewrite all of the operand disassembly code for interpreting
* different r, d, K, k, s, etc. characters in the opcode, which all stand
* for a different operand type, because they are clearly written out
* have to rewrite all of the operand disassembly code for interpreting
* different r, d, K, k, s, etc. characters in the opcode, which all stand
* for a different operand type, because they are clearly written out
* in the instruction set data structure.
*/
@ -97,7 +97,7 @@ instructionInfo instructionSet[AVR_TOTAL_INSTRUCTIONS] = {
{"brvs", 0xf003, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
{"bset", 0x9408, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}},
{"call", 0x940e, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}},
{"clr", 0x2400, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
{"clr", 0x2400, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
{"com", 0x9400, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
{"dec", 0x940a, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
{"inc", 0x9403, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},

2
libr/asm/arch/avr/errorcodes.h
View File

@ -16,7 +16,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* errorcodesdisasm.h - All error codes that can take place during disassembler
* operation.

2
libr/asm/arch/avr/format.c
View File

@ -72,7 +72,7 @@ int printDisassembledInstruction(avrDisassembleContext *context, char *out, cons
* pointer to a C-string strOperand, which must be free'd after it has been used.
* I decided to format the disassembled operands individually into strings for maximum flexibility,
* and so that the printing of the formatted operand is not hard coded into the format operand code.
* If an addressLabelPrefix is specified in formattingOptions (option is set and string is not NULL),
* If an addressLabelPrefix is specified in formattingOptions (option is set and string is not NULL),
* it will print the relative branch/jump/call with this prefix and the destination address as the label. */
static int formatDisassembledOperand(avrDisassembleContext *context, char *strOperand, int operandNum, const disassembledInstruction dInstruction, formattingOptions fOptions) {
char binary[9];

4
libr/asm/arch/avr/format.h
View File

@ -16,13 +16,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* format_disasm.h - Header file to formatting of disassembled instructions, with
* regard to the several formatting features this disasssembler supports.
*
*/
#include "avr_disasm.h"
#include "errorcodes.h"

4
libr/asm/arch/dcpu16/asm.c
View File

@ -197,9 +197,9 @@ static ut8 decode_parameter(char* param, int* extra_word_needed, ut16* extra_wor
/* Must be a label, store a labelref */
*extra_word_needed = 1;
/* Allocate blank extra word, this will be where the
/* Allocate blank extra word, this will be where the
pointer to the label will be stored at link stage */
*extra_word_value = 0;
*extra_word_value = 0;
return 0x1f;
}

8
libr/asm/arch/dcpu16/main.c
View File

@ -7,10 +7,10 @@ int main(int argc, char **argv) {
if (argc>1) {
char out[32];
ut8 buf[64] = {
0x01, 0x7c, 0x30, 0x00, 0xe1, 0x7d, 0x00, 0x10, 0x20, 0x00, 0x03,
0x78, 0x00, 0x10, 0x0d, 0xc0, 0xc1, 0x7d, 0x1a, 0x00, 0x61, 0xa8,
0x01, 0x7c, 0x00, 0x20, 0x61, 0x21, 0x00, 0x20, 0x63, 0x84, 0x6d,
0x80, 0xc1, 0x7d, 0x0d, 0x00, 0x31, 0x90, 0x10, 0x7c, 0x18, 0x00,
0x01, 0x7c, 0x30, 0x00, 0xe1, 0x7d, 0x00, 0x10, 0x20, 0x00, 0x03,
0x78, 0x00, 0x10, 0x0d, 0xc0, 0xc1, 0x7d, 0x1a, 0x00, 0x61, 0xa8,
0x01, 0x7c, 0x00, 0x20, 0x61, 0x21, 0x00, 0x20, 0x63, 0x84, 0x6d,
0x80, 0xc1, 0x7d, 0x0d, 0x00, 0x31, 0x90, 0x10, 0x7c, 0x18, 0x00,
0xc1, 0x7d, 0x1a, 0x00, 0x37, 0x90, 0xc1, 0x61, 0xc1, 0x7d, 0x1a,
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, };
int len = sizeof (buf)-1;

2
libr/asm/arch/gb/gbasm.c
View File

@ -557,7 +557,7 @@ static int gbAsm(RAsm *a, RAsmOp *op, const char *buf) {
}
}
break;
case 0x63616c6c: //call
case 0x63616c6c: //call
if (strlen(buf_asm) < 6) {
return op->size = 0;
}

158
libr/asm/arch/hexagon/hexagon_disas.c
View File

@ -23575,7 +23575,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->ops[4].type = HEX_OP_TYPE_IMM;
hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm);
break;
}
@ -23665,7 +23665,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->ops[4].type = HEX_OP_TYPE_IMM;
hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm);
break;
}
@ -23753,7 +23753,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->ops[4].type = HEX_OP_TYPE_IMM;
hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm);
break;
}
@ -23841,7 +23841,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->ops[4].type = HEX_OP_TYPE_IMM;
hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm);
break;
}
@ -23929,7 +23929,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->ops[4].type = HEX_OP_TYPE_IMM;
hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm);
break;
}
@ -24017,7 +24017,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->ops[4].type = HEX_OP_TYPE_IMM;
hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm);
break;
}
@ -24441,7 +24441,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->ops[4].type = HEX_OP_TYPE_REG;
hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg);
break;
}
@ -24529,7 +24529,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->ops[4].type = HEX_OP_TYPE_REG;
hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg);
break;
}
@ -24617,7 +24617,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->ops[4].type = HEX_OP_TYPE_REG;
hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg);
break;
}
@ -24708,7 +24708,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[4].type = HEX_OP_TYPE_REG;
hi->ops[4].attr |= HEX_OP_REG_PAIR;
hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0);
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg);
break;
}
@ -24816,7 +24816,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->ops[4].type = HEX_OP_TYPE_REG;
hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg);
break;
}
@ -24890,7 +24890,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 5)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 5);
}
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm);
break;
}
@ -25032,7 +25032,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->ops[4].type = HEX_OP_TYPE_REG;
hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg);
break;
}
@ -25050,7 +25050,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->ops[4].type = HEX_OP_TYPE_REG;
hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg);
break;
}
@ -25160,7 +25160,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 5)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 5);
}
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm);
break;
}
@ -25268,7 +25268,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7));
hi->ops[4].type = HEX_OP_TYPE_REG;
hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg);
break;
}
@ -25342,7 +25342,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 5)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 5);
}
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm);
break;
}
@ -25449,7 +25449,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_IMM;
hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 3; // scaled
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend_off(&hi->ops[3], 3);
sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm);
break;
@ -25530,7 +25530,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_IMM;
hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5);
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend(&hi->ops[3]);
sprintf(hi->mnem, "if !P%d R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm);
break;
@ -25610,7 +25610,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_IMM;
hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend_off(&hi->ops[3], 1);
sprintf(hi->mnem, "if !P%d R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm);
break;
@ -25690,7 +25690,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_IMM;
hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5);
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend(&hi->ops[3]);
sprintf(hi->mnem, "if !P%d R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm);
break;
@ -25770,7 +25770,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_IMM;
hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend_off(&hi->ops[3], 1);
sprintf(hi->mnem, "if !P%d R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm);
break;
@ -25851,7 +25851,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_IMM;
hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 2; // scaled
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend_off(&hi->ops[3], 2);
sprintf(hi->mnem, "if !P%d R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm);
break;
@ -25930,7 +25930,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3));
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -26006,7 +26006,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -26082,7 +26082,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -26164,7 +26164,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].attr |= HEX_OP_REG_PAIR;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8);
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
hex_op_extend_off(&hi->ops[2], 3);
sprintf(hi->mnem, "if !P%d memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg);
break;
@ -26246,7 +26246,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3));
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
hex_op_extend(&hi->ops[2]);
sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
@ -26370,7 +26370,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
hex_op_extend_off(&hi->ops[2], 1);
sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
@ -26387,7 +26387,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -26482,7 +26482,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
hex_op_extend_off(&hi->ops[2], 2);
sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
@ -26537,7 +26537,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8);
hi->ops[1].type = HEX_OP_TYPE_REG;
hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d callr R%d", hi->ops[0].op.pred, hi->ops[1].op.reg);
break;
}
@ -26617,7 +26617,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8);
hi->ops[1].type = HEX_OP_TYPE_REG;
hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg);
break;
}
@ -26641,7 +26641,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8);
hi->ops[1].type = HEX_OP_TYPE_REG;
hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg);
break;
}
@ -26698,7 +26698,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[1].op.imm & (1 << 16)) {
hi->ops[1].op.imm |= (0xFFFFFFFF << 16);
}
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
hex_op_extend_off(&hi->ops[1], 2);
sprintf(hi->mnem, "if !P%d call 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm);
break;
@ -26758,7 +26758,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[1].op.imm & (1 << 16)) {
hi->ops[1].op.imm |= (0xFFFFFFFF << 16);
}
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm);
break;
}
@ -26773,7 +26773,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[1].op.imm & (1 << 16)) {
hi->ops[1].op.imm |= (0xFFFFFFFF << 16);
}
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d jump:t 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm);
break;
}
@ -28326,7 +28326,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 7)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 7);
}
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
hex_op_extend(&hi->ops[3]);
sprintf(hi->mnem, "if !P%d R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm);
break;
@ -28389,7 +28389,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg);
break;
}
@ -28445,7 +28445,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg);
break;
}
@ -28501,7 +28501,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg);
break;
}
@ -28557,7 +28557,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg);
break;
}
@ -28624,7 +28624,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[2].op.imm & (1 << 11)) {
hi->ops[2].op.imm |= (0xFFFFFFFF << 11);
}
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
hex_op_extend(&hi->ops[2]);
sprintf(hi->mnem, "if !P%d R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm);
break;
@ -28685,7 +28685,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg);
break;
}
@ -28741,7 +28741,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg);
break;
}
@ -31526,7 +31526,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 6)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 6);
}
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm);
break;
}
@ -31597,7 +31597,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0);
hi->ops[2].type = HEX_OP_TYPE_IMM;
hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8));
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend(&hi->ops[2]);
sprintf(hi->mnem, "if !P%d R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm);
break;
@ -31796,7 +31796,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 3)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 3);
}
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
sprintf(hi->mnem, "if !P%d R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm);
break;
}
@ -31863,7 +31863,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_IMM;
hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8));
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend(&hi->ops[2]);
sprintf(hi->mnem, "if !P%d R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm);
break;
@ -32326,7 +32326,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 4)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 4);
}
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
sprintf(hi->mnem, "if !P%d R%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm);
break;
}
@ -32393,7 +32393,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_IMM;
hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8));
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend(&hi->ops[2]);
sprintf(hi->mnem, "if !P%d R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm);
break;
@ -32590,7 +32590,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 3)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 3);
}
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
sprintf(hi->mnem, "if !P%d R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm);
break;
}
@ -32657,7 +32657,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_IMM;
hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8));
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend(&hi->ops[2]);
sprintf(hi->mnem, "if !P%d R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm);
break;
@ -32854,7 +32854,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 4)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 4);
}
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
sprintf(hi->mnem, "if !P%d R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm);
break;
}
@ -32921,7 +32921,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_IMM;
hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8));
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend(&hi->ops[2]);
sprintf(hi->mnem, "if !P%d R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm);
break;
@ -33118,7 +33118,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
if (hi->ops[3].op.imm & (1 << 5)) {
hi->ops[3].op.imm |= (0xFFFFFFFF << 5);
}
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
sprintf(hi->mnem, "if !P%d R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm);
break;
}
@ -33185,7 +33185,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd
hi->ops[2].type = HEX_OP_TYPE_IMM;
hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8));
hi->predicate = HEX_PRED_FALSE; // if !Pt
hi->predicate = HEX_PRED_FALSE; // if !Pt
hex_op_extend(&hi->ops[2]);
sprintf(hi->mnem, "if !P%d R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm);
break;
@ -34027,7 +34027,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
}
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -34093,7 +34093,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3));
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg);
break;
}
@ -34286,7 +34286,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
}
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -34352,7 +34352,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3));
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg);
break;
}
@ -34545,7 +34545,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
}
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -34612,7 +34612,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3));
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
hex_op_extend(&hi->ops[1]);
sprintf(hi->mnem, "if !P%d memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg);
break;
@ -34819,7 +34819,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].attr |= HEX_OP_REG_PAIR;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8);
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg);
break;
}
@ -34889,7 +34889,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].attr |= HEX_OP_REG_PAIR;
hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8);
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg);
break;
}
@ -35085,7 +35085,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
}
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -35151,7 +35151,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3));
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg);
break;
}
@ -35470,7 +35470,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
}
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -35546,7 +35546,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
}
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -35612,7 +35612,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3));
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg);
break;
}
@ -35668,7 +35668,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3));
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg);
break;
}
@ -35862,7 +35862,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
}
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
sprintf(hi->mnem, "if !P%d memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg);
break;
}
@ -35929,7 +35929,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3));
hi->ops[2].type = HEX_OP_TYPE_REG;
hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pv
hi->predicate = HEX_PRED_FALSE; // if !Pv
hex_op_extend(&hi->ops[1]);
sprintf(hi->mnem, "if !P%d memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg);
break;
@ -44910,7 +44910,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg);
break;
}
@ -44976,7 +44976,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg);
break;
}
@ -45042,7 +45042,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg);
break;
}
@ -45106,7 +45106,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg);
break;
}
@ -45170,7 +45170,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg);
break;
}
@ -45234,7 +45234,7 @@ int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {
hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt
hi->ops[3].type = HEX_OP_TYPE_REG;
hi->ops[3].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs
hi->predicate = HEX_PRED_FALSE; // if !Pu
hi->predicate = HEX_PRED_FALSE; // if !Pu
sprintf(hi->mnem, "if !P%d R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg);
break;
}

4
libr/asm/arch/i8080/i8080dis.c
View File

@ -13,7 +13,7 @@
// publish, distribute, sublicense, and/or sell copies of the Software,
// and to permit persons to whom the Software is furnished to do so,
// subject to the following conditions:
//
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
@ -127,7 +127,7 @@ static int i8080_disasm(unsigned char const* const code, char* text, int text_sz
struct opcode_t const *op;
for (op = &opcodes[0]; op->size; ++op) {
int const grp = cmd &
~((op->arg1.mask << op->arg1.shift) |
~((op->arg1.mask << op->arg1.shift) |
(op->arg2.mask << op->arg2.shift));
int const branch = (grp == 0xc0 || grp == 0xc2 || grp == 0xc4);
if (grp == op->cmd) {

2
libr/asm/arch/i8080/i8080dis.h
View File

@ -13,7 +13,7 @@
// publish, distribute, sublicense, and/or sell copies of the Software,
// and to permit persons to whom the Software is furnished to do so,
// subject to the following conditions:
//
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//

2
libr/asm/arch/include/elf/mips.h
View File

@ -1,5 +1,5 @@
/*
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
of binutils-gdb.
*/
/* MIPS ELF support for BFD.

6
libr/asm/arch/include/elf/xtensa.h
View File

@ -37,7 +37,7 @@ START_RELOC_NUMBERS (elf_xtensa_reloc_type)
RELOC_NUMBER (R_XTENSA_PLT, 6)
RELOC_NUMBER (R_XTENSA_OP0, 8)
RELOC_NUMBER (R_XTENSA_OP1, 9)
RELOC_NUMBER (R_XTENSA_OP2, 10)
RELOC_NUMBER (R_XTENSA_OP2, 10)
RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11)
RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12)
RELOC_NUMBER (R_XTENSA_32_PCREL, 14)
@ -137,7 +137,7 @@ typedef struct property_table_entry_t
block is specified in the current block and the size of the current
block does not include any fill required to align to the next
block. */
#define XTENSA_PROP_LITERAL 0x00000001
#define XTENSA_PROP_INSN 0x00000002
#define XTENSA_PROP_DATA 0x00000004
@ -148,7 +148,7 @@ typedef struct property_table_entry_t
/* Instruction-only properties about code. */
#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
#define XTENSA_PROP_INSN_NO_REORDER 0x00000080
/* Historically, NO_TRANSFORM was a property of instructions,
/* Historically, NO_TRANSFORM was a property of instructions,
but it should apply to literals under certain circumstances. */
#define XTENSA_PROP_NO_TRANSFORM 0x00000100

6
libr/asm/arch/include/libiberty.h
View File

@ -1,7 +1,7 @@
/* Function declarations for libiberty.
Copyright 2001, 2002, 2005 Free Software Foundation, Inc.
Note - certain prototypes declared in this header file are for
functions whoes implementation copyright does not belong to the
FSF. Those prototypes are present in this file for reference
@ -23,7 +23,7 @@
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA.
Written by Cygnus Support, 1994.
The libiberty library provides a number of functions which are
@ -184,7 +184,7 @@ extern char * getpwd (void);
#ifdef __MINGW32__
/* Forward declaration to avoid #include <sys/time.h>. */
struct timeval;
extern int gettimeofday (struct timeval *, void *);
extern int gettimeofday (struct timeval *, void *);
#endif
/* Get the amount of time the process has run, in microseconds. */

2
libr/asm/arch/include/mybfd.h
View File

@ -1,5 +1,5 @@
/*
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
of binutils-gdb.
This file contains some manual modifications as additon of original generated file. */

2
libr/asm/arch/include/opcode/cris.h
View File

@ -340,7 +340,7 @@ extern const struct cris_opcode cris_opcodes[];
#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
/* Yet another add-on: the register in "target2" must be multiplied
by 4 (mutually exclusive with .._MULT2). */
by 4 (mutually exclusive with .._MULT2). */
#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
/* The register in "target2" is an indirect memory reference (of the

16
libr/asm/arch/include/opcode/hppa.h
View File

@ -33,7 +33,7 @@
* controled by the nullification bit, and conditional, which depends
* on the direction of the branch and its success or failure.
*
* NONE is unfortunately #defined in the hiux system include files.
* NONE is unfortunately #defined in the hiux system include files.
* #undef it away.
*/
#undef NONE
@ -257,7 +257,7 @@ Floating point registers all have 'f' as a prefix:
fC operand 3 register with L/R halves at 16:18,21:23
fe Like fT, but encoding is different.
fE Same as fe, except prints a space before register during disasm.
fx target register at 15 (only for PA 2.0 long format FLDD/FSTD).
fx target register at 15 (only for PA 2.0 long format FLDD/FSTD).
Float registers for fmpyadd and fmpysub:
@ -592,11 +592,11 @@ static const struct pa_opcode pa_opcodes[] =
{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0},
{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0},
{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0},
{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, 0},
{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, 0},
{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
@ -810,7 +810,7 @@ static const struct pa_opcode pa_opcodes[] =
{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0},
/* Floating Point Coprocessor Instructions. */
{ "fldw", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT},
{ "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT},
{ "fldw", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},

6
libr/asm/arch/include/opcode/lanai.h
View File

@ -34,7 +34,7 @@
* Arcadia, CA 91024 *
*************************************************************************/
/* initial version released 5/95 */
/* This file is based upon sparc.h from the Gnu binutils-2.5.2
/* This file is based upon sparc.h from the Gnu binutils-2.5.2
release, which had the following copyright notice: */
/* Definitions for opcode table for the sparc.
@ -56,7 +56,7 @@
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
USA. */
/* The Lanai opcode table (and other related data) is defined in
@ -144,7 +144,7 @@ Kinds of operands:
d Rd register.
4 Op1 (for RRR)
5 Op2 (for RRR)
5 Op2 (for RRR)
6 Op2 (for RRM)
J 0x????0000

4
libr/asm/arch/include/opcode/mips.h
View File

@ -1,5 +1,5 @@
/*
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
of binutils-gdb.
*/
/* mips.h. Mips opcode list for GDB, the GNU debugger.
@ -1159,7 +1159,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
#define INSN_ISA32R3 8
#define INSN_ISA32R5 9
#define INSN_ISA32R6 10
#define INSN_ISA64 11
#define INSN_ISA64 11
#define INSN_ISA64R2 12
#define INSN_ISA64R3 13
#define INSN_ISA64R5 14

20
libr/asm/arch/include/opcode/nios2.h
View File

@ -44,7 +44,7 @@ enum overflow_type
no_overflow
};
/* This structure holds information for a particular instruction.
/* This structure holds information for a particular instruction.
The args field is a string describing the operands. The following
letters can appear in the args:
@ -78,24 +78,24 @@ enum overflow_type
struct nios2_opcode
{
const char *name; /* The name of the instruction. */
const char *args; /* A string describing the arguments for this
const char *args; /* A string describing the arguments for this
instruction. */
const char *args_test; /* Like args, but with an extra argument for
const char *args_test; /* Like args, but with an extra argument for
the expected opcode. */
unsigned long num_args; /* The number of arguments the instruction
unsigned long num_args; /* The number of arguments the instruction
takes. */
unsigned long match; /* The basic opcode for the instruction. */
unsigned long mask; /* Mask for the opcode field of the
unsigned long mask; /* Mask for the opcode field of the
instruction. */
unsigned long pinfo; /* Is this a real instruction or instruction
unsigned long pinfo; /* Is this a real instruction or instruction
macro? */
enum overflow_type overflow_msg; /* Used to generate informative
enum overflow_type overflow_msg; /* Used to generate informative
message when fixup overflows. */
};
/* This value is used in the nios2_opcode.pinfo field to indicate that the
instruction is a macro or pseudo-op. This requires special treatment by
the assembler, and is used by the disassembler to determine whether to
/* This value is used in the nios2_opcode.pinfo field to indicate that the
instruction is a macro or pseudo-op. This requires special treatment by
the assembler, and is used by the disassembler to determine whether to
check for a nop. */
#define NIOS2_INSN_MACRO 0x80000000
#define NIOS2_INSN_MACRO_MOV 0x80000001

2
libr/asm/arch/include/opintl.h
View File

@ -23,7 +23,7 @@
#ifdef ENABLE_NLS
# include <libintl.h>
/* Note the use of dgetext() and PACKAGE here, rather than gettext().
This is because the code in this directory is used to build a library which
will be linked with code in other directories to form programs. We want to
maintain a separate translation file for this directory however, rather

4
libr/asm/arch/include/symcat.h
View File

@ -11,7 +11,7 @@
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
@ -44,6 +44,6 @@
bar", "XSTRING(foo)", to yield "bar". Be aware that this only
works for __STDC__, not for traditional C which will still resolve
to "foo". */
#define XSTRING(s) STRINGX(s)
#define XSTRING(s) STRINGX(s)
#endif /* SYM_CAT_H */

2
libr/asm/arch/include/wine-arm.h
View File

@ -120,7 +120,7 @@
#define ARM_DTX_LOAD (0x01<<20)
#define ARM_DTX_STORE 0x00
// mascara registre desti
// mascara registre desti
#define ARM_DTX_RD_MASK ( 0x0F << 12 )

12
libr/asm/arch/include/xtensa-isa.h
View File

@ -15,7 +15,7 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
USA. */
#ifndef XTENSA_LIBISA_H
@ -184,7 +184,7 @@ typedef xtensa_insnbuf_word *xtensa_insnbuf;
/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */
extern int
xtensa_insnbuf_size (xtensa_isa isa);
xtensa_insnbuf_size (xtensa_isa isa);
/* Allocate an xtensa_insnbuf of the right size. */
@ -240,7 +240,7 @@ xtensa_isa_free (xtensa_isa isa);
/* Get the maximum instruction size in bytes. */
extern int
xtensa_isa_maxlength (xtensa_isa isa);
xtensa_isa_maxlength (xtensa_isa isa);
/* Decode the length in bytes of an instruction in raw memory (not an
@ -260,7 +260,7 @@ xtensa_isa_length_from_chars (xtensa_isa isa, const unsigned char *cp);
stages before stage 0. Returns XTENSA_UNDEFINED on error. */
extern int
xtensa_isa_num_pipe_stages (xtensa_isa isa);
xtensa_isa_num_pipe_stages (xtensa_isa isa);
/* Get the number of various entities that are defined for this processor. */
@ -537,7 +537,7 @@ xtensa_operand_regfile (xtensa_isa isa, xtensa_opcode opc, int opnd);
extern int
xtensa_operand_num_regs (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* Some register operands do not completely identify the register being
accessed. For example, the operand value may be added to an internal
@ -554,7 +554,7 @@ xtensa_operand_is_known_reg (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* Check if an immediate operand is PC-relative. Returns 0 for register
operands and non-PC-relative immediates, 1 for PC-relative
immediates, and XTENSA_UNDEFINED on error. */
extern int
xtensa_operand_is_PCrelative (xtensa_isa isa, xtensa_opcode opc, int opnd);

14
libr/asm/arch/lanai/gnu/lanai-dis.c
View File

@ -34,7 +34,7 @@
* Arcadia, CA 91024 *
*************************************************************************/
/* initial version released 5/95 */
/* This file is based upon <> from the Gnu binutils-2.5.2
/* This file is based upon <> from the Gnu binutils-2.5.2
release, which had the following copyright notice: */
/* Print SPARC instructions.
@ -69,7 +69,7 @@ static char *reg_names[] =
"r24","r25","r26","r27","r28","r29","r30","r31",
};
static char *op_names[] =
static char *op_names[] =
{ "add", "addc", "sub", "subb", "and", "or", "xor", "sh" };
/* Nonzero if INSN is the opcode for a delayed branch. */
@ -147,7 +147,7 @@ print_insn_lanai (memaddr, info)
the effect of adding or or'ing the imm13 field to rs1. */
int imm_added_to_rs1 = 0;
/* Do we have an `add' or `or' immediate instruction where rs1 is
/* Do we have an `add' or `or' immediate instruction where rs1 is
the same as rd? */
if (((!(opcode->match & 0x80000000) /* RI insn */
@ -356,13 +356,13 @@ print_insn_lanai (memaddr, info)
&& X_RD (prev_insn) )
{
(*info->fprintf_func) (stream, "\t! ");
info->target
info->target
= X_C16( insn) << (L3_RI_H& insn ? 16 : 0);
if((prev_insn & 0xf07c0000) == 0x50000000 ){
info->target
info->target
|= X_C16(prev_insn) << (L3_RI_H&prev_insn ? 16 : 0);
}else{
info->target
info->target
+= X_C16(prev_insn) << (L3_RI_H&prev_insn ? 16 : 0);
}
(*info->print_address_func) (info->target, info);
@ -479,7 +479,7 @@ compare_opcodes (a, b)
op0->name, op1->name);
}
}
/* Fewer arguments are preferred. */
{
int length_diff = strlen (op0->args) - strlen (op1->args);

26
libr/asm/arch/lanai/gnu/lanai-opc.c
View File

@ -34,7 +34,7 @@
* Arcadia, CA 91024 *
*************************************************************************/
/* initial version released 5/95 */
/* This file is based upon <> from the Gnu binutils-2.5.2
/* This file is based upon <> from the Gnu binutils-2.5.2
release, which had the following copyright notice: */
/* Table of opcodes for the sparc.
@ -54,7 +54,7 @@
You should have received a copy of the GNU General Public License
along with this software; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
USA. */
/* FIXME-someday: perhaps the ,a's and such should be embedded in the
@ -76,7 +76,7 @@ const char *architecture_pname[] = {
/* A pair is the set of all bits that must be high or low as determined
solely by the opcode. This macro takes a mask and the set of
all bits that must be high and generates the pair. I do this
all bits that must be high and generates the pair. I do this
so the macro definitions below are simpler. */
#define GENERIC_PAIR(mask,high) \
@ -353,7 +353,7 @@ struct lanai_opcode lanai_opcodes[] = {
{ "ld", RM_PAIR(0,1,0) ,"o[1],d", F_RM,0},
{ "ld", RM_PAIR(0,1,1) ,"o[*1],d", F_RM,0},
{ "ld", RM_PAIR(0,0,1) ,"o[1*],d", F_RM,0},
{ "uld", 0x80030004,0x7000fffb ,"[++1],d", F_ALIAS,0},
{ "uld", 0x80010004,0x7002fffb ,"[1++],d", F_ALIAS,0},
{ "uld", 0x8003fffc,0x70000003 ,"[--1],d", F_ALIAS,0},
@ -370,7 +370,7 @@ struct lanai_opcode lanai_opcodes[] = {
{ "uld", RM_PAIR(0,1,0) ,"o[1],d", F_ALIAS,0},
{ "uld", RM_PAIR(0,1,1) ,"o[*1],d", F_ALIAS,0},
{ "uld", RM_PAIR(0,0,1) ,"o[1*],d", F_ALIAS,0},
{ "ld.h", 0xf0030c02,0x0000f3fd ,"[++1],d", F_HALF|F_SPLS,0},
{ "ld.h", 0xf0030402,0x0000fbfd ,"[1++],d", F_HALF|F_SPLS,0},
{ "ld.h", 0xf0030ffe,0x0000f001 ,"[--1],d", F_HALF|F_SPLS,0},
@ -386,7 +386,7 @@ struct lanai_opcode lanai_opcodes[] = {
{ "ld.h", SPLS_PAIR(0,L3_SIGNED_HALFWORD,1,0) ,"i[1],d", F_HALF|F_SPLS,0},
{ "ld.h", SPLS_PAIR(0,L3_SIGNED_HALFWORD,1,1) ,"i[*1],d", F_HALF|F_SPLS,0},
{ "ld.h", SPLS_PAIR(0,L3_SIGNED_HALFWORD,0,1) ,"i[1*],d", F_HALF|F_SPLS,0},
{ "uld.h", 0xf0031c02,0x0000e3fd ,"[++1],d", F_HALF|F_SPLS,0},
{ "uld.h", 0xf0031402,0x0000ebfd ,"[1++],d", F_HALF|F_SPLS,0},
{ "uld.h", 0xf0031ffe,0x0000e001 ,"[--1],d", F_HALF|F_SPLS,0},
@ -402,7 +402,7 @@ struct lanai_opcode lanai_opcodes[] = {
{ "uld.h",SPLS_PAIR(0,L3_UNSIGNED_HALFWORD,1,0),"i[1],d", F_HALF|F_SPLS,0},
{ "uld.h",SPLS_PAIR(0,L3_UNSIGNED_HALFWORD,1,1),"i[*1],d", F_HALF|F_SPLS,0},
{ "uld.h",SPLS_PAIR(0,L3_UNSIGNED_HALFWORD,0,1),"i[1*],d", F_HALF|F_SPLS,0},
{ "ld.b", 0xf0034c01,0x0000b3fe ,"[++1],d", F_BYTE|F_SPLS,0},
{ "ld.b", 0xf0034401,0x0000bbfe ,"[1++],d", F_BYTE|F_SPLS,0},
{ "ld.b", 0xf0034fff,0x0000b000 ,"[--1],d", F_BYTE|F_SPLS,0},
@ -418,7 +418,7 @@ struct lanai_opcode lanai_opcodes[] = {
{ "ld.b", SPLS_PAIR(0,L3_SIGNED_BYTE,1,0) ,"i[1],d", F_BYTE|F_SPLS,0},
{ "ld.b", SPLS_PAIR(0,L3_SIGNED_BYTE,1,1) ,"i[*1],d", F_BYTE|F_SPLS,0},
{ "ld.b", SPLS_PAIR(0,L3_SIGNED_BYTE,0,1) ,"i[1*],d", F_BYTE|F_SPLS,0},
{ "uld.b", 0xf0035c01,0x0000a3fe ,"[++1],d", F_BYTE|F_SPLS,0},
{ "uld.b", 0xf0035401,0x0000abfe ,"[1++],d", F_BYTE|F_SPLS,0},
{ "uld.b", 0xf0035fff,0x0000a000 ,"[--1],d", F_BYTE|F_SPLS,0},
@ -439,7 +439,7 @@ struct lanai_opcode lanai_opcodes[] = {
{ "leadz", LEADZ_PAIR(0) ,"1,d", F_LEADZ,0},
{ "leadz.f", LEADZ_PAIR(1) ,"1,d", F_LEADZ,0},
/* or */
{ "or", RR_PAIR(0,L3_OR) ,"1,2,d", F_RR,0},
@ -449,8 +449,8 @@ struct lanai_opcode lanai_opcodes[] = {
{ "or.f", RI_PAIR(L3_OR,1,0) ,"1,j,d", F_RI,0},
{ "or.f", RI_PAIR(L3_OR,1,1) ,"1,J,d", F_RI,0},
/* popc */
/* popc */
{ "popc", POPC_PAIR(0) ,"1,d", F_POPC,0},
{ "popc.f", POPC_PAIR(1) ,"1,d", F_POPC,0},
@ -491,7 +491,7 @@ struct lanai_opcode lanai_opcodes[] = {
{ "st", RM_PAIR(1,1,0) ,"d,o[1]", F_RM,0},
{ "st", RM_PAIR(1,1,1) ,"d,o[*1]", F_RM,0},
{ "st", RM_PAIR(1,0,1) ,"d,o[1*]", F_RM,0},
{ "st.h", 0xf0032c02,0x0000d3fd ,"d,[++1]", F_HALF|F_SPLS,0},
{ "st.h", 0xf0032402,0x0000dbfd ,"d,[1++]", F_HALF|F_SPLS,0},
{ "st.h", 0xf0032ffe,0x0000d001 ,"d,[--1]", F_HALF|F_SPLS,0},
@ -507,7 +507,7 @@ struct lanai_opcode lanai_opcodes[] = {
{ "st.h", SPLS_PAIR(1,L3_SIGNED_HALFWORD,1,0) ,"d,i[1]", F_HALF|F_SPLS,0},
{ "st.h", SPLS_PAIR(1,L3_SIGNED_HALFWORD,1,1) ,"d,i[*1]", F_HALF|F_SPLS,0},
{ "st.h", SPLS_PAIR(1,L3_SIGNED_HALFWORD,0,1) ,"d,i[1*]", F_HALF|F_SPLS,0},
{ "st.b", 0xf0036c01,0x000093fe ,"d,[++1]", F_BYTE|F_SPLS,0},
{ "st.b", 0xf0036401,0x00009bfe ,"d,[1++]", F_BYTE|F_SPLS,0},
{ "st.b", 0xf0036fff,0x00009000 ,"d,[--1]", F_BYTE|F_SPLS,0},

2
libr/asm/arch/mips/gnu/micromips-opc.c
View File

@ -1,5 +1,5 @@
/*
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
of binutils-gdb.
*/
/* micromips-opc.c. microMIPS opcode table.

4
libr/asm/arch/mips/gnu/mips-dis.c
View File

@ -1,5 +1,5 @@
/*
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
of binutils-gdb.
*/
/* Default disassembler options are modified to match radare2 config. */
@ -983,7 +983,7 @@ parse_mips_ase_option (const char *option)
mips_ase |= ASE_LOONGSON_CAM;
return TRUE;
}
/* Put here for match ext2 frist */
if (CONST_STRNEQ (option, "loongson-ext2"))
{

4
libr/asm/arch/mips/gnu/mips-formats.h
View File

@ -1,6 +1,6 @@
/* Modified version of mips-formats.h. Some assetions are removed. */
/* Modified version of mips-formats.h. Some assetions are removed. */
/*
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
of binutils-gdb.
*/
/* mips-formats.h

2
libr/asm/arch/mips/gnu/mips-opc.c
View File

@ -1,5 +1,5 @@
/*
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
of binutils-gdb.
*/
/* mips-opc.c -- MIPS opcode list.

2
libr/asm/arch/mips/gnu/mips16-opc.c
View File

@ -1,5 +1,5 @@
/*
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
Based on commits 250d07de5cf6efc81ed934c25292beb63c7e3129 from master branch
of binutils-gdb.
*/
/* mips16-opc.c. Mips16 opcode table.

4
libr/asm/arch/msp430/msp430_disas.c
View File

@ -167,7 +167,7 @@ static int decode_emulation(ut16 instr, struct msp430_cmd *cmd)
} else if (opcode == MSP430_ADD && as == 2 && src == MSP430_R3) {
snprintf(cmd->instr, sizeof (cmd->instr), "%s", bw ? "incd.b" : "incd");
remove_first_operand(cmd);
} else if (opcode == MSP430_XOR && as == 3 && src == MSP430_R3) {
} else if (opcode == MSP430_XOR && as == 3 && src == MSP430_R3) {
snprintf(cmd->instr, sizeof (cmd->instr), "%s", bw ? "inv.b" : "inv");
remove_first_operand(cmd);
} else if (opcode == MSP430_ADD && src == dst) {
@ -279,7 +279,7 @@ static int decode_addressing_mode(ut16 instr, ut16 op1, ut16 op2, struct msp430_
/* addressing mode of destination operand */
switch (ad) {
case 0: /* register mode */
snprintf(dstbuf, sizeof (dstbuf), ", %s", msp430_register_names[dst]);
snprintf(dstbuf, sizeof (dstbuf), ", %s", msp430_register_names[dst]);
break;
case 1:
/* check addr. mode of source operand */

4
libr/asm/arch/nios/gnu/nios2-dis.c
View File

@ -160,7 +160,7 @@ static struct nios2_reg *
nios2_coprocessor_regs (void)
{
static struct nios2_reg *cached = NULL;
if (!cached)
{
int i;
@ -180,7 +180,7 @@ static struct nios2_reg *
nios2_control_regs (void)
{
static struct nios2_reg *cached = NULL;
if (!cached)
{
int i;

16
libr/asm/arch/ppc/gnu/ppc-opc.c
View File

@ -590,12 +590,12 @@ const struct powerpc_operand powerpc_operands[] =
#define FCRT_MASK (0x1f << 21)
{ 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
/* Xilinx FSL related masks and macros */
/* Xilinx FSL related masks and macros */
#define FSL (FCRT + 1)
#define FSL_MASK (0x1f << 11)
{ 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
{ 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
/* Xilinx UDI related masks and macros */
/* Xilinx UDI related masks and macros */
#define URT (FSL + 1)
{ 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
@ -2349,7 +2349,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}},
@ -2381,7 +2381,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
@ -2395,7 +2395,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"evdivws", VX (4,1222), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}},
{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}},
@ -4898,8 +4898,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dctfix", XRC(59,290,0), X_MASK, POWER6, {FRT, FRB}},
{"dctfix.", XRC(59,290,1), X_MASK, POWER6, {FRT, FRB}},
{"ddedpd", XRC(59,322,0), X_MASK, POWER6, {SP, FRT, FRB}},
{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, {SP, FRT, FRB}},
{"ddedpd", XRC(59,322,0), X_MASK, POWER6, {SP, FRT, FRB}},
{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, {SP, FRT, FRB}},
{"dxex", XRC(59,354,0), X_MASK, POWER6, {FRT, FRB}},
{"dxex.", XRC(59,354,1), X_MASK, POWER6, {FRT, FRB}},

2
libr/asm/arch/ppc/libps/libps.c
View File

@ -31,7 +31,7 @@ ps_opcode_t ps_opcodes_array[] = {
{ psq_st, "psq_st", OP (60), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store"},
{ psq_stu, "psq_stu", OP (61), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store with update"},
{ ps_div, "ps_div", OPSC (4, 18, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide"},
{ ps_div, "ps_div", OPSC (4, 18, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide"},
{ ps_div_dot, "ps_div.", OPSC (4, 18, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide"},
{ ps_sub, "ps_sub", OPSC (4, 20, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract"},
{ ps_sub_dot, "ps_sub.", OPSC (4, 20, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract"},

4
libr/asm/arch/ppc/libvle/vle.c
View File

@ -250,7 +250,7 @@ const e_vle_t e_ops[] = {
{ "e_and2is." , 0x7000E800, 0x7000E800 | E_MASK_I16L, E_I16LS , R_ANAL_OP_TYPE_AND, R_ANAL_COND_AL, {TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "e_andi" , 0x1800C000, 0x1800C000 | E_MASK_SCI8, E_SCI8I , R_ANAL_OP_TYPE_AND, R_ANAL_COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
{ "e_andi." , 0x1800C800, 0x1800C800 | E_MASK_SCI8, E_SCI8I , R_ANAL_OP_TYPE_AND, R_ANAL_COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
// has cr0-cr3
// has cr0-cr3
{ "e_beq" , 0x7A000000, 0x7A120000 | E_MASK_BD15, E_BD15 , R_ANAL_OP_TYPE_CJMP, R_ANAL_COND_EQ, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "e_bge" , 0x7A000000, 0x7A000000 | E_MASK_BD15, E_BD15 , R_ANAL_OP_TYPE_CJMP, R_ANAL_COND_GE, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "e_bgt" , 0x7A000000, 0x7A110000 | E_MASK_BD15, E_BD15 , R_ANAL_OP_TYPE_CJMP, R_ANAL_COND_GT, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
@ -269,7 +269,7 @@ const e_vle_t e_ops[] = {
{ "e_beql" , 0x7A000001, 0x7A130001 | E_MASK_BD15, E_BD15 , R_ANAL_OP_TYPE_CCALL, R_ANAL_COND_VC, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "e_bsol" , 0x7A000001, 0x7A140001 | E_MASK_BD15, E_BD15 , R_ANAL_OP_TYPE_CCALL, R_ANAL_COND_VS, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "e_bcl" , 0x7A000001, 0x7A140001 | E_MASK_BD15, E_BD15 , R_ANAL_OP_TYPE_CCALL, R_ANAL_COND_VS, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
// has cr0-cr3
// has cr0-cr3
{ "e_bdnz" , 0x7A200000, 0x7A200000 | E_MASK_BD15, E_BD15c , R_ANAL_OP_TYPE_JMP, R_ANAL_COND_AL, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "e_bdnzl" , 0x7A200001, 0x7A200001 | E_MASK_BD15, E_BD15c , R_ANAL_OP_TYPE_CALL, R_ANAL_COND_AL, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "e_bdz" , 0x7A300000, 0x7A300000 | E_MASK_BD15, E_BD15c , R_ANAL_OP_TYPE_JMP, R_ANAL_COND_AL, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

2
libr/asm/arch/propeller/propeller_disas.c
View File

@ -186,7 +186,7 @@ static int decode_jmp (struct propeller_cmd *cmd, ut32 instr) {
"#0x%x", get_src (instr) << 2);
} else {
cmd->immed = 0;
cmd->src = get_src (instr) << 2;
cmd->src = get_src (instr) << 2;
snprintf (cmd->operands, PROP_INSTR_MAXLEN - 1,
"0x%x", get_src (instr) << 2);
}

2
libr/asm/arch/riscv/riscv.c
View File

@ -278,7 +278,7 @@ static struct riscv_opcode *get_opcode (insn_t word) {
if (!riscv_hash[OP_HASH_IDX (op->match)]) {
riscv_hash[OP_HASH_IDX (op->match)] = op;
}
}
}
init = 1;
}

2
libr/asm/arch/sh/gnu/sh-opc.h
View File

@ -568,7 +568,7 @@ sh_opcode_info sh_table[] = {
/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}},
{ 0 }
{ 0 }
};
#endif

2
libr/asm/arch/sparc/gnu/sparc-dis.c
View File

@ -109,7 +109,7 @@ static const char *v9_priv_reg_names[] =
static const char *v9_hpriv_reg_names[] =
{
"hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
"resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
"resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
"resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
"resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
"resv28", "resv29", "resv30", "hstick_cmpr"

210
libr/asm/arch/tms320/c55x_plus/hashtable.c
View File

@ -314,7 +314,7 @@ st32 get_hashfunc_03(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_04(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x80000000 ) {
if ((arg2 & 0x80000000) == 0x80000000) {
@ -329,7 +329,7 @@ st32 get_hashfunc_04(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_05(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x80000000 ) {
if ((arg2 & 0x80000000) == 0x80000000) {
@ -344,7 +344,7 @@ st32 get_hashfunc_05(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_06(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x80000000 ) {
if ((st32) (arg2 & 0x80000000) == 0x80000000) {
@ -374,7 +374,7 @@ st32 get_hashfunc_07(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_08(st32 arg1, st32 arg2) {
st32 tmp;
st32 tmp;
tmp = arg2 & 0xC0000000;
if ( (arg2 & 0xC0000000u) <= 0x80000000 ) {
@ -396,7 +396,7 @@ st32 get_hashfunc_08(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_09(st32 arg1, st32 arg2) {
st32 v2;
st32 v2;
v2 = arg2 & 0xC0000000;
if ( (arg2 & 0xC0000000u) <= 0x80000000 ) {
@ -418,8 +418,8 @@ st32 get_hashfunc_09(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_10(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 v2;
st32 v3;
v2 = arg2;
v3 = v2 & 0x500000;
@ -442,7 +442,7 @@ st32 get_hashfunc_10(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_11(st32 arg1, st32 arg2) {
st32 result;
st32 result;
/* */
@ -459,9 +459,9 @@ st32 get_hashfunc_11(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_12(st32 arg1, st32 arg2) {
st32 tmp;
st32 v3;
st32 result;
st32 tmp;
st32 v3;
st32 result;
tmp = arg2;
v3 = tmp & 0x400000;
@ -478,7 +478,7 @@ st32 get_hashfunc_12(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_13(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -493,7 +493,7 @@ st32 get_hashfunc_13(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_14(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if (arg2 & 0x1000000) {
if ((arg2 & 0x1000000) == 0x1000000) {
@ -508,7 +508,7 @@ st32 get_hashfunc_14(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_15(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -523,7 +523,7 @@ st32 get_hashfunc_15(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_16(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -538,7 +538,7 @@ st32 get_hashfunc_16(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_17(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -553,7 +553,7 @@ st32 get_hashfunc_17(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_18(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -568,7 +568,7 @@ st32 get_hashfunc_18(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_19(st32 arg1, st32 arg2) {
st32 v2;
st32 v2;
v2 = arg2 & 0xC1000000;
if ( (arg2 & 0xC1000000u) > 0x40000000 ) {
@ -587,7 +587,7 @@ st32 get_hashfunc_19(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_20(st32 arg1, st32 arg2) {
st32 v2;
st32 v2;
v2 = arg2 & 0x1400000;
if ( (arg2 & 0x1400000u) <= 0x1000000 ) {
@ -609,7 +609,7 @@ st32 get_hashfunc_20(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_21(st32 arg1, st32 arg2) {
st32 v2;
st32 v2;
v2 = arg2 & 0x1400000;
if ( (arg2 & 0x1400000u) <= 0x1000000 ) {
@ -631,7 +631,7 @@ st32 get_hashfunc_21(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_22(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x8200 ) {
if ((unsigned short)(arg2 & 0x8200) == 512) {
@ -646,8 +646,8 @@ st32 get_hashfunc_22(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_23(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 v2;
st32 v3;
v2 = arg2;
v3 = v2 & 0x41C000;
@ -707,8 +707,8 @@ st32 get_hashfunc_23(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_24(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 v2;
st32 v3;
v2 = arg2;
v3 = v2 & 0x418000;
@ -747,7 +747,7 @@ st32 get_hashfunc_24(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_25(st32 arg1, st32 arg2) {
ut32 v2;
ut32 v2;
v2 = (ut32)hash_const_02 & arg2;
if ( ((ut32)hash_const_02 & arg2) <= 0x8000 ) {
@ -782,8 +782,8 @@ st32 get_hashfunc_25(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_26(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 v2;
st32 v3;
v2 = arg2;
v3 = v2 & 0x41C000;
@ -810,9 +810,9 @@ st32 get_hashfunc_26(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_27(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 result;
st32 v2;
st32 v3;
st32 result;
v2 = arg2;
v3 = v2 & 0x18000;
@ -834,9 +834,9 @@ st32 get_hashfunc_27(st32 arg1, st32 arg2) {
st32 get_hashfunc_28(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
char v5;
st32 v2;
st32 v3;
char v5;
v2 = arg2;
v3 = v2 & 0x1F800;
@ -924,8 +924,8 @@ st32 get_hashfunc_28(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_29(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 v2;
st32 v3;
v2 = arg2;
v3 = v2 & 0x40F800;
@ -949,9 +949,9 @@ st32 get_hashfunc_29(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_30(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 result;
st32 v2;
st32 v3;
st32 result;
v2 = arg2;
v3 = v2 & 0x18000;
@ -972,7 +972,7 @@ st32 get_hashfunc_30(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_31(st32 arg1, st32 arg2) {
st32 result;
st32 result;
st32 v3 = arg2 & 0x380000;
if ( (ut32)v3 <= 0x200000 ) {
@ -1012,9 +1012,9 @@ st32 get_hashfunc_31(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_32(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 result;
st32 v2;
st32 v3;
st32 result;
v2 = arg2;
v3 = v2 & 0x18000;
@ -1036,7 +1036,7 @@ st32 get_hashfunc_32(st32 arg1, st32 arg2) {
st32 get_hashfunc_33(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x8000 ) {
if ((unsigned short)(arg2 & 0x8000) == 32768) {
@ -1051,7 +1051,7 @@ st32 get_hashfunc_33(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_34(st32 arg1, st32 arg2) {
st32 result;
st32 result;
st32 v2 = arg2;
st32 v3 = v2 & 0x580000;
if ( (ut32)v3 <= 0x180000 ) {
@ -1082,7 +1082,7 @@ st32 get_hashfunc_34(st32 arg1, st32 arg2) {
st32 get_hashfunc_35(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1097,7 +1097,7 @@ st32 get_hashfunc_35(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_36(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1C00000 ) {
if ((arg2 & 0x1C00000) == 16777216) {
@ -1112,7 +1112,7 @@ st32 get_hashfunc_36(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_37(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( (arg2 & 0x1800000) == 8388608 ) {
result = 473;
@ -1147,7 +1147,7 @@ st32 get_hashfunc_38(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_39(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( (arg2 & 0x1010000) == 65536 ) {
result = 25;
@ -1162,7 +1162,7 @@ st32 get_hashfunc_39(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_40(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1010000 ) {
if ((arg2 & 0x1010000) == 16777216) {
@ -1177,7 +1177,7 @@ st32 get_hashfunc_40(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_41(st32 arg1, st32 arg2) {
st32 result;
st32 result;
st32 v2 = arg2 & 0x1010000;
if ( arg2 & 0x1010000 ) {
if ( v2 == 16777216 ) {
@ -1216,7 +1216,7 @@ st32 get_hashfunc_42(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_43(st32 arg1, st32 arg2) {
st32 v2;
st32 v2;
v2 = arg2 & 0x1010000;
if ( (arg2 & 0x1010000u) <= 0x1000000 ) {
@ -1238,7 +1238,7 @@ st32 get_hashfunc_43(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_44(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1253,7 +1253,7 @@ st32 get_hashfunc_44(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_45(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1268,7 +1268,7 @@ st32 get_hashfunc_45(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_46(st32 arg1, st32 arg2) {
st32 v2;
st32 v2;
v2 = arg2 & 0xC1000000;
if ( (arg2 & 0xC1000000u) > 0x40000000 ) {
@ -1287,7 +1287,7 @@ st32 get_hashfunc_46(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_47(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1302,7 +1302,7 @@ st32 get_hashfunc_47(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_48(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1317,7 +1317,7 @@ st32 get_hashfunc_48(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_49(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if (arg2 & 0x80000000) {
if ((arg2 & 0x80000000) == 0x80000000) {
@ -1417,7 +1417,7 @@ st32 get_hashfunc_52(st32 arg1, st32 arg2) {
st32 get_hashfunc_53(st32 arg1, st32 arg2) {
st32 v2 = arg2 & 0x8200;
st32 result;
st32 result;
if (arg2 & 0x8200) {
if (v2 == 512) {
@ -1466,7 +1466,7 @@ st32 get_hashfunc_55(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_56(st32 arg1, st32 arg2) {
st32 result;
st32 result;
st32 v3 = arg2 & 0x18180;
if ( (ut32)v3 <= 0x8080 ) {
if (v3 == 32896) {
@ -1495,7 +1495,7 @@ st32 get_hashfunc_56(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_57(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x8000 ) {
if ((unsigned short)(arg2 & 0x8000) == 32768) {
@ -1510,9 +1510,9 @@ st32 get_hashfunc_57(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_58(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 result;
st32 v2;
st32 v3;
st32 result;
v2 = arg2;
v3 = v2 & 0x18000;
@ -1533,7 +1533,7 @@ st32 get_hashfunc_58(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_59(st32 arg1, st32 arg2) {
st32 result;
st32 result;
st32 v2 = arg2 & 0x8180;
if ( (ut32)v2 <= 0x100 ) {
if (v2 == 256) {
@ -1559,7 +1559,7 @@ st32 get_hashfunc_59(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_60(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1574,7 +1574,7 @@ st32 get_hashfunc_60(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_61(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1589,7 +1589,7 @@ st32 get_hashfunc_61(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_62(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1604,7 +1604,7 @@ st32 get_hashfunc_62(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_63(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1619,7 +1619,7 @@ st32 get_hashfunc_63(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_64(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1634,7 +1634,7 @@ st32 get_hashfunc_64(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_65(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1649,7 +1649,7 @@ st32 get_hashfunc_65(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_66(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( (arg2 & 0x1C00000) == 12582912 ) {
result = 157;
@ -1665,7 +1665,7 @@ st32 get_hashfunc_66(st32 arg1, st32 arg2) {
st32 get_hashfunc_67(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1680,7 +1680,7 @@ st32 get_hashfunc_67(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_68(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1695,7 +1695,7 @@ st32 get_hashfunc_68(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_69(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1710,8 +1710,8 @@ st32 get_hashfunc_69(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_70(st32 arg1, st32 arg2) {
st32 v2;
st32 result;
st32 v2;
st32 result;
v2 = arg2 & 0x1400000;
if ( arg2 & 0x1400000 ) {
@ -1731,7 +1731,7 @@ st32 get_hashfunc_70(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_71(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1400000 ) {
if ((arg2 & 0x1400000) == 4194304) {
@ -1746,7 +1746,7 @@ st32 get_hashfunc_71(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_72(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1761,7 +1761,7 @@ st32 get_hashfunc_72(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_73(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1010000 ) {
if ((arg2 & 0x1010000) == 16777216) {
@ -1776,7 +1776,7 @@ st32 get_hashfunc_73(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_74(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( (arg2 & 0x1010000) == 65536 ) {
result = 213;
@ -1791,7 +1791,7 @@ st32 get_hashfunc_74(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_75(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x80000000 ) {
if ((arg2 & 0x80000000) == 0x80000000) {
@ -1806,7 +1806,7 @@ st32 get_hashfunc_75(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_76(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1821,7 +1821,7 @@ st32 get_hashfunc_76(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_77(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -1857,9 +1857,9 @@ st32 get_hashfunc_78(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_79(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 result;
st32 v2;
st32 v3;
st32 result;
v2 = arg2;
v3 = v2 & 0x18180;
@ -1917,9 +1917,9 @@ st32 get_hashfunc_79(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_80(st32 arg1, st32 arg2) {
st32 v2;
st32 v3;
st32 result;
st32 v2;
st32 v3;
st32 result;
v2 = arg2;
v3 = v2 & 0x18180;
@ -1977,7 +1977,7 @@ st32 get_hashfunc_80(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_81(st32 arg1, st32 arg2) {
st32 result;
st32 result;
st32 v2 = arg2 & 0x1000180;
if ( (arg2 & 0x1000180u) <= 0x1000000 ) {
if ((arg2 & 0x1000180) == 16777216) {
@ -2016,8 +2016,8 @@ st32 get_hashfunc_81(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_82(st32 arg1, st32 arg2) {
st32 v2;
st32 result;
st32 v2;
st32 result;
v2 = arg2 & 0x1000180;
if ( (arg2 & 0x1000180u) <= 0x100 ) {
@ -2044,9 +2044,9 @@ st32 get_hashfunc_82(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_83(st32 arg1, st32 arg2) {
st32 v2;
st32 result;
char v4;
st32 v2;
st32 result;
char v4;
v2 = arg2 & 0x1810180;
if ( (arg2 & 0x1810180u) <= 0x800080 ) {
@ -2127,7 +2127,7 @@ st32 get_hashfunc_83(st32 arg1, st32 arg2) {
st32 get_hashfunc_84(st32 arg1, st32 arg2) {
st32 result;
st32 result;
st32 v2 = arg2 & 0x1000180;
if ( arg2 & 0x1000180 ) {
if ( v2 == 16777344 ) {
@ -2146,7 +2146,7 @@ st32 get_hashfunc_84(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_85(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( (arg2 & 0x1000180) == 128 ) {
result = 511;
@ -2161,7 +2161,7 @@ st32 get_hashfunc_85(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_86(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( arg2 & 0x1000000 ) {
if ((arg2 & 0x1000000) == 16777216) {
@ -2176,7 +2176,7 @@ st32 get_hashfunc_86(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_87(st32 arg1, st32 v2) {
st32 result;
st32 result;
st32 v3 = v2 & 0x79B981;
if (v3 == 33024 || v3 == 4227328) {
result = 490;
@ -2205,7 +2205,7 @@ st32 get_hashfunc_88(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_89(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( (arg2 & 0x1B901B9) == 16777600 ) {
result = 488;
@ -2220,9 +2220,9 @@ st32 get_hashfunc_89(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_90(st32 arg1, st32 arg2) {
st32 v2;
st32 v4;
st32 v5;
st32 v2;
st32 v4;
st32 v5;
v2 = arg2 & 0x1F901B9;
if ( (arg2 & 0x1F901B9u) <= 0x1810101 ) {
@ -2267,7 +2267,7 @@ st32 get_hashfunc_90(st32 arg1, st32 arg2) {
}
st32 get_hashfunc_91(st32 arg1, st32 arg2) {
st32 result;
st32 result;
if ( (arg2 & 0x1F901BF) == 8454145 ) {
result = 501;

2
libr/asm/arch/tms320/c55x_plus/ins.c
View File

@ -57,7 +57,7 @@ ut32 get_ins_part(ut32 pos, ut32 len) {
if ((st32)pos < 0 || pos >= ins_buff_len) {
has_failed = 1;
return ret;
}
}
for (; len > 0; len--) {
ret <<= 8;

6
libr/asm/arch/tricore/gnu/cpu-tricore.c
View File

@ -72,7 +72,7 @@ unsigned long tricore_mask_ssr;
unsigned long tricore_mask_ssro;
unsigned long tricore_opmask[TRICORE_FMT_MAX];
int
int
bfd_default_scan (info, string)
const bfd_arch_info_type *info;
const char *string;
@ -247,7 +247,7 @@ tricore_init_arch_vars (mach)
tricore_mask_rcrw = 0x00e000ff;
tricore_mask_rlc = 0x000000ff;
tricore_mask_rr = 0x0ff300ff;
tricore_mask_rr1 = 0x0ffc00ff;
tricore_mask_rr1 = 0x0ffc00ff;
tricore_mask_rr2 = 0x0fff00ff;
tricore_mask_rrpw = 0x006000ff;
tricore_mask_rrr = 0x00f300ff;
@ -295,7 +295,7 @@ tricore_init_arch_vars (mach)
tricore_opmask[TRICORE_FMT_RCRW] = tricore_mask_rcrw;
tricore_opmask[TRICORE_FMT_RLC] = tricore_mask_rlc;
tricore_opmask[TRICORE_FMT_RR] = tricore_mask_rr;
tricore_opmask[TRICORE_FMT_RR1] = tricore_mask_rr1;
tricore_opmask[TRICORE_FMT_RR1] = tricore_mask_rr1;
tricore_opmask[TRICORE_FMT_RR2] = tricore_mask_rr2;
tricore_opmask[TRICORE_FMT_RRPW] = tricore_mask_rrpw;
tricore_opmask[TRICORE_FMT_RRR] = tricore_mask_rrr;

10
libr/asm/arch/tricore/gnu/tricore-dis.c
View File

@ -1434,7 +1434,7 @@ print_decoded_insn (memaddr, info)
abs = (dec_insn.cexp[i] << 1) + memaddr;
(*info->print_address_func) (abs, info);
break;
case 'c':
needs_creg = 1;
/* Fall through. */
@ -1458,7 +1458,7 @@ print_decoded_insn (memaddr, info)
case '&':
dec_insn.regs[i] = 10;
/* Fall through. */
/* Fall through. */
case '@':
if (dec_insn.regs[i] == 10) {
DPRINT (DFILE, "[" REGPREFIX "sp]");
@ -1524,7 +1524,7 @@ print_decoded_insn (memaddr, info)
break;
case 'S':
DPRINT (DFILE, "["REGPREFIX"a15]");
DPRINT (DFILE, "["REGPREFIX"a15]");
need_comma = 0;
break;
}
@ -1577,7 +1577,7 @@ decode_tricore_insn (memaddr, insn, len32, info)
}
/* Oops -- this isn't a valid TriCore insn! Since we know that
MEMADDR is an even address (otherwise it already would have
MEMADDR is an even address (otherwise it already would have
been handled by print_insn_tricore below) and that TriCore
insns can only start at even addresses, we just print the
lower 16 bits of INSN as a .hword pseudo-opcode and return 2,
@ -1880,7 +1880,7 @@ decode_pcp_insn (memaddr, buffer, info)
(or possible) to decode a single instruction or a pseudo-op, i.e.
1, 2 or 4 bytes. */
int
int
print_insn_tricore (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;

4
libr/asm/arch/xtensa/gnu/xtensa-dis.c
View File

@ -100,7 +100,7 @@ print_xtensa_operand (bfd_vma memaddr,
{
xtensa_isa isa = xtensa_default_isa;
int signed_operand_val;
if (show_raw_fields)
{
if (operand_val < 0xa) {
@ -146,7 +146,7 @@ print_xtensa_operand (bfd_vma memaddr,
xtensa_regfile_shortname (isa, opnd_rf),
operand_val);
i++;
}
}
}
}

2
libr/asm/arch/z80/expressions.c
View File

@ -462,7 +462,7 @@ rd_factor (const char **p, int *valid, int level, int *check, int print_errors)
{
(*p)++;
int value = rd_value (p, valid, level, check, print_errors);
if (value == 0){
if (value == 0){
printerr (1, "division by zero\n");
return -1;
}

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