Add xmm registers for the FreeBSD debugger ##debug

libr/debug/p/debug_native.c

@@ -661,13 +661,19 @@ static int bsd_reg_read(RDebug *dbg, int type, ut8* buf, int size) {
 		return true;
 		break;
 	case R_REG_TYPE_FPU:
+	case R_REG_TYPE_VEC64: // MMX
 	   ret = ptrace (PT_GETFPREGS, pid, (caddr_t)buf, sizeof (struct fpreg));
 	   break;
-	case R_REG_TYPE_VEC64: // MMX
 	case R_REG_TYPE_VEC128: // XMM
 	case R_REG_TYPE_VEC256: // YMM
 	case R_REG_TYPE_VEC512: // ZMM
-		// not implemented
+#if __KFBSD__
+		struct ptrace_xstate_info info;
+		ret = ptrace (PT_GETXSTATE_INFO, pid, (caddr_t)&info, sizeof (info));
+		if (info.xsave_len != 0) {
+		ret = ptrace (PT_GETXSTATE, pid, (caddr_t)buf, info.xsave_len);
+		}
+#endif
 		break;
 	case R_REG_TYPE_SEG:
 	case R_REG_TYPE_FLG:

libr/debug/p/native/bsd/bsd_debug.c

@@ -118,8 +118,20 @@ bool bsd_reg_write(RDebug *dbg, int type, const ut8 *buf, int size) {
 #endif
 		break;
 	case R_REG_TYPE_FPU:
+	case R_REG_TYPE_VEC64: // MMX
 		r = ptrace (PT_SETFPREGS, dbg->pid, (caddr_t)buf, sizeof (struct fpreg));
 		break;
+	case R_REG_TYPE_VEC128: // XMM
+	case R_REG_TYPE_VEC256: // YMM
+	case R_REG_TYPE_VEC512: // ZMM
+#if __KFBSD__
+		struct ptrace_xstate_info info;
+		r = ptrace (PT_GETXSTATE_INFO, dbg->pid, (caddr_t)&info, sizeof (info));
+		if (info.xsave_len != 0) {
+			r = ptrace (PT_SETXSTATE, dbg->pid,  (caddr_t)buf, info.xsave_len);
+		}
+#endif
+	      break;
 	}
 	return r == 0;
 }

libr/debug/p/native/reg/kfbsd-x64.h

@@ -112,4 +112,54 @@ return strdup (
 "vec64@fpu	mm5 .64 112	8\n"
 "vec64@fpu	mm6 .64 128 8\n"
 "vec64@fpu	mm7 .64 144 8\n"
+
+"vec128@fpu    xmm0    .128	160 16\n"
+"fpu		xmm0l	         .64	160	8\n"
+"fpu		xmm0h	 .64	168	8\n"
+"vec128@fpu    xmm1    .128	176 16\n"
+"fpu		xmm1l	         .64	176	8\n"
+"fpu		xmm1h	 .64	184	8\n"
+"vec128@fpu    xmm2    .128	192 16\n"
+"fpu		xmm2l	         .64	192	8\n"
+"fpu		xmm2h	 .64	200	8\n"
+"vec128@fpu    xmm3    .128	208 16\n"
+"fpu		xmm3l	         .64	208	8\n"
+"fpu		xmm3h	.64		216	8\n"
+"vec128@fpu    xmm4    .128	224 16\n"
+"fpu		xmm4l	         .64	224	8\n"
+"fpu		xmm4h	 .64	232	8\n"
+"vec128@fpu    xmm5    .128	240 16\n"
+"fpu		xmm5l	         .64	240	8\n"
+"fpu		xmm5h	 .64	248	8\n"
+"vec128@fpu    xmm6    .128	256 16\n"
+"fpu		xmm6l	         .64	256	8\n"
+"fpu		xmm6h	 .64	264	8\n"
+"vec128@fpu    xmm7    .128	272 16\n"
+"fpu		xmm7l	         .64	272	8\n"
+"fpu		xmm7h	 .64	280	8\n"
+"vec128@fpu    xmm8    .128	288 16\n"
+"fpu		xmm8l	         .64	288	8\n"
+"fpu		xmm8h	 .64	296	8\n"
+"vec128@fpu    xmm9    .128	304 16\n"
+"fpu		xmm9l	         .64	304	8\n"
+"fpu		xmm9h	 .64	312	8\n"
+"vec128@fpu    xmm10   .128	320 16\n"
+"fpu		xmm10l	 .64	320	8\n"
+"fpu		xmm10h	 .64	328	8\n"
+"vec128@fpu    xmm11   .128	336 16\n"
+"fpu		xmm11l	 .64	336	8\n"
+"fpu		xmm11h	 .64	344	8\n"
+"vec128@fpu    xmm12   .128	352 16\n"
+"fpu		xmm12l	   .64	352	8\n"
+"fpu		xmm12h	   .64	360	8\n"
+"vec128@fpu    xmm13   .128	368 16\n"
+"fpu		xmm13l	  .64	368	8\n"
+"fpu		xmm13h	  .64	376	8\n"
+"vec128@fpu    xmm14   .128	384 16\n"
+"fpu		xmm14l	   .64	384	8\n"
+"fpu		xmm14h	   .64	392	8\n"
+"vec128@fpu    xmm15   .128	400 16\n"
+"fpu		xmm15l	   .64	400	8\n"
+"fpu		xmm15h	   .64	408	8\n"
+"fpu	x64	.64	416	0\n"
 );