Added registers st0 to st7, mm0 to mm7 while debugging under FreeBSD ##debug

* added registers st0 to st7, mm0 to mm7 while debugging under FreeBSD.

* Apply suggestions from code review

---------

Co-authored-by: User Julien <julien@ryzen3950x.home>
Co-authored-by: pancake <pancake@nowsecure.com>

libr/debug/p/debug_native.c

@@ -661,6 +661,8 @@ static int bsd_reg_read(RDebug *dbg, int type, ut8* buf, int size) {
 		return true;
 		break;
 	case R_REG_TYPE_FPU:
+	   ret = ptrace (PT_GETFPREGS, pid, (caddr_t)buf, sizeof (struct fpreg));
+	   break;
 	case R_REG_TYPE_VEC64: // MMX
 	case R_REG_TYPE_VEC128: // XMM
 	case R_REG_TYPE_VEC256: // YMM

libr/debug/p/native/reg/kfbsd-x64.h

@@ -86,4 +86,30 @@ return strdup (
 "flg	if	.1	.1225	0	interrupt\n"
 "flg	df	.1	.1226	0	direction\n"
 "flg	of	.1	.1227	0	overflow\n"
+"fpu	cwd	.16	0	0\n"
+"fpu	swd	.16	2	0\n"
+"fpu	ftw	.16	4	0\n"
+"fpu	fop	.16	6	0\n"
+"fpu	frip	.64	8	0\n"
+"fpu	frdp	.64	16	0\n"
+"fpu	mxcsr	.32	24	0\n"
+"fpu	mxcr_mask	.32	28	0\n"
+
+"fpu	st0	.80	32	0\n"
+"fpu	st1	.80	48	0\n"
+"fpu	st2	.80	64	0\n"
+"fpu	st3	.80	80	0\n"
+"fpu	st4	.80	96	0\n"
+"fpu	st5	.80	112	0\n"
+"fpu	st6	.80	128	0\n"
+"fpu	st7	.80	144	0\n"
+
+"vec64@fpu	mm0 .64 32	8\n"
+"vec64@fpu	mm1 .64 48	8\n"
+"vec64@fpu	mm2 .64 64	8\n"
+"vec64@fpu	mm3 .64 80	8\n"
+"vec64@fpu	mm4 .64 96	8\n"
+"vec64@fpu	mm5 .64 112	8\n"
+"vec64@fpu	mm6 .64 128 8\n"
+"vec64@fpu	mm7 .64 144 8\n"
 );