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fix the arm64 sdiv and udiv instrs on div by 0

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This commit is contained in:
aemmitt 2022-02-17 22:12:03 -05:00 committed by pancake
parent a7386c4b83
commit f59b7dfb56
3 changed files with 20 additions and 3 deletions
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9
libr/anal/p/anal_arm_cs.c
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@ -1619,11 +1619,16 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
FPOPCALL ("/");
break;
case ARM64_INS_SDIV:
OPCALL_SIGN ("/", REGBITS64 (1));
r_strbuf_setf (&op->esil, "%s,!,?{,0,%s,=,}{,", REG64 (2), REG64 (0));
OPCALL_SIGN ("~/", REGBITS64 (1));
r_strbuf_appendf (&op->esil, ",}");
break;
case ARM64_INS_UDIV:
/* TODO: support WZR XZR to specify 32, 64bit op */
OPCALL ("/");
// arm64 does not have a div-by-zero exception, just quietly sets R0 to 0
r_strbuf_setf (&op->esil, "%s,!,?{,0,%s,=,}{,", REG64 (2), REG64 (0));
OPCALL("/");
r_strbuf_appendf (&op->esil, ",}");
break;
#if CS_API_MAJOR > 4
case ARM64_INS_BRAA:

8
libr/anal/p/anal_arm_v35.c
View File

@ -1580,11 +1580,17 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
FPOPCALL("/");
break;
case ARM64_SDIV:
OPCALL_SIGN("/", REGBITS64 (1));
// arm64 does not have a div-by-zero exception, just quietly sets R0 to 0
r_strbuf_setf (&op->esil, "%s,!,?{,0,%s,=,}{,", REG64 (2), REG64 (0));
OPCALL_SIGN ("~/", REGBITS64 (1));
r_strbuf_appendf (&op->esil, ",}");
break;
case ARM64_UDIV:
/* TODO: support WZR XZR to specify 32, 64bit op */
// arm64 does not have a div-by-zero exception, just quietly sets R0 to 0
r_strbuf_setf (&op->esil, "%s,!,?{,0,%s,=,}{,", REG64 (2), REG64 (0));
OPCALL("/");
r_strbuf_appendf (&op->esil, ",}");
break;
// TODO actually implement some kind of fake PAC or at least clear the bits
// PAC B* instructions will not work without clearing PAC bits

6
libr/anal/p/anal_x86_cs.c
View File

@ -999,9 +999,15 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
case X86_INS_CWDE:
esilprintf (op, "ax,eax,=,15,eax,>>,?{,0xffff0000,eax,|=,}");
break;
case X86_INS_CWD:
esilprintf (op, "0,dx,=,15,ax,>>,?{,0xffff,dx,=,}");
break;
case X86_INS_CDQ:
esilprintf (op, "0,edx,=,31,eax,>>,?{,0xffffffff,edx,=,}");
break;
case X86_INS_CQO:
esilprintf (op, "0,rdx,=,63,rax,>>,?{,-1,rdx,=,}");
break;
case X86_INS_CDQE:
esilprintf (op, "eax,rax,=,31,rax,>>,?{,0xffffffff00000000,rax,|=,}");
break;