16bit displacement must be signed, but were unsigned. I've converted the
branch variants to 8/16/32bit signed casts rather than duplicating the
8bit ISBITSET() special case.
36e42b33fe37e922f132e286508bd88ef9fb137d broke analysis by introducing a
new enum value. The analysis code didn't switch on the enum but rather
used it directly as an integer, so since the new SNES_OP_IMM has 5 as
its integer value the analysis code would think that the op was 5 bytes
in length.
Size for immediate operands depends on the value of the M flag
(for register A) or the X flag (for registers X and Y). A register is
8-bit when its respective flag is set and 16-bit when clear.
These flags can be set or unset independently, so this still isn't quite right
for when one flag is set and the other isn't, but it's an improvement. It's
possible to force a particular instruction to decode correctly by using the
`afh` command.
I just misread the operands of the rcall instruction
their is 2 similar types of instruction (naming conveintions used only
by me and mentioned no where in the manual) the N_T where the n operand
is 8 bit and NET_T where the n operand is 11 bit
the rcall looks like the following 1101 1nnn nnnn nnnn which is obviosly
NEX_T
I also hunted 4th illegal memory read
the first 2 bytes of b is always casted to (ut16) type
with out checking if b even contains 2 bytes
now it is handled it correctly
Before this commit,any illegal opcode would return -1 which
would make r2 use 1 byte as default opcode width.This was
wrong on MSP430 as it uses fixed 2 byte opcodes.Fix this