radare
9e08da0fa6
Improve build of libr.a and libr.dylib, fix and improve sys/ios-sdk.sh ( #10046 )
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- Update spp and force hidden visibility
- Use R_API wisely
- RSys.prefix returns const things
- Use -install_name on Apple
- Fix merged lib visibility linking on Linux
- Use OSTYPE instead of BUILD_OS
- Honor crosscompiler-objcopy and support android like linux
- Add extra missing archives
- Fix for android
- Upgrade spp and sdb
- Skip libr. from symstall
- Add --enable-merged configure option
- Use --enable-merged on ios-sdk
- Upgrade sdb again for js0n
- Kill sys/ios-shell.sh
- Msvc dynamic build fix
2018-05-09 23:31:52 +02:00
pancake
bd276ef2fd
Fix #9969 - Stack overflow in wasm disassembler
2018-05-06 15:26:26 +02:00
RagingCactus
dd4761f792
Fix analyzed opcode size for some z80 instructions ( #9984 )
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This bug affected instructions starting with:
* 0xED (extended instructions)
* 0xDD (instructions operating on IX register)
* 0xFD (instructions operating on IY register)
2018-04-29 22:19:55 +02:00
pancake
227dec4cc7
Fix last covs in armass
2018-04-24 12:07:16 +02:00
radare
62978bbf6e
Full thumb2 assembler support
2018-04-21 11:33:55 +02:00
pancake
1adac87918
Update sdb-1.1.0, update calls to sdb_fmt()
2018-04-10 23:52:47 +02:00
pancake
251fe5b1e7
Fix last covs
2018-03-21 11:51:20 +01:00
vdf-git
2efb14af3a
ARM Thumb/Const argcodes ( #9730 )
2018-03-20 17:06:37 +01:00
vdf-git
eb03a87d1a
New implementation of opcodes a through C
2018-03-20 12:21:54 +01:00
pancake
fe7ae5d0af
Fix last 20 coverity issues
2018-03-19 11:51:04 +01:00
Florian Märkl
94bdf5ce56
Enable xtensa in meson
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Fix r_anal_op() for anal_xtensa if ESIL is disabled
Fix anal_xtensa for Windows
2018-03-16 11:10:15 +01:00
pancake
2682d34291
Fix warnings
2018-03-14 23:54:27 +01:00
vdf-git
42b5bbd882
Arm thumb/thumb selector for the armass ( #9681 )
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* added function to translate number to imm12
* added function to get thumb shifts easily
* added selector, newfangled implementation of adc
* add bitmask for command suffixes
* added new routine for parsing suffixes to opcodes. Error check added in getnum. Bugfixes.
2018-03-14 13:07:03 +01:00
Paul I
69e655fd49
Meson: enable Propeller and Java ( #9639 )
2018-03-09 20:05:47 +08:00
vdf-git
5fa1b0d218
Arm assembler thumb/thumb shift ( #9621 )
2018-03-09 00:32:19 +01:00
vdf-git
b526d7af16
Added function to translate number to imm12 ( #9604 )
2018-03-07 09:39:29 +01:00
vdf-git
e85be034e3
solves issue #9524 ( #9559 )
2018-03-05 09:40:31 +01:00
fergomatic
056d5ab859
tricore: added support for BOL format of st.b ( #9474 )
2018-02-23 09:13:54 +01:00
Anton Kochkov
0341b8455d
Fix MSVC dynamic linking
2018-02-21 13:04:46 +08:00
Giovanni
0c776c0e71
warnings from lib ( #9445 )
2018-02-20 23:19:35 +01:00
Fangrui Song
320a2d5a58
Add FUNC_ATTR_USED and fix some warnings ( #9413 )
2018-02-17 20:19:33 -06:00
StefanBruens
9d92c2d2f0
Consolidate thumb BL and BLX, simplify, bugfix ( #9391 )
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Encoding for BL and BLX with immediate offset is identical, only
difference is the opcode in the second half of the instruction pair.
Use r_num_math instead of getnum, as the latter does not work correctly
for large arguments (>= 0x80000000).
Simplify logic for 16 bit aligned origin addresses. In case the origin
is not 32 bit aligned copy bit[1] to the target address (which is masked
by the decoder) and calculate the offset based on the modified address.
Using the same implementaton also fixes the missing offset handling in BL.
Fix for #9319
2018-02-14 15:08:00 -06:00
Michael Scherer
8c683eab91
Add REV and others to Rasm2, related to bug #7250 ( #9365 )
2018-02-12 16:09:31 +01:00
Giovanni
e46939eb4f
merged fixes from contributor to libvle ( #9380 )
2018-02-12 16:09:19 +01:00
Giuseppe
1e9bce4a8d
Fix #9197 - aarch64 ldur
instruction was missing ( #9372 )
2018-02-11 20:44:52 +01:00
Michael Scherer
b35f936b73
Fix first parameter position for CLZ asm code ( #9364 )
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Fix error in 4b74942
2018-02-10 20:44:08 +01:00
Michael Scherer
4b7494252e
Add CLZ instruction to rasm2 ( #9363 )
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Partially fix #7250
2018-02-10 19:24:34 +01:00
Sven Steinbauer
1b60dbd9e2
Correctly assemble blx
for arm32 and arm16 ( #9352 )
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FIX #9319
Tests added to r2r master
2018-02-09 15:27:39 +01:00
Anton Kochkov
56e5012142
Fix hexagon duplexes recognition
2018-02-06 12:51:53 +08:00
Anton Kochkov
129b1ced20
Fix GCC parentheses warnings
2018-02-06 12:47:38 +08:00
Anton Kochkov
1b73ae0777
Fix Hexagon OOB problem
2018-02-05 18:50:11 +08:00
Anton Kochkov
a3153a4801
Fix Hexagon OOB problem
2018-02-05 18:39:46 +08:00
Anton Kochkov
efcc2bef68
Hexagon QDSP6 v6 support - LGPLv3 ( #9289 )
2018-02-02 13:10:40 +01:00
Sven Steinbauer
d304cef875
Add support for mul ops ( #9281 )
2018-02-01 15:38:25 +01:00
fenugrec
a010d09204
sh: fix disassembly of branch opcodes ( #9238 )
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The displacement field must be sign-extended and multiplied by 2, not
cast to an unsigned type !
2018-01-25 16:25:00 +01:00
Giovanni
9a63f43d01
Fixed illegal access on libps ( #9192 )
2018-01-14 17:55:05 +01:00
wargio
ddb5fd0575
fixed bad load/store for ppc:ps
2018-01-14 10:18:39 +01:00
Giovanni
f32cc2777a
added ppc Paired single ( #9172 )
2018-01-11 14:07:30 +01:00
pancake
c1ef0d7580
Fix dsb, dmb regressions
2018-01-07 13:54:38 +01:00
pancake
1bc0fcdea5
Implement isb, dsb and dmb for the arm64 assembler
2018-01-05 00:45:50 +01:00
pancake
1d7f75fb91
Fix non-null terminated string issue in 8051 disassembler
2018-01-04 18:39:17 +01:00
Florian Märkl
f862b90d4a
Add PIC Baseline ASM Plugin
2018-01-02 18:18:42 +01:00
Anton Kochkov
1b8ab5f7cf
WASM analysis - initial stub ( #9091 )
2017-12-29 19:56:33 +01:00
Adrian Studer
f36f165312
Substitute 8051 register names ( #9072 )
2017-12-28 00:36:41 +01:00
Giovanni
83d6067db9
fixed wrong output ( #8908 )
2017-11-29 04:16:12 +01:00
Fedor Sakharov
881e797e8b
We are moving EVM to radare2-extras
2017-11-21 01:31:05 +01:00
pancake
52b1526443
Fix crash in wasm disassembler
2017-10-11 19:02:25 +02:00
Pepe Vila
5c3cdb44d5
Fixed coverity errors ( #8595 )
2017-09-30 10:50:14 +02:00
pancake
f805d0672a
Fix warnings
2017-09-17 23:27:43 +02:00
pancake
9bc246c5e9
Fix riscv again :(
2017-09-17 23:14:34 +02:00