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1501 Commits

Author SHA1 Message Date
/usr/share
87b78b63eb SNES: (kinda) handle X and M flags (#7095) 2017-03-23 12:53:14 +01:00
alvarofe
ce25037120 Fix #7070 - oob read wrong init buffer asm_sh.c 2017-03-20 23:28:38 +01:00
pancake
e2df61f48e Fixes for m68k -n 16 and sega mega drive roms endian 2017-03-19 11:33:39 +01:00
davidpolverari
1fb422b532 Fix #6162 - Renames r_str_concat to r_str_append 2017-03-16 22:29:49 +01:00
Sven Steinbauer
bd884531f0 Add 16bit jmp x86 (#7023) 
Add 16bit jmp x86
 2017-03-14 16:19:43 +00:00
Sven Steinbauer
5a4c18f49a Add ARM64 barrier ops 2017-03-13 17:53:26 +01:00
Sven Steinbauer
b4d74880c2 Add shift support to ldr instructions (#7014) 2017-03-13 14:27:35 +01:00
Simone Ferrini
a5cc36525f [armass] Added support for sequence registers in pop instruction (#6994) 2017-03-12 19:18:28 +01:00
Álvaro Felipe Melchor
6870bec29f Fix #6853 - get rid of asserts 2017-03-12 15:24:05 +01:00
Lowly Worm
b9302dd4b6 fix typo in WebAssemlby 2017-03-10 23:27:45 -08:00
Sven Steinbauer
73ff7ec410 implement ORR for arm64 FIX #6611 (#6977) 
* implement ORR for arm64 FIX #6611

Implements or with registers and immediate (not yet with rot values for
registers)

* Squash warnings
 2017-03-10 15:38:04 +01:00
Simone Ferrini
781b3fc58e Fix BL for arm thumb (#6968) 2017-03-09 23:47:03 +01:00
pancake
bb4f591d93 Fix capstone3 build regression introduced in 272786852b 2017-03-09 00:02:28 +01:00
Wladimir J. van der Laan
10d1df6dd2 Update RiscV opcodes for disassembly (#6897) 
* riscv: Update opcodes from binutils-gdb

Update to riscv opcodes from
[riscv-binutils-gdb](https://github.com/riscv/riscv-binutils-gdb/commit/08219b2)
git 08219b2.

* riscv: set no_alias=false while disassembling

I'm not sure what the rationale was for setting no_alias to true
originally. But setting it to false means that shorter and (usually)
better readable aliases for instructions will be shown:

Before               |  After
---------------------+------------
`c.jr ra`            | `ret`
`addi a5, zero, 123` | `li a5,123`
`jal zero, 0x101dc`  | `j 0x101dc`

And so on.
 2017-03-04 10:18:45 +01:00
Q
b7db017fa5 Fix multiple definition error in static builds (#6891) 
Rename conflicting global names 'fields' array in AArch64
and 'fields' function in MachoO
 2017-03-03 10:53:41 +01:00
dogtopus
247a8df1e7 Add getimmed8, fix #6841 (#6892) 2017-03-03 08:24:24 +01:00
pancake
8ab0befbd7 Remove assert in GNU's arm64 disassembler 2017-03-03 01:30:56 +01:00
Giovanni
780b834e61 Fix #6882 - tricore byte copy 2017-03-03 00:10:32 +01:00
h4ng3r
f41e941341 Fix #6885 - oob write in dalvik_disassemble 2017-03-02 22:51:57 +01:00
pancake
34089ab363 Fix entrypoint in wasm and add some uleb128-based instructions 2017-03-02 18:45:10 +01:00
Giovanni
aaa46baa48 fixed tricore bug (#6883) 2017-03-02 17:56:43 +01:00
pancake
a41a8252ae Initial import of the WIP support for WebAssembly (bin + disasm) 2017-03-02 14:42:05 +01:00
pancake
d6756e235c Implement author and version of RAsmPlugin 2017-02-28 02:26:55 +01:00
pancake
3b83e18c51 Remove assert for the GNU arm64 disassembler 2017-02-26 23:34:24 +01:00
Wladimir J. van der Laan
aab2bc824c riscv: Choose first match while disassembling 
The opcodes table is sorted with the preferred instructions with a
certain encoding first.
 2017-02-26 23:06:32 +01:00
Wladimir J. van der Laan
78089cd34f riscv: Return actual instruction length 
Support instructions of varying length.
Addresses #6849.
 2017-02-26 23:06:32 +01:00
Maijin
266eee75ae Fix #6560 Unify Windows/Win32 define 2017-02-26 16:51:03 +01:00
alvarofe
f992370474 Fix some memory leaks after ht clean up 2017-02-25 23:50:33 +01:00
alvarofe
0b97b11d38 Fix regression on tms320 2017-02-24 23:42:17 +01:00
alvarofe
8ff55080ea Use ht_* in tms320 2017-02-24 23:42:17 +01:00
Sven Steinbauer
7d71bf5fa2 x86.nz infer bits from register names (#6792) 2017-02-15 11:49:35 +01:00
Sven Steinbauer
65791475ff Refactor msr mrs instructions 2017-02-10 13:11:14 +01:00
Sven Steinbauer
d5c9a65a97 Refactor exceptions 2017-02-10 13:11:14 +01:00
Sven Steinbauer
70a16f14df Refactor branch instructions 2017-02-10 13:11:14 +01:00
Sven Steinbauer
59aac1fdc4 Fix arithmetic op encoding 2017-02-10 13:11:14 +01:00
Sven Steinbauer
3480b9c799 Add lsl and shift to operand 2017-02-10 13:11:14 +01:00
Sven Steinbauer
cb36fd40cb refactor mov instructions 2017-02-10 13:11:14 +01:00
Sven Steinbauer
4ef134e5c4 Add parsing routines 2017-02-10 13:11:14 +01:00
Sven Steinbauer
f6120770eb Add ldrex strex to ARM assembler 2017-02-08 18:29:02 +01:00
Sven Steinbauer
6e9ae1772b Fix #6696 - Prevent infinite loop on visual assembler (#6709) 2017-02-08 12:31:15 +01:00
Sven Steinbauer
8847e121d7 x86.nz fixes enhancements (#6720) 
* Fix group 1 assemble
Fix assembling of group 1 instructions
* add byte [0x452343], 0x34
* add byte [0x435341], al
* Add support for register based offsets
mov [eax + ecx], 0x33

* Fix lea with large values in second operand

* Add movsx and movzx ops
 2017-02-07 17:26:35 +01:00
SchumBlubBlub
6c00c9e2d5 Reorganize string macros 2017-02-06 00:00:03 +01:00
pancake
bd25a763d8 Fix null deref and infinite loop when building with no plugins 2017-02-02 13:25:21 +01:00
pancake
5fa9601abe Implement add+sub for arm64 2017-01-29 14:48:13 +01:00
pancake
f64b082bd2 Implement adr instruction for the arm64 assembler 2017-01-29 14:08:04 +01:00
pancake
3c9e80372f Fix #6598 - r2pm db2 issue and add 2 arm64 bonus ops to the assembler 2017-01-29 03:44:18 +01:00
pancake
1627b990ad Add hvc and smc instructions in the arm64 assembler 2017-01-29 03:24:47 +01:00
pancake
196c800b87 Implement svc instruction for the arm64 assembler 2017-01-29 02:36:44 +01:00
Sven Steinbauer
4e73901e31 Add arm64 mov instruction (#6594) 
Only handles immediates up to 32 at the moment.

FIX #6588
 2017-01-27 20:49:34 +01:00
Álvaro Felipe Melchor
088c13ddad Fix UAF in cb_asmarch 2017-01-25 23:20:20 +01:00
pancake
d9fb5713db Fix racy set of asm.cpu and asm.arch 2017-01-24 13:57:17 +01:00
pancake
197443d42a asm.cpu=cortex required for arm (not by default) 2017-01-23 03:02:35 +01:00
Sven Steinbauer
7c49535f07 Add cmov* support to x86.nz (#6544) 2017-01-20 17:14:08 +01:00
pancake
9467d350cc nomclass is not for arm64 2017-01-18 15:14:31 +01:00
pancake
40f70bdf21 Fix #6400 - Properly set CS_MODE_MCLASS for Thumb 2017-01-17 18:25:48 +01:00
Sven Steinbauer
658241f038 Fix spp directive replacement 2017-01-17 15:24:04 +00:00
Sven Steinbauer
a8d3d5b996 Retire x86_olly to r2e (#6521) 2017-01-17 14:28:14 +00:00
Sven Steinbauer
4687135c5b Add asm directives help (-hh) and update manpage 2017-01-16 12:03:06 +01:00
pancake
2a83f21a3e Make gcc6 warnings happy 2017-01-15 22:02:57 +01:00
Sven Steinbauer
4fe5d34b44 Add comment for r_asm_from_string 2017-01-10 12:27:09 +00:00
Sven Steinbauer
58252b4cc2 Fix #6356 - Move spp integration to libr/asm.c 
* Make spp parsing optional
* Add -p arg to rasm2
 2017-01-10 00:57:49 +01:00
pancake
529c578487 Fix rax2 Ox (octal output) 2017-01-09 00:46:32 +01:00
Sven Steinbauer
583ca82dd9 ARM asm Fix #6436 (#6441) 
Fix order of opcodes in comparison list to check against ands over and.
 2017-01-07 01:45:10 +01:00
Sven Steinbauer
b517c80945 Fix check for al register (#6382) 
Also check it's not memory. Move checks into own function.
 2016-12-27 10:41:42 +01:00
Sven Steinbauer
8c30faf35c group1 instructions generate short opcodes FIX #6377 (#6378) 
For group 1 instructions with AL for op1 and a constant for op2, nz will
now generate the shorter opcodes
 2016-12-26 14:13:36 +01:00
pancake
130c22fc49 XOR assemble for x86.nz requires 2 parameters 2016-12-26 02:20:57 +01:00
pancake
d7240fac8e Fix latest covs 2016-12-22 16:13:49 +01:00
Álvaro Felipe Melchor
1a05aecaa4 Fix uaf in bin_dex.c and oob write in pi with dex 2016-12-19 19:41:10 +01:00
Álvaro Felipe Melchor
88d4649cc6 fix more coverities 2016-12-19 17:23:30 +01:00
pancake
50d73d1547 Fix a lot of memleaks, null derefs and undef behaviour thanks to clang-analyzer 2016-12-19 16:44:51 +01:00
pancake
9039228b58 Honor Q as an alias for q! in visual and prompt 2016-12-19 04:46:50 +01:00
pancake
2c5400e03e Fix more CIDs, memleaks mainly 2016-12-19 04:21:56 +01:00
Álvaro Felipe Melchor
a874de805e clean up code applying coding style 2016-12-15 21:04:27 +01:00
Gerardo García Peña
f40cbcee33 Set ATmega8 MCU by default. (#6291) 2016-12-08 01:22:54 +01:00
Álvaro Felipe Melchor
028e8f0ca3 Fix few covs 2016-12-04 22:26:17 +01:00
Sven Steinbauer
e4b5f0f32b Cleanup opjc for x86_nz 2016-12-01 10:07:53 +00:00
pancake
cb06c9c26b Fix #6270 - Honor current offset when assembling conditional jumps in x86 2016-11-30 16:22:34 +01:00
pancake
7e07579cdc Fix last covs 2016-11-20 12:20:05 +01:00
Sven Steinbauer
5010de936f Add br and blr (#6217) 2016-11-17 16:54:24 +00:00
Sven Steinbauer
8cf9af578c Add arm64 branch instructions (#6216) 2016-11-17 17:05:13 +01:00
Sven Steinbauer
dec588687a Fix add and sub for arm thumb FIX #6181 (#6198) 
* Enhance sub op support for thumb arch

Generate correct instructions up to 0x100

* Improve support for add instruction for thumb arch
 2016-11-16 11:25:11 +00:00
pancake
23cb88355d Remove global code_align into RAsmCode 2016-11-16 01:24:09 +01:00
pancake
72b2249110 aae now flag all syscalls found in the binary 2016-11-15 12:55:09 +01:00
pancake
11f2c4fe4f Add more movk/movz/movn for the arm64 assembler 2016-11-15 11:57:48 +01:00
radare
7852d92713 thumb assembly issues fix #3122 (#6189) 
* Fix thumb ldr r0, [rN] assembly

* Handle numeric values for ldr rN, [rN, N]

does not handle special cases with values ending in 0, 4, 8

* Fix ldr assembly for 4 bit values

values that can be expressed with 4 bits care outputted with shorter instructions.

* Add support for blx op with register values

* Fix mov instruction with register as first parm
 2016-11-14 14:23:38 +01:00
Sven Steinbauer
cd37be0406 Fix mov instruction with register as first parm 2016-11-14 12:14:51 +00:00
Sven Steinbauer
64bea8794c Add support for blx op with register values 2016-11-14 11:48:49 +00:00
Sven Steinbauer
ef448c64fe Fix ldr assembly for 4 bit values 
values that can be expressed with 4 bits care outputted with shorter instructions.
 2016-11-14 09:18:37 +00:00
Duncan Ogilvie
e16b490db5 fixed incorrect jna/jbe (#6185) 2016-11-12 17:58:00 +01:00
Sebastian Reichel
e9383b1441 Arch independent data in share (#6183) 
* magic data is architecture independent

* fcnsign data is architecture independent

* opcode data is architecture independent

* syscall data is architecture independent

* hud data is architecture independent
 2016-11-12 11:08:34 +01:00
Sven Steinbauer
9eb8802a0e Handle numeric values for ldr rN, [rN, N] 
does not handle special cases with values ending in 0, 4, 8
 2016-11-11 19:09:42 +00:00
Sven Steinbauer
26cdbfdbdc Fix thumb ldr r0, [rN] assembly 2016-11-11 08:37:06 +00:00
Sebastian Reichel
ff868af3be asm_m68k_cs: Add missing CORELIB check (#6169) 
radare_plugin should not be defined for builtin plugins.
 2016-11-10 10:14:45 +01:00
Stefan Marsiske
ec4e60d2bd fix radare_plugin redundantly defined (#6165) 
without these guards the linker complains:

p/asm_z80.o:(.data.rel+0x0): multiple definition of `radare_plugin'
p/asm_m68k_cs.o:(.data.rel+0x0): first defined here
collect2: error: ld returned 1 exit status
 2016-11-09 17:35:47 +01:00
Álvaro Felipe Melchor
f5166f936d Fix some meamleaks (#6156) 2016-11-09 02:28:14 +01:00
Álvaro Felipe Melchor
3222447eab Fix warnings when compiling in linux 2016-11-08 01:58:07 +01:00
Álvaro Felipe Melchor
9f6c3a2c8a fix warning in tms320 s/st8/char/g 2016-11-07 22:31:09 +01:00
Álvaro Felipe Melchor
f941d219fe revert change on ins.c 2016-11-07 21:23:05 +01:00
Álvaro Felipe Melchor
302d3f52e9 Take into account section alignment 2016-11-06 22:00:08 +01:00
Sven Steinbauer
e797258741 Test for valid numbers in arm getnum function (#6118) 
* Test for valid numbers in arm getnum function

Using strtod it's possible to test if the string passed in is a valid
number

Also handles hexvalues

* KISS the fix
 2016-11-05 10:38:42 +01:00
szt
f29a91b63a arm chars are unsigned by default 
http://blog.cdleary.com/2012/11/arm-chars-are-unsigned-by-default/
 2016-11-04 04:49:34 +01:00
Sven Steinbauer
80da50f31f Error on invalid b instruction (#6109) 
If label resolves to an offset of 0, assume instruction invalid
 2016-11-04 00:34:56 +01:00
Álvaro Felipe Melchor
601bd60e4d refix r_asm_set_big_endian 2016-11-03 13:47:51 +01:00
Álvaro Felipe Melchor
53655fd3c2 fix regression 2016-11-03 13:42:37 +01:00
pancake
2e23217ccd Add support for .endian rasm2 directive 2016-11-03 12:49:16 +01:00
pancake
cb1f0c79ce Support /**/ in a single line 2016-11-03 12:32:50 +01:00
pancake
0fb0a170d2 Fix /**/ comments in rasm2 2016-11-03 12:29:08 +01:00
pancake
90fcf76623 Initial support for .align in rasm2 2016-11-03 12:01:54 +01:00
pancake
9d1f080b59 Fix heap overflow in rasm2 2016-11-03 11:11:50 +01:00
pancake
39f25ae2db Support /**/ in rasm2 -f 2016-11-03 10:39:20 +01:00
pancake
37454c1dc1 Fix #6052 - ?O supports name -> id 2016-11-02 03:49:55 +01:00
Sven Steinbauer
ab2551691c Add arm shift ops FIX #5482 (#6081) 2016-11-01 00:56:27 +01:00
pancake
4421b2ef72 Fix m68k plugin name 2016-10-31 00:00:01 +01:00
Maijin
e5b30f91d8 Add Oj Fix #6074 
Add Oj Fix #6074
 2016-10-30 12:39:49 +01:00
pancake
e31164a5fa Fix latest covs 2016-10-29 13:06:11 +02:00
Sven Steinbauer
54afd47d9e Remove m68k asm and anal from core (#6063) 
* Remove m68k disassembler - Moving to extras
* Remove m68k anal plugin - Gets moved to r2e to be installed with m68k
 2016-10-28 12:54:48 +02:00
Sven Steinbauer
7d5f4cbde7 Assemble 64bit byte mov correctly [FIX 6042] (#6053) 
$ rasm2 -a x86 -b 64 'mov byte [rbp - 0x100], 2'
c68500ffffff02

Oddly this also compiles correctly before this patch with keystone
installed. Not sure as to why yet.
 2016-10-27 15:14:10 +02:00
pancake
94d47c79bb Completely remove all references to list.h 2016-10-27 13:33:27 +02:00
pancake
e925e04ea2 Fix crash in disassembler 2016-10-27 01:42:00 +02:00
pancake
d41b577106 Fix #5924 - r_flags -> r_flag 2016-10-27 01:07:58 +02:00
pancake
3ab7122df2 Implement ?O and r_asm_mnemonics() new API 2016-10-27 00:54:48 +02:00
pancake
589ac97bda Fix some overflow-related covs 2016-10-26 23:40:17 +02:00
pancake
8d37adc546 Fix all pending null-deref covs 2016-10-26 23:22:04 +02:00
Álvaro Felipe Melchor
a2befc8adc Enhance performance in r_anal_fcn_get_in() using tinyrange and sorted adds 
* added sorted parameter in r_list
* use r_list_sort in r_range_sort
* some clean up
* added is_data into RBinSection
* use tinyrange by default to improve speed
 2016-10-25 01:12:06 +02:00
Sven Steinbauer
52cc4dfe95 Move Z80 non-commercial to r2e (#6015) 
* Move z80 non-commercial to r2e

Rename z80-cr to z80 as a consequence as it will be the default z80 disassembler

* Add GPL z80 assembler back in

* Fix Clang build
 2016-10-24 13:21:36 +01:00
Álvaro Felipe Melchor
0cd32b4090 fix build 2016-10-24 11:58:35 +02:00
Sven Steinbauer
aa5fd3253c Update and fix LGPL Z80 disassembler (#6009) 
* Fix dd IX instructions

* Fix segfault for dd and de ops

Although only seemed to happen on OSX, not on linux.

* Fix ed op

* Remove invalid instruction "in f, [c]" which is not referenced in
http://clrhome.org/table/

* fix bad offsets to ops following removed one

* Fix fd ops with bad type flags

* Fix ed and fdcb ops

Remove debug prints
 2016-10-24 10:28:59 +01:00
pancake
35d9eef757 Fix 20 more covs (divBy0, dbl3, negidx, bufovr, ..) 2016-10-20 15:39:36 +02:00
pancake
be9df39f6f Fixed 40 null derefs reported by coverity 2016-10-20 15:02:25 +02:00
pancake
7a1b6871d9 Fix a bunch of outstanding coverities 2016-10-20 14:11:02 +02:00
Sven Steinbauer
4a2fba6168 Add segment reg support and numerous fixes FIX #5967 (#5995) 
* Add support for seg registers

Support added for mov and pop instructions

[fs] is treated as [fs:0] which is not equivalent

Accepts sreg:[x] and [sreg:x] syntax

* Error if mov op reg sizes differ

also add support for 16bit register mov ops

* Improve segment register handling for mov op

* Fix opcode for 64bit instr with 32bits regs

* Refactor parsing of segment reg offset
 2016-10-19 21:10:17 +01:00
Sven Steinbauer
f6b0ba574b Fix for issue #5976 (#5979) 
Check that register is not memory i.e. [eax] to generate correct opcode
 2016-10-17 15:45:38 +02:00
szt
45bbca4e29 Fix "orr" in ARM assembler (#5958) 
https://github.com/radare/radare2/issues/5954 fix
 2016-10-12 23:33:53 +02:00
Álvaro Felipe Melchor
84b4b1b8f6 fix regression 2016-10-10 21:09:30 +02:00
pancake
3ae8b9813b Get rid of some %\d$ constructions in anal_8051.c for #3944 2016-10-10 10:20:51 +02:00
Duncan Ogilvie
d0cccc5ec7 updated various opcode descriptions (#5948) 2016-10-09 19:11:40 +02:00
Álvaro Felipe Melchor
66a55302ee Fix build 2016-10-08 13:25:16 +02:00
pancake
cd26e34a7b Blind fix #5938 - remove some __FILE__ references 2016-10-08 03:01:22 +02:00
pancake
a8af78c7a6 Rollback the z80 change 2016-10-08 02:40:40 +02:00
pancake
0cf6623f52 Kill the z80.cr plugin, and use the disasm into z80 2016-10-08 01:35:27 +02:00
Duncan Ogilvie
8386438ea0 fixed and added opcode descriptions (#5942) 2016-10-07 18:35:40 +02:00
pancake
d7e0be5dad Implement rasm2 -s? and refactor this a bit 2016-10-04 15:01:02 +02:00
pancake
1e89dddd87 Fixes in oa, asm.bits, avr and io debug issues 2016-09-26 00:46:20 +02:00
Álvaro Felipe Melchor
7c8292b9fb Fix warnings and coding style 2016-09-25 01:27:05 +02:00
h4ng3r
e1889b31a1 Fix some BR test from asm.dalvik 2016-09-25 01:26:52 +02:00
Sven Steinbauer
8ab5f5fb5b Add short jumps to nz (#5832) 2016-09-23 17:26:07 +02:00
Marc
0c8556bb22 Fix some DEX disasm issues (#5829) 2016-09-23 00:33:25 +02:00
Vlad Ivanov
438f151d6c asm_xtensa: fix possible buffer overrun (#5820) 2016-09-22 12:21:37 +02:00
Gerardo García Peña
91cb15a3e7 New opcodes and operations in AVR anal plugin. (#5783) 2016-09-20 13:48:17 +02:00
Álvaro Felipe Melchor
05ae77eda4 fix warning & remove check in version info elf 2016-09-19 15:47:19 +02:00