pancake
bbc508b324
Move lua53 plugins to radare2-extras, available via r2pm
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This reverts commit 16c2fd2fe4
2017-04-05 10:16:50 +02:00
Pepe Vila
86c8fa1a01
wasm disasm support ( #7204 )
2017-04-04 02:34:31 +02:00
Cararasu
16c2fd2fe4
Lua 5.3 Assembler/Disassembler, Analyzer and Binary Plugin ( #3836 ) ( #7197 )
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* Added Lua 5.3 Assembly and Disassembly
* Implemented Lua 5.3 Binary Analyzer #3836
* removed unnecesasry prints for lua implementation #3836
* implemented caching for parsing the lua-file #3836 grouped global data together
* added mnemonics to analyzer and fixed a wrong instructionname
* replaced llx and llu with PFMT64x
* removed trailing whitespaces from lua 5.3 assembler and binary analyzer
* made all functions in lua53 plugins that are possible static
2017-04-03 11:59:17 +02:00
alvarofe
643267ab67
Fix some warnings when compiling
2017-04-02 12:43:25 +02:00
alvarofe
42fb071d4b
Fix #7198 - static code analysis by AppChecker
2017-04-02 12:22:04 +02:00
Sven Steinbauer
a6c4939b62
Fix single operand parsing for arm64 ( #7191 )
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FIX #7189
2017-03-31 12:52:08 +02:00
Thomas Ilsche
1a72b58daa
fix NULL deref on failed strbuf_new and memory leak in r_asm_mdisassemble ( #7163 )
2017-03-29 00:44:36 +02:00
pancake
74690db2b1
Dont enable v8 mode on arm64 for capstone
2017-03-28 13:25:29 +02:00
pancake
265a44c0d2
Fix #7133 - asm.cpu=v8 doesnt toggles cortex
2017-03-28 11:37:23 +02:00
pancake
c504b85a7c
Fix #7117 - Implement s! to show near flag names for history offsets
2017-03-27 13:12:59 +02:00
pancake
6de49610ea
Add 40 more asm.describe for Thumb2
2017-03-27 12:38:14 +02:00
Sven Steinbauer
3e72eb21c7
Fix bad 64 bit assembly for group1 ops ( #7146 )
2017-03-26 23:55:53 +02:00
Sven Steinbauer
06a36c923f
Error on trailing for add op 16bit ( #7147 )
2017-03-26 23:55:46 +02:00
Sven Steinbauer
3aa18670ec
Support assembling the BND prefix on x86.nz branch instructions
2017-03-24 12:22:04 +01:00
Q
49a54115d3
Fix multiple definition of 'snesflags' in static build
2017-03-24 11:10:30 +01:00
Giovanni
1a5ffd5221
Fix sparc regressions, ahi s and pd@x
2017-03-24 02:42:31 +01:00
radare
321e51fa6a
Update the GNU ARM disassembler from Binutils (GIT)
2017-03-24 00:56:21 +01:00
/usr/share
87b78b63eb
SNES: (kinda) handle X and M flags ( #7095 )
2017-03-23 12:53:14 +01:00
alvarofe
ce25037120
Fix #7070 - oob read wrong init buffer asm_sh.c
2017-03-20 23:28:38 +01:00
pancake
e2df61f48e
Fixes for m68k -n 16 and sega mega drive roms endian
2017-03-19 11:33:39 +01:00
davidpolverari
1fb422b532
Fix #6162 - Renames r_str_concat to r_str_append
2017-03-16 22:29:49 +01:00
Sven Steinbauer
bd884531f0
Add 16bit jmp x86 ( #7023 )
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Add 16bit jmp x86
2017-03-14 16:19:43 +00:00
Sven Steinbauer
5a4c18f49a
Add ARM64 barrier ops
2017-03-13 17:53:26 +01:00
Sven Steinbauer
b4d74880c2
Add shift support to ldr instructions ( #7014 )
2017-03-13 14:27:35 +01:00
Simone Ferrini
a5cc36525f
[armass] Added support for sequence registers in pop instruction ( #6994 )
2017-03-12 19:18:28 +01:00
Álvaro Felipe Melchor
6870bec29f
Fix #6853 - get rid of asserts
2017-03-12 15:24:05 +01:00
Lowly Worm
b9302dd4b6
fix typo in WebAssemlby
2017-03-10 23:27:45 -08:00
Sven Steinbauer
73ff7ec410
implement ORR for arm64 FIX #6611 ( #6977 )
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* implement ORR for arm64 FIX #6611
Implements or with registers and immediate (not yet with rot values for
registers)
* Squash warnings
2017-03-10 15:38:04 +01:00
Simone Ferrini
781b3fc58e
Fix BL for arm thumb ( #6968 )
2017-03-09 23:47:03 +01:00
pancake
bb4f591d93
Fix capstone3 build regression introduced in 272786852b
2017-03-09 00:02:28 +01:00
Wladimir J. van der Laan
10d1df6dd2
Update RiscV opcodes for disassembly ( #6897 )
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* riscv: Update opcodes from binutils-gdb
Update to riscv opcodes from
[riscv-binutils-gdb](https://github.com/riscv/riscv-binutils-gdb/commit/08219b2 )
git 08219b2.
* riscv: set no_alias=false while disassembling
I'm not sure what the rationale was for setting no_alias to true
originally. But setting it to false means that shorter and (usually)
better readable aliases for instructions will be shown:
Before | After
---------------------+------------
`c.jr ra` | `ret`
`addi a5, zero, 123` | `li a5,123`
`jal zero, 0x101dc` | `j 0x101dc`
And so on.
2017-03-04 10:18:45 +01:00
Q
b7db017fa5
Fix multiple definition error in static builds ( #6891 )
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Rename conflicting global names 'fields' array in AArch64
and 'fields' function in MachoO
2017-03-03 10:53:41 +01:00
dogtopus
247a8df1e7
Add getimmed8, fix #6841 ( #6892 )
2017-03-03 08:24:24 +01:00
pancake
8ab0befbd7
Remove assert in GNU's arm64 disassembler
2017-03-03 01:30:56 +01:00
Giovanni
780b834e61
Fix #6882 - tricore byte copy
2017-03-03 00:10:32 +01:00
h4ng3r
f41e941341
Fix #6885 - oob write in dalvik_disassemble
2017-03-02 22:51:57 +01:00
pancake
34089ab363
Fix entrypoint in wasm and add some uleb128-based instructions
2017-03-02 18:45:10 +01:00
Giovanni
aaa46baa48
fixed tricore bug ( #6883 )
2017-03-02 17:56:43 +01:00
pancake
a41a8252ae
Initial import of the WIP support for WebAssembly (bin + disasm)
2017-03-02 14:42:05 +01:00
pancake
d6756e235c
Implement author and version of RAsmPlugin
2017-02-28 02:26:55 +01:00
pancake
3b83e18c51
Remove assert for the GNU arm64 disassembler
2017-02-26 23:34:24 +01:00
Wladimir J. van der Laan
aab2bc824c
riscv: Choose first match while disassembling
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The opcodes table is sorted with the preferred instructions with a
certain encoding first.
2017-02-26 23:06:32 +01:00
Wladimir J. van der Laan
78089cd34f
riscv: Return actual instruction length
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Support instructions of varying length.
Addresses #6849 .
2017-02-26 23:06:32 +01:00
Maijin
266eee75ae
Fix #6560 Unify Windows/Win32 define
2017-02-26 16:51:03 +01:00
alvarofe
f992370474
Fix some memory leaks after ht clean up
2017-02-25 23:50:33 +01:00
alvarofe
0b97b11d38
Fix regression on tms320
2017-02-24 23:42:17 +01:00
alvarofe
8ff55080ea
Use ht_* in tms320
2017-02-24 23:42:17 +01:00
Sven Steinbauer
7d71bf5fa2
x86.nz infer bits from register names ( #6792 )
2017-02-15 11:49:35 +01:00
Sven Steinbauer
65791475ff
Refactor msr mrs instructions
2017-02-10 13:11:14 +01:00
Sven Steinbauer
d5c9a65a97
Refactor exceptions
2017-02-10 13:11:14 +01:00
