radare2/libr/asm/arch/riscv
Wladimir J. van der Laan 10d1df6dd2 Update RiscV opcodes for disassembly (#6897)
* riscv: Update opcodes from binutils-gdb

Update to riscv opcodes from
[riscv-binutils-gdb](https://github.com/riscv/riscv-binutils-gdb/commit/08219b2)
git 08219b2.

* riscv: set no_alias=false while disassembling

I'm not sure what the rationale was for setting no_alias to true
originally. But setting it to false means that shorter and (usually)
better readable aliases for instructions will be shown:

Before               |  After
---------------------+------------
`c.jr ra`            | `ret`
`addi a5, zero, 123` | `li a5,123`
`jal zero, 0x101dc`  | `j 0x101dc`

And so on.
2017-03-04 10:18:45 +01:00
..
riscv-opc.c Update RiscV opcodes for disassembly (#6897) 2017-03-04 10:18:45 +01:00
riscv-opc.h Update RiscV opcodes for disassembly (#6897) 2017-03-04 10:18:45 +01:00
riscv.c Update RiscV opcodes for disassembly (#6897) 2017-03-04 10:18:45 +01:00
riscv.h Update RiscV opcodes for disassembly (#6897) 2017-03-04 10:18:45 +01:00