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https://github.com/radareorg/radare2.git
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597 lines
14 KiB
C
597 lines
14 KiB
C
/* radare - LGPL - Copyright 2009-2014 - nibble, pancake */
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#include <r_lib.h>
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#include <r_types.h>
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#include <r_anal.h>
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#include <r_util.h>
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#include "udis86/types.h"
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#include "udis86/extern.h"
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#include "esil.h"
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static st64 getval(ud_operand_t *op);
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// XXX Copypasta from udis
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#define UD_REG_TAB_SIZE (sizeof (ud_reg_tab)/sizeof (*ud_reg_tab))
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static const char* ud_reg_tab[] =
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{
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"al", "cl", "dl", "bl",
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"ah", "ch", "dh", "bh",
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"spl", "bpl", "sil", "dil",
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"r8b", "r9b", "r10b", "r11b",
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"r12b", "r13b", "r14b", "r15b",
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"ax", "cx", "dx", "bx",
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"sp", "bp", "si", "di",
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"r8w", "r9w", "r10w", "r11w",
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"r12w", "r13w", "r14w", "r15w",
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"eax", "ecx", "edx", "ebx",
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"esp", "ebp", "esi", "edi",
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"r8d", "r9d", "r10d", "r11d",
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"r12d", "r13d", "r14d", "r15d",
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"rax", "rcx", "rdx", "rbx",
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"rsp", "rbp", "rsi", "rdi",
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"r8", "r9", "r10", "r11",
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"r12", "r13", "r14", "r15",
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"es", "cs", "ss", "ds",
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"fs", "gs",
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"cr0", "cr1", "cr2", "cr3",
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"cr4", "cr5", "cr6", "cr7",
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"cr8", "cr9", "cr10", "cr11",
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"cr12", "cr13", "cr14", "cr15",
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"dr0", "dr1", "dr2", "dr3",
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"dr4", "dr5", "dr6", "dr7",
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"dr8", "dr9", "dr10", "dr11",
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"dr12", "dr13", "dr14", "dr15",
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"mm0", "mm1", "mm2", "mm3",
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"mm4", "mm5", "mm6", "mm7",
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"st0", "st1", "st2", "st3",
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"st4", "st5", "st6", "st7",
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"xmm0", "xmm1", "xmm2", "xmm3",
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"xmm4", "xmm5", "xmm6", "xmm7",
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"xmm8", "xmm9", "xmm10", "xmm11",
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"xmm12","xmm13", "xmm14", "xmm15",
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"ymm0", "ymm1", "ymm2", "ymm3",
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"ymm4", "ymm5", "ymm6", "ymm7",
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"ymm8", "ymm9", "ymm10", "ymm11",
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"ymm12","ymm13", "ymm14", "ymm15",
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"rip"
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};
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static int getarg(char *src, struct ud *u, st64 mask, int idx) {
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ud_operand_t *op = &u->operand[idx];
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st64 n;
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src[0] = 0;
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if (!mask) mask = UT64_MAX;
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switch (op->type) {
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case UD_OP_PTR:
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case UD_OP_CONST:
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case UD_OP_JIMM:
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case UD_OP_IMM:
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n = getval (op);
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if (op->type == UD_OP_JIMM)
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n += u->pc;
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if (n>=0 && n<256)
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sprintf (src, "%"PFMT64d, n & mask);
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else sprintf (src, "0x%"PFMT64x, n & mask);
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break;
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case UD_OP_REG:
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idx = op->base-UD_R_AL;
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if (idx>=0 && idx<UD_REG_TAB_SIZE)
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strcpy (src, ud_reg_tab[idx]);
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break;
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case UD_OP_MEM:
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n = getval (op);
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// TODO ->scale
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if (op->base != UD_NONE) {
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idx = op->base-UD_R_AL;
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if (idx>=0 && idx<UD_REG_TAB_SIZE) {
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if (u->mnemonic == UD_Ilea)
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sprintf (src, "%s", ud_reg_tab[idx]);
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else sprintf (src, "[%s", ud_reg_tab[idx]);
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src += strlen (src);
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if (op->index != UD_NONE) {
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idx = op->index - UD_R_AL;
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if (idx >= 0 && idx < UD_REG_TAB_SIZE)
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sprintf (src, "+%d*%s", op->scale, ud_reg_tab[idx]);
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src += strlen (src);
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}
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if (u->mnemonic == UD_Ilea) {
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if (n>0) sprintf (src, "+%"PFMT64d, n);
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else if (n<0) sprintf (src, "%"PFMT64d, n);
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} else if (n >= -256 && n < 256)
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sprintf (src, "%+d]", (int) n);
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else
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sprintf (src, "+0x%"PFMT64x"]", mask & n);
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}
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else sprintf (src, "[unknown_reg_%d]", idx); /* If UDis86 works properly, it will never reach this point. Only useful for debug purposes ("unknown reg" is clearer than an empty string, right?) */
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}
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else sprintf (src, "[0x%"PFMT64x"]", n & mask);
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break;
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default:
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break;
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}
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return 0;
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}
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static st64 getval(ud_operand_t *op) {
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int bits = op->size;
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switch (op->type) {
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case UD_OP_PTR:
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return (op->lval.ptr.seg<<4) + (op->lval.ptr.off & 0xFFFF);
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default:
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break;
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}
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if (!bits) bits = 32;
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switch (bits) {
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case 8: return (char)op->lval.sbyte;
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case 16: return (short) op->lval.uword;
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case 32: return op->lval.udword;
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case 64: return op->lval.uqword;
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}
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return 0LL;
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}
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int x86_udis86_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len) {
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const char *pc = anal->bits==64? "rip": anal->bits==32? "eip": "ip";
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const char *sp = anal->bits==64? "rsp": anal->bits==32? "esp": "sp";
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const char *bp = anal->bits==64? "rbp": anal->bits==32? "ebp": "bp";
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int oplen, regsz = 4;
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char str[64], src[32], dst[32];
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struct ud u;
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switch (anal->bits) {
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case 64: regsz = 8; break;
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case 16: regsz = 2; break;
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default:
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case 32: regsz = 4; break;
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}
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UDis86Esil *handler;
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UDis86OPInfo info = {0, anal->bits, (1LL << anal->bits) - 1, regsz, 0, pc, sp, bp};
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memset (op, '\0', sizeof (RAnalOp));
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op->addr = addr;
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op->jump = op->fail = -1;
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op->ptr = op->val = -1;
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ud_init (&u);
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ud_set_pc (&u, addr);
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ud_set_mode (&u, anal->bits);
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ud_set_syntax (&u, NULL);
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ud_set_input_buffer (&u, data, len);
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ud_disassemble (&u);
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oplen = op->size = ud_insn_len (&u);
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r_strbuf_init (&op->esil);
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if (anal->decode && (handler = udis86_esil_get_handler (u.mnemonic))) {
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info.oplen = oplen;
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if (handler->argc > 0) {
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info.n = getval (u.operand);
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getarg (dst, &u, info.bitmask, 0);
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if (handler->argc > 1) {
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getarg (src, &u, info.bitmask, 1);
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if (handler->argc > 2)
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getarg (str, &u, info.bitmask, 2);
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}
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}
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handler->callback (&info, op, dst, src, str);
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}
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switch (u.mnemonic) {
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case UD_Iinvalid:
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oplen = op->size = -1;
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return -1;
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break;
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case UD_Itest:
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case UD_Icmp:
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op->type = R_ANAL_OP_TYPE_CMP;
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break;
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case UD_Isalc: // ??
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// al = cf
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break;
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case UD_Ixor:
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op->type = R_ANAL_OP_TYPE_XOR;
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break;
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case UD_Ior:
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op->type = R_ANAL_OP_TYPE_OR;
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break;
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case UD_Iand:
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op->type = R_ANAL_OP_TYPE_AND;
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break;
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case UD_Isar:
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op->type = R_ANAL_OP_TYPE_SAR;
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break;
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// XXX: sal ?!?
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case UD_Ishl:
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op->type = R_ANAL_OP_TYPE_SHL;
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break;
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case UD_Ishr:
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op->type = R_ANAL_OP_TYPE_SHR;
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break;
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case UD_Irol:
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op->type = R_ANAL_OP_TYPE_ROL;
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break;
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case UD_Iror:
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op->type = R_ANAL_OP_TYPE_ROR;
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break;
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case UD_Iint3:
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op->type = R_ANAL_OP_TYPE_TRAP;
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break;
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case UD_Iint:
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op->type = R_ANAL_OP_TYPE_SWI;
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op->val = u.operand[0].lval.uword;
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break;
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case UD_Ilea:
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case UD_Imov:
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op->type = R_ANAL_OP_TYPE_MOV;
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switch (u.operand[1].type) {
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case UD_OP_MEM:
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op->type = R_ANAL_OP_TYPE_MOV;
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if (u.operand[1].base == UD_R_RIP) {
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int delta = u.operand[1].lval.uword;
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op->ptr = addr + oplen + delta;
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}
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break;
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default:
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op->type = R_ANAL_OP_TYPE_MOV;
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op->ptr = getval (&u.operand[1]);
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// XX
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break;
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}
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op->stackop = R_ANAL_STACK_INC;
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op->stackptr = regsz;
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break;
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case UD_Ipush:
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case UD_Ipusha:
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case UD_Ipushad:
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case UD_Ipushfq:
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case UD_Ipushfd:
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case UD_Ipushfw:
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switch (u.operand[0].type) {
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case UD_OP_CONST:
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case UD_OP_JIMM:
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case UD_OP_IMM:
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op->type = R_ANAL_OP_TYPE_PUSH;
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op->ptr = getval (&u.operand[0]);
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break;
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case UD_OP_REG:
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case UD_OP_PTR:
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case UD_OP_MEM:
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default:
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op->type = R_ANAL_OP_TYPE_UPUSH;
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op->ptr = 0;
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break;
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}
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op->stackop = R_ANAL_STACK_INC;
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op->stackptr = regsz;
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break;
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case UD_Ipop:
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case UD_Ipopa:
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case UD_Ipopad:
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case UD_Ipopfw:
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case UD_Ipopfd:
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case UD_Ipopfq:
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op->type = R_ANAL_OP_TYPE_POP;
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op->stackop = R_ANAL_STACK_INC;
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op->stackptr = -regsz;
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break;
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case UD_Ileave:
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op->type = R_ANAL_OP_TYPE_MOV;
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op->stackop = R_ANAL_STACK_INC;
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op->stackptr = -regsz;
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break;
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case UD_Iadd:
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case UD_Isub:
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op->type = (u.mnemonic==UD_Iadd)? R_ANAL_OP_TYPE_ADD: R_ANAL_OP_TYPE_SUB;
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op->ptr = 0;
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op->stackptr = 0;
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if (u.operand[0].type == UD_OP_REG) {
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if (u.operand[0].base == UD_R_RSP) {
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int o = (int)getval (&u.operand[1]);
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op->stackop = R_ANAL_STACK_INC;
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if (u.mnemonic ==UD_Iadd) {
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op->stackptr = -o;
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} else {
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op->stackptr = o;
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}
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}
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if (u.operand[1].type != UD_OP_REG)
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op->val = getval (&u.operand[1]);
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}
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op->stackptr = 4;
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break;
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case UD_Iadc:
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case UD_Iinc:
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op->type = R_ANAL_OP_TYPE_ADD;
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break;
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case UD_Isbb:
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case UD_Idec:
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op->type = R_ANAL_OP_TYPE_SUB;
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break;
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case UD_Ijmp:
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switch (u.operand[0].type) {
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case UD_OP_MEM:
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case UD_OP_REG:
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op->type = R_ANAL_OP_TYPE_UJMP;
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break;
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default:
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op->type = R_ANAL_OP_TYPE_JMP;
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#if 0
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{
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ut16 a = (op->lval.ptr.seg & 0xFFFF);
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ut16 b = (op->lval.ptr.off);
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switch (op->size) {
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case 32:
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sprintf (src, "%04x:%04x", a, b & 0xFFFF);
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break;
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case 48:
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sprintf (src, "%04x:%04x", a, b);
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break;
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default:
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eprintf ("FUCK YOU\n");
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}
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}
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#endif
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if (u.operand[0].type==UD_OP_PTR) {
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op->jump = getval (&u.operand[0]);
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} else {
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if (anal->bits==16) {
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// honor segment
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op->jump = (addr&0xf0000) + oplen + \
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((((addr&0xffff)+getval (&u.operand[0]))&0xffff));
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} else {
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op->jump = addr + oplen + (int)getval (&u.operand[0]);
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}
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}
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}
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break;
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case UD_Ije:
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case UD_Ijne:
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case UD_Ijb:
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case UD_Ijbe:
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case UD_Ija:
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case UD_Ijae:
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case UD_Ijs:
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case UD_Ijns:
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case UD_Ijo:
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case UD_Ijno:
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case UD_Ijp:
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case UD_Ijnp:
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case UD_Ijl:
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case UD_Ijge:
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case UD_Ijle:
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case UD_Ijg:
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case UD_Ijcxz:
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case UD_Iloop:
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op->type = R_ANAL_OP_TYPE_CJMP;
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op->jump = addr + oplen + (int)getval (&u.operand[0]);
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op->fail = addr+oplen;
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break;
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case UD_Icall:
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op->type = R_ANAL_OP_TYPE_CALL;
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switch (u.operand[0].type) {
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case UD_OP_REG:
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op->type = R_ANAL_OP_TYPE_UCALL;
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op->jump = 0; // EAX, EBX, ... use anal->reg
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break;
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case UD_OP_PTR:
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op->jump = (int)getval (&u.operand[0]);
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break;
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case UD_OP_IMM:
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case UD_OP_MEM:
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default:
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op->jump = addr + oplen + (int)getval (&u.operand[0]);
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}
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op->fail = addr + oplen;
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break;
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case UD_Ihlt:
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op->type = R_ANAL_OP_TYPE_TRAP; //HALT;
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break;
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case UD_Iret:
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case UD_Iretf:
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case UD_Isysret:
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op->type = R_ANAL_OP_TYPE_RET;
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op->stackop = R_ANAL_STACK_INC;
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op->stackptr = -regsz;
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break;
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case UD_Isyscall:
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op->type = R_ANAL_OP_TYPE_SWI;
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break;
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case UD_Inop:
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op->type = R_ANAL_OP_TYPE_NOP;
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break;
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default:
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break;
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}
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return oplen;
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}
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static int set_reg_profile(RAnal *anal) {
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/* XXX Dupped Profiles */
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if (anal->bits == 32)
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#if __WINDOWS__
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return r_reg_set_profile_string (anal->reg,
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"=pc eip\n"
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"=sp esp\n"
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"=bp ebp\n"
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"=a0 eax\n"
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"=a1 ebx\n"
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"=a2 ecx\n"
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"=a3 edi\n"
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"drx dr0 .32 4 0\n"
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"drx dr1 .32 8 0\n"
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"drx dr2 .32 12 0\n"
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"drx dr3 .32 16 0\n"
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"drx dr6 .32 20 0\n"
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"drx dr7 .32 24 0\n"
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/* floating save area 4+4+4+4+4+4+4+80+4 = 112 */
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"seg gs .32 132 0\n"
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"seg fs .32 136 0\n"
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"seg es .32 140 0\n"
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"seg ds .32 144 0\n"
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"gpr edi .32 156 0\n"
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"gpr esi .32 160 0\n"
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"gpr ebx .32 164 0\n"
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"gpr edx .32 168 0\n"
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"gpr ecx .32 172 0\n"
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"gpr eax .32 176 0\n"
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"gpr ebp .32 180 0\n"
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"gpr esp .32 196 0\n"
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"gpr eip .32 184 0\n"
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"seg cs .32 184 0\n"
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"seg ds .32 152 0\n"
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"seg gs .32 140 0\n"
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"seg fs .32 144 0\n"
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"gpr eflags .32 192 0 c1p.a.zstido.n.rv\n" // XXX must be flg
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"seg ss .32 200 0\n"
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/* +512 bytes for maximum supoprted extension extended registers */
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);
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#else
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return r_reg_set_profile_string (anal->reg,
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"=pc eip\n"
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"=sp esp\n"
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"=bp ebp\n"
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"=a0 eax\n"
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"=a1 ebx\n"
|
|
"=a2 ecx\n"
|
|
"=a3 edi\n"
|
|
"gpr eip .32 48 0\n"
|
|
"gpr ip .16 48 0\n"
|
|
"gpr oeax .32 44 0\n"
|
|
"gpr eax .32 24 0\n"
|
|
"gpr ax .16 24 0\n"
|
|
"gpr ah .8 24 0\n"
|
|
"gpr al .8 25 0\n"
|
|
"gpr ebx .32 0 0\n"
|
|
"gpr bx .16 0 0\n"
|
|
"gpr bh .8 0 0\n"
|
|
"gpr bl .8 1 0\n"
|
|
"gpr ecx .32 4 0\n"
|
|
"gpr cx .16 4 0\n"
|
|
"gpr ch .8 4 0\n"
|
|
"gpr cl .8 5 0\n"
|
|
"gpr edx .32 8 0\n"
|
|
"gpr dx .16 8 0\n"
|
|
"gpr dh .8 8 0\n"
|
|
"gpr dl .8 9 0\n"
|
|
"gpr esp .32 60 0\n"
|
|
"gpr sp .16 60 0\n"
|
|
"gpr ebp .32 20 0\n"
|
|
"gpr bp .16 20 0\n"
|
|
"gpr esi .32 12 0\n"
|
|
"gpr si .16 12 0\n"
|
|
"gpr edi .32 16 0\n"
|
|
"gpr di .16 16 0\n"
|
|
"seg xfs .32 36 0\n"
|
|
"seg xgs .32 40 0\n"
|
|
"seg xcs .32 52 0\n"
|
|
"seg cs .16 52 0\n"
|
|
"seg xss .32 52 0\n"
|
|
"gpr eflags .32 56 0 c1p.a.zstido.n.rv\n"
|
|
"gpr flags .16 56 0\n"
|
|
"flg carry .1 .448 0\n"
|
|
"flg flag_p .1 .449 0\n"
|
|
"flg flag_a .1 .450 0\n"
|
|
"flg zero .1 .451 0\n"
|
|
"flg sign .1 .452 0\n"
|
|
"flg flag_t .1 .453 0\n"
|
|
"flg flag_i .1 .454 0\n"
|
|
"flg flag_d .1 .455 0\n"
|
|
"flg flag_o .1 .456 0\n"
|
|
"flg flag_r .1 .457 0\n"
|
|
"drx dr0 .32 0 0\n"
|
|
"drx dr1 .32 4 0\n"
|
|
"drx dr2 .32 8 0\n"
|
|
"drx dr3 .32 12 0\n"
|
|
//"drx dr4 .32 16 0\n"
|
|
//"drx dr5 .32 20 0\n"
|
|
"drx dr6 .32 24 0\n"
|
|
"drx dr7 .32 28 0\n");
|
|
#endif
|
|
else return r_reg_set_profile_string (anal->reg,
|
|
"=pc rip\n"
|
|
"=sp rsp\n"
|
|
"=bp rbp\n"
|
|
"=a0 rax\n"
|
|
"=a1 rbx\n"
|
|
"=a2 rcx\n"
|
|
"=a3 rdx\n"
|
|
"# no profile defined for x86-64\n"
|
|
"gpr r15 .64 0 0\n"
|
|
"gpr r14 .64 8 0\n"
|
|
"gpr r13 .64 16 0\n"
|
|
"gpr r12 .64 24 0\n"
|
|
"gpr rbp .64 32 0\n"
|
|
"gpr ebp .32 32 0\n"
|
|
"gpr rbx .64 40 0\n"
|
|
"gpr ebx .32 40 0\n"
|
|
"gpr r11 .64 48 0\n"
|
|
"gpr r10 .64 56 0\n"
|
|
"gpr r9 .64 64 0\n"
|
|
"gpr r8 .64 72 0\n"
|
|
"gpr rax .64 80 0\n"
|
|
"gpr eax .32 80 0\n"
|
|
"gpr rcx .64 88 0\n"
|
|
"gpr ecx .32 88 0\n"
|
|
"gpr rdx .64 96 0\n"
|
|
"gpr edx .32 96 0\n"
|
|
"gpr rsi .64 104 0\n"
|
|
"gpr esi .32 104 0\n"
|
|
"gpr rdi .64 112 0\n"
|
|
"gpr edi .32 112 0\n"
|
|
"gpr oeax .64 120 0\n"
|
|
"gpr rip .64 128 0\n"
|
|
"seg cs .64 136 0\n"
|
|
//"flg eflags .64 144 0\n"
|
|
"gpr eflags .32 144 0 c1p.a.zstido.n.rv\n"
|
|
"gpr rsp .64 152 0\n"
|
|
"seg ss .64 160 0\n"
|
|
"seg fs_base .64 168 0\n"
|
|
"seg gs_base .64 176 0\n"
|
|
"seg ds .64 184 0\n"
|
|
"seg es .64 192 0\n"
|
|
"seg fs .64 200 0\n"
|
|
"seg gs .64 208 0\n"
|
|
"drx dr0 .32 0 0\n"
|
|
"drx dr1 .32 4 0\n"
|
|
"drx dr2 .32 8 0\n"
|
|
"drx dr3 .32 12 0\n"
|
|
"drx dr6 .32 24 0\n"
|
|
"drx dr7 .32 28 0\n");
|
|
}
|
|
|
|
struct r_anal_plugin_t r_anal_plugin_x86_udis = {
|
|
.name = "x86",
|
|
.desc = "X86 analysis plugin (udis86 backend)",
|
|
.license = "LGPL3",
|
|
.arch = R_SYS_ARCH_X86,
|
|
.bits = 16|32|64,
|
|
.init = NULL,
|
|
.fini = NULL,
|
|
.op = &x86_udis86_op,
|
|
.set_reg_profile = &set_reg_profile,
|
|
.fingerprint_bb = NULL,
|
|
.fingerprint_fcn = NULL,
|
|
.diff_bb = NULL,
|
|
.diff_fcn = NULL,
|
|
.diff_eval = NULL
|
|
};
|
|
|
|
#ifndef CORELIB
|
|
struct r_lib_struct_t radare_plugin = {
|
|
.type = R_LIB_TYPE_ANAL,
|
|
.data = &r_anal_plugin_x86_udis
|
|
};
|
|
#endif
|