Fabian Freyer e4d7f656ca
Fix incorrect esil of RISC-V auipc insn ##emu (#17787)
* According to the spec, the auipc instruction's immediate is a
  20-bit upper immediate, which means it should be left-shifted
  by 12 similar to the lui instruction:

  > AUIPC forms a 32-bit offset from the 20-bit U-immediate,
  > filling in the lowest 12 bits with zeros, adds this offset
  > to the address of the AUIPC instruction, then places the
  > result in register rd.
2020-10-16 12:52:42 +08:00
..
2020-10-16 12:52:01 +08:00
2020-10-15 18:14:03 +08:00
2020-09-27 13:33:26 +08:00
2020-09-27 13:33:26 +08:00
2020-09-27 13:33:26 +08:00