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288 lines
11 KiB
Plaintext
288 lines
11 KiB
Plaintext
ESIL
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====
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# source https://github.com/radare/radare2/wiki/ESIL
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ESIL stands for 'Evaluable Strings Intermedate Language'. It aims to describe a Forth-like representation for every opcode. Those representations can be evaluated in order to emulate code. Each element of an esil expression is separated by a comma. The VM can be described as this:
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```
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while ((word=haveCommand())) {
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if (word.isKeyword()) {
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esilCommands[word](esil);
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} else {
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esil.push (evaluateToNumber(word));
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}
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nextCommand();
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}
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```
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The esil commands are operations that pop values from the stack, performs some calculations and pushes the result in the stack (if any). They aim to cover all common operations done by CPUs, permitting to do binary operations, memory peeks and pokes, spawning a syscall, etc.
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#### Use ESIL
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```
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[0x00000000]> e asm.esil = true
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```
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Syntax
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======
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An opcode is translated into a comma separated list of ESIL expressions.
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```
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xor eax, eax -> 0,eax,=,1,zf,=
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```
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Memory access is defined by brackets.
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```
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mov eax, [0x80480] -> 0x80480,[],eax,=
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```
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Default size is the destination of the operation. In this case 8bits, aka 1 byte.
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```
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movb $0, 0x80480 -> 0,0x80480,=[1]
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```
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Conditionals are expressed with the '?' char at the beginning of the expression. This checks if the rest of the expression is 0 or not and skips the next expression if doesn't matches. '$' is the prefix for internal vars.
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```
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cmp eax, 123 -> 123,eax,==,$z,zf,=
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jz eax -> zf,?{,eax,eip,=,}
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```
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So.. if you want to run more than one expression under a conditional, you'll have to write it
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```
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zf,?{,eip,esp,=[],eax,eip,=,$r,esp,-=,}
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```
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The whitespace, newlines and other chars are ignored in esil, so the first thing to do is:
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```
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esil = r_str_replace (esil, " ", "", true);
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```
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Syscalls are specially handled by '$' at the beginning of the expression. After that char you have an optional numeric value that specifies the number of syscall. The emulator must handle those expressions and 'simulate' the syscalls. (r_esil_syscall)
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Order of arguments
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==================
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As discussed on irc, current implementation works like this:
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```
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a,b,- b - a
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a,b,/= b /= a
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```
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This approach is more readable, but it's less stack-friendly
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Special instructions
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====================
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NOPs are represented as empty strings. Unknown or invalid instructions
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Syscalls are implemented with the '0x80,$' command. It delegates the execution of the esil vm into a callback that implements the syscall for a specific kernel.
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Traps are implemented with the `<trap>,<code>,$$` command. They are used to throw exceptions like invalid instructions, division by zero, memory read error, etc.
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Quick analysis
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==============
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Here's a list of some quick checks to retrieve information from an esil string. Relevant information will be probably found in the first expression of the list.
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```
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indexOf('[') -> have memory references
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indexOf("=[") -> write in memory
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indexOf("pc,=") -> modifies program counter (branch, jump, call)
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indexOf("sp,=") -> modifies the stack (what if we found sp+= or sp-=?)
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indexOf("=") -> retrieve src and dst
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indexOf(":") -> unknown esil, raw opcode ahead
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indexOf("$") -> accesses internal esil vm flags
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indexOf("$") -> syscall
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indexOf("$$") -> can trap
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indexOf('++') -> has iterator
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indexOf('--') -> count to zero
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indexOf("?{") -> conditional
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indexOf("LOOP") -> is a loop (rep?)
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equalsTo("") -> empty string, means: nop (wrong, if we append pc+=x)
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```
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Common operations:
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* Check dstreg
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* Check srcreg
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* Get destinaion
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* Is jump
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* Is conditional
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* Evulate
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* Is syscall
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CPU Flags
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=========
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CPU flags are usually defined as 1 bit registers in the RReg profile. and sometimes under the 'flg' register type.
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ESIL Flags
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==========
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ESIL VM have an internal state flags that can are read only and can be used to export those values to the underlaying CPU flags. This is because the ESIL vm defines all the flag changes, while the CPUs only update the flags under certain conditions or specific instructions.
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Those internal flags are prefixed by the '$' character.
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```
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z - zero flag, only set if the result of an operation is 0
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b - borrow, this requires to specify from which bit (example: $b4 - checks if borrow from bit 4)
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c - carry, same like above (example: $c7 - checks if carry from bit 7)
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p - parity
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r - regsize ( asm.bits/8 )
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```
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Variables
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=========
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1. No predefined bitness (should be easy to extend them to 128,256 and 512bits, e.g. for MMX, SSE, AVX, Neon)
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2. Infinite number (for SSA-form compatibility)
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3. Register names have no specific syntax. They are just strings
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4. Numbers can be specified in any base supported by RNum (dec, hex, oct, binary ...)
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5. Each ESIL backend should have an associated RReg profile to describe the esil register specs
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Bitarrays
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=========
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What to do with them? What about bit arithmetics if use variables instead of registers?
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Arithmetics
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===========
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1. ADD ("+")
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2. MUL ("*")
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3. SUB ("-")
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4. DIV ("/")
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5. MOD ("%")
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Bit arithmetics
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===============
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1. AND "&"
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2. OR "|"
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3. XOR "^"
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4. SHL "<<"
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5. SHR ">>"
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6. ROL "<<<"
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7. ROR ">>>"
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8. NEG "!"
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Floating point
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==============
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_TODO_
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The x86 REP prefix in ESIL
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==========================
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ESIL specifies that the parsing control-flow commands are in uppercase. Bear in mind that some archs have uppercase register names. The register profile should take care to not reuse any of the following:
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```
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3,SKIP - skip N instructions. used to make relative forward GOTOs
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3,GOTO - goto instruction 3
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LOOP - alias for 0,GOTO
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BREAK - stop evaluating the expression
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STACK - dump stack contents to screen
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CLEAR - clear stack
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```
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Usage example:
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rep cmpsb
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---------
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cx,!,?{,BREAK,},esi,[1],edi,[1],==,?{,BREAK,},esi,++,edi,++,cx,--,LOOP
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Unimplemented/unhandled instructions
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====================================
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Those are expressed with the 'TODO' command. which acts as a 'BREAK', but displaying a warning message describing which instruction is not implemented and will not be emulated.
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For example:
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```
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fmulp ST(1), ST(0) => TODO,fmulp ST(1),ST(0)
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```
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Disassembly example:
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====================
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```
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[0x1000010f8]> e asm.esil=true
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[0x1000010f8]> pd $r @ entry0
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; [0] va=0x1000010f8 pa=0x000010f8 sz=13299 vsz=13299 rwx=-r-x 0.__text
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;-- section.0.__text:
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0x1000010f8 55 8,rsp,-=,rbp,rsp,=[8]
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0x1000010f9 4889e5 rsp,rbp,=
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0x1000010fc 4883c768 104,rdi,+=
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0x100001100 4883c668 104,rsi,+=
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0x100001104 5d rsp,[8],rbp,=,8,rsp,+= ┌─< 0x100001105 e950350000 0x465a,rip,= ;[1]
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│ 0x10000110a 55 8,rsp,-=,rbp,rsp,=[8]
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│ 0x10000110b 4889e5 rsp,rbp,= │ 0x10000110e 488d4668 rsi,104,+,rax,=
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│ 0x100001112 488d7768 rdi,104,+,rsi,=
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│ 0x100001116 4889c7 rax,rdi,=
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│ 0x100001119 5d rsp,[8],rbp,=,8,rsp,+= ┌──< 0x10000111a e93b350000 0x465a,rip,= ;[1]
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││ 0x10000111f 55 8,rsp,-=,rbp,rsp,=[8]
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││ 0x100001120 4889e5 rsp,rbp,=
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││ 0x100001123 488b4f60 rdi,96,+,[8],rcx,=
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││ 0x100001127 4c8b4130 rcx,48,+,[8],r8,= ││ 0x10000112b 488b5660 rsi,96,+,[8],rdx,=
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││ 0x10000112f b801000000 1,eax,= ; 0x00000001
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││ 0x100001134 4c394230 rdx,48,+,[8],r8,==,cz,?=
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┌───< 0x100001138 7f1a sf,of,!,^,zf,!,&,?{,0x1154,rip,=,} ;[2]
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┌────< 0x10000113a 7d07 of,!,sf,^,?{,0x1143,rip,} ;[3]
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││││ 0x10000113c b8ffffffff 0xffffffff,eax,= ; 0xffffffff ┌─────< 0x100001141 eb11 0x1154,rip,= ;[2]
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│└────> 0x100001143 488b4938 rcx,56,+,[8],rcx,=
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│ │││ 0x100001147 48394a38 rdx,56,+,[8],rcx,==,cz,?=
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```
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Radare anal ESIL code example
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==============================
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As an example implementation of ESIL analysis for the AVR family of microcontrollers there is
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a `avr_op` function in `/libr/anal/p/anal_avr.c` which contains information on how the
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instructions are expressed in ESIL and other opcode information such as cycle counts per instruction:
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static int avr_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
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short ofst;
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int d, r, k;
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(...)
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Variables d, r and k refer to "destination", "register" and "(k)onstant", respectively. They
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are used later on by ESIL string formatting function like for instance:
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r_strbuf_setf (&op->esil, "0x%x,r%d,=", k, d);
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Which in this case corresponds to the LDI (LoaD with immediate) instruction in AVR. As an example,
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the above ESIL string template will translate into the following when reversing in radare:
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│ 0x00000080 30e0 0x0,r19,= ; LDI Rd,K. load immediate
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Or in non-ESIL format:
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│ 0x00000080 30e0 ldi r19, 0x00 ; LDI Rd,K. load immediate
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Looking at other architectures which already have mature ESIL support such as x86 can help
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in understanding the syntax and conventions of radare's ESIL.
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Introspection
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=============
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To ease esil parsing we should have a way to express introspection expressions to extract the data we want. For example. We want to get the target address of a jmp.
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The parser for the esil expressions should be implemented in an API to make it possible to extract information by analyzing the expressions easily.
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```
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> ao~esil,opcode
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opcode: jmp 0x10000465a
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esil: 0x10000465a,rip,=
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```
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We need a way to retrieve the numeric value of 'rip'. This is a very simple example, but there will be more complex, like conditional ones and we need expressions to get:
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- opcode type
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- destination of jump
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- condition depends on
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- all regs modified (write)
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- all regs accessed (read)
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API HOOKS
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=========
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It is important for emulation to be able to setup hooks in the parser, so we can extend the parser to implement the analysis without having to write the parser again and again. This is, every time an operation is going to be executed we call a user hook which can be used to determine if rip is changing or if the instruction updates the stack.
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Later, at this level we can split that callback into several ones to have an event based analysis api that may be extended in js like this:
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esil.on('regset', function(){..
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esil.on('syscall', function(){esil.regset('rip'
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we have already them. see hook_flag_read() hook_execute() hook_mem_read() ...
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return true if you want to override the action taken for a callback. for example. avoid mem reads in a region or mem writes to make all memory read only.
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return false or 0 if you want to trace esil expression parsing. aka emulation
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..
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Other operations that require bindings to external functionalities to work. In this case r_ref and r_io. This must be defined when initializing the esil vm.
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* Io Get/Set
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Out ax, 44
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44,ax,:ou
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* Selectors (cs,ds,gs...)
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Mov eax, ds:[ebp+8]
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Ebp,8,+,:ds,eax,=
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