first commit

doc/.gitignore

@@ -0,0 +1 @@
+*.html

doc/Makefile

@@ -0,0 +1,11 @@
+HTML_FILES	= build.html hacking.html licenses.html todo.html tests.html
+
+.PHONY: all
+all: $(HTML_FILES)
+
+%.html: %.asciidoc
+	asciidoc -b html -o $@ $<
+
+.PHONY: clean
+clean:
+	rm -f $(HTML_FILES)

doc/build.asciidoc

@@ -0,0 +1,194 @@
+Snowman: Build Instructions
+===========================
+:toc:
+Yegor Derevenets <yegor.derevenets@gmail.com>
+
+Prerequisites
+-------------
+
+Snowman is written in $$C++$$. So, you will need a $$C++$$ compiler to
+build it. The following compilers are known to work:
+
+    * http://gcc.gnu.org/[GCC] >= 4.6
+    * http://llvm.clang.org[Clang] >= 3.1
+    * http://mingw.org/[MinGW GCC] >= 4.6
+    * http://mingw-w64.sourceforge.net/[MinGW-w64 GCC] >= 4.6
+    * http://www.microsoft.com/[Microsoft Visual Studio] >= 2010
+
+The following software packages must be installed before Snowman can be
+built:
+
+    * http://cmake.org/[CMake] >= 3.7
+    * http://www.boost.org/[Boost] >= 1.49 (headers only)
+    * http://qt-project.org/[Qt] >= 4.7
+
+For installation instructions for the above packages, please refer to
+the respective web pages and/or your operating system's manual.
+
+[NOTE]
+If you want to use Visual Studio 2012 to build applications that would
+run on Windows XP, you have to install Visual Studio 2012 Update 1 or
+later and at <<configuration_step,configuration step>> choose `v110_xp`
+toolset in CMake using `-T` switch (support since CMake 2.8.11, known to
+work with `Visual Studio` generators).
+
+Notes on Building IDA Plug-In
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+1. The following additional package is required to build IDA plug-in:
+
+    * http://www.hex-rays.com/products/ida/[IDA SDK] >= 6.1
+
+2. You must use the same compiler as the one used by IDA and the same
+version of Qt (different patch levels of the same major.minor version
+are binary compatible and work too):
+
+    * IDA 6.1 — MSVC 2010 - 32-bit — Qt 4.7.2.
+    * IDA 6.3 — MSVC 2010 - 32-bit — Qt 4.8.1.
+    * IDA 6.4 — MSVC 2010 - 32-bit — Qt 4.8.1.
+    * IDA 6.5 — MSVC 2010 - 32-bit — Qt 4.8.4.
+    * IDA 6.95 — MSVC 2015 - 32-bit — Qt 5.6.0.
+    * IDA 7.0 — MSVC 2015 - 64-bit — Qt 5.6.0.
+
+3. Qt must be built in namespace `QT`, e.g.:
++
+Qt4, Windows, 32-bit:
++
+------------------------------------------------------------------------
+configure.exe -qtnamespace QT -platform win32-msvc2010 -debug-and-release -opensource -no-qt3support -no-multimedia -no-audio-backend -no-phonon -no-webkit -no-script -no-scripttools -nomake demos -nomake examples && nmake
+------------------------------------------------------------------------
++
+Qt4, Linux, 32-bit:
++
+------------------------------------------------------------------------
+./configure -qtnamespace QT -platform linux-g++-32 -debug-and-release -confirm-license -opensource -no-qt3support -no-multimedia -no-audio-backend -no-phonon -no-webkit -no-script -no-scripttools -nomake demos -nomake examples -prefix $HOME/opt/qt-4.8.4-32 && make && make install
+------------------------------------------------------------------------
++
+Qt5, Windows, 64-bit:
++
+------------------------------------------------------------------------
+configure.exe -qtnamespace QT -platform win32-msvc2015 -debug-and-release -opensource -no-audio-backend -nomake examples -nomake tools && nmake
+------------------------------------------------------------------------
++
+Qt5, Linux, 64-bit:
++
+------------------------------------------------------------------------
+./configure -qtnamespace QT -platform linux-g++-64 -release -confirm-license -opensource -no-audio-backend -nomake examples -prefix $HOME/opt/qt-5.6.1-64 && make && make install
+------------------------------------------------------------------------
+
+4. You must must build decompiler in +Release+ mode, because this is the
+one used by IDA. Otherwise, you will end up linked against debug Qt
+library, while IDA uses the release version. Nothing good comes out of
+this.
+
+Building
+--------
+Snowman is built using a tool called CMake. The build process consists
+of two steps: <<configuration_step,configuration>> and
+<<build_step,build>>.
+
+Setting up the Environment
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+You can help your system to find CMake and CMake to find the compiler
+and required libraries at non-standard locations by setting the
+following environment variables. Alternatively, you may specify these
+locations at <<configuration_step,configuration step>>.
+
+    1. Add CMake and the compiler to your `PATH`.
+    2. Set `BOOST_ROOT` to the path to Boost installation directory (it
+       should contain `boost` subdirectory with header files).
+    3. Set `QTDIR` to the path to the Qt installation directory (it
+       should contain `include` and `lib` subdirectories).
+    4. Set `IDA_SDK_DIR` to the IDA SDK installation directory (it
+       should contain `include` and `lib`) subdirectories.
+
+[[configuration_step]]
+Configuration Step
+~~~~~~~~~~~~~~~~~~
+CMake authors are advocates of out-of-tree builds, so a separate
+directory for compilation results must be created:
+
+-----------------------------------------------------------------
+cd /path/to/decompiler && mkdir build && cd build && cmake ../src
+-----------------------------------------------------------------
+
+You can specify a toolchain using CMake's `-G` switch, e.g.:
+
+    * `-G "Visual Studio 10"` — generate a Visual Studio 2010 solution
+      for building 32-bit application.
+    * `-G "Visual Studio 11 Win64"` — generate a Visual Studio 2012
+      solution for building 64-bit application.
+    * `-G "MinGW Makefiles"` — generate Makefiles for building by
+      MinGW GCC and `mingw32-make`.
+
+You can choose a build mode (`Debug`, `Release`, `RelWithDebInfo`, or
+`MinSizeRel`):
+
+    * `-D CMAKE_BUILD_TYPE=Release`
+
+If you have built Qt in a namespace, do not forget to specify this,
+e.g.:
+
+    * `-D QT_NAMESPACE=QT`
+
+You can choose whether to build the IDA plug-in and which one to build:
+
+    * `-D IDA_PLUGIN_ENABLED=YES` (or `NO`, defaults to `YES` when IDA
+      Pro SDK is found).
+    * `-D IDA_64_BIT_EA_T=YES` (`YES` to build `.p64` version for
+      handling 64-bit code, `NO` for building `.plw` version for
+      handling 32-bit code).
+
+You can choose to build 32-bit code on 64-bit Linux machine:
+
+    * `-D NC_M32=YES`.
+
+You can choose between Qt5 and Qt4:
+
+    * `-D NC_QT5=YES` (`YES` for Qt5, `NO` for Qt4).
+
+You can set the installation prefix:
+
+    * `-D CMAKE_INSTALL_PREFIX=/install/prefix`
+
+[NOTE]
+The build mode specified at the configuration step will not have any
+effect for builds by Visual Studio. There you can choose the build mode
+using `--config` option of CMake directly at <<build_step,build>> and
+<<installation,installation>> steps.
+
+[NOTE]
+On Windows, when choosing release or debug mode, make sure that Qt has
+been built in this mode too. If it was not, the build may fail, or even
+succeed but produce non-working executables.
+
+[[build_step]]
+Build Step
+~~~~~~~~~~
+---------------
+cmake --build .
+---------------
+
+Installation Step
+~~~~~~~~~~~~~~~~~
+--------------------------------
+cmake --build . --target install
+--------------------------------
+
+[NOTE]
+On Windows, when the decompiler is built with Qt4, this command will
+install to the same directory all non-system `.dll` files on which the
+decompiler executables depend, so that the installation can be
+painlessly moved to any other machine and remain workable.
+
+[NOTE]
+When IDA plug-in is enabled, it is the only target which is installed.
+The rationale is that IDA is thread-unsafe, and multithreading is
+disabled in the builds with plug-in enabled. This gives you less chances
+to install single-threaded standalone version of the decompiler (which
+you should not normally want).
+
+//////////////////////////////
+# vim:set et sts=4 sw=4 tw=72:
+//////////////////////////////

doc/hacking.asciidoc

@@ -0,0 +1,86 @@
+Snowman: Use of Programming Language and Libraries
+==================================================
+:toc:
+
+Snowman is written in $$C++$$ and uses the following libraries:
+
+    * http://www.boost.org/[Boost] (header-only libraries),
+    * http://qt-project.org/[Qt] (QtCore, QtGui components).
+
+As a build system we use http://cmake.org/[CMake].
+
+Use of $$C++$$
+--------------
+
+$$C++11$$ Features
+~~~~~~~~~~~~~~~~~~
+We use the following features of C++11:
+
+    * automatic type inference (`auto`);
+    * lambda functions;
+    * rvalue references;
+    * `std::unique_ptr` (supersedes `std::auto_ptr`);
+    * static assertions;
+    * explicit overrides (`<nc/config.h>` defines `override` to an empty string on compilers not supporting this feature);
+
+Wikipedia contains a good survey of these and other $$C++11$$ enhancements:
+
+    * http://en.wikipedia.org/wiki/C++11
+    * http://ru.wikipedia.org/wiki/C++11
+
+Standard Library
+~~~~~~~~~~~~~~~~
+We extensively use the $$C++$$ standard library.
+However, we prefer Qt classes for I/O and `QString` to `std::string`.
+We also prefer the de facto faster unordered containers from Boost to the standard unordered containers.
+
+Exceptions
+~~~~~~~~~~
+The decompiler project uses exceptions for error handling.
+The `nc::Exception` class (see `<nc/common/Exception.h>`) derives from `std::exception` and `boost::exception` and provides Unicode error messages.
+All classes of exceptions inside the project must be derived from `nc::Exception`.
+
+Language Extensions
+~~~~~~~~~~~~~~~~~~~
+The following language extensions are used:
+
+    * `foreach` — a statement for iterating over a range (array, container) defined in `<nc/common/Foreach.h>`.
+      Effectively, it is an alias either for C++11 range-based `for` or (for older compilers) `BOOST_FOREACH`.
+    * Fast implementation of dynamic_cast.
+      See `<nc/common/Subclass.h>` for details.
+    * `std::make_unique` — a function for convenient and exception-safe creation of unique pointers (available since C++14).
+      It is defined in `<nc/common/make_unique.h>`.
+
+Coding Conventions
+------------------
+
+Spacing
+~~~~~~~
+Indentation step is 4 spaces.
+Spaces are always used instead of tabs.
+`clang-format` is your friend.
+
+Naming
+~~~~~~
+Class names are written in `CamelCase` starting with a capital.
+Names of functions, variables are written in `camelCase` starting with a lower-case.
+Names of `enum` constants and macros are written in `ALL_CAPITALS`.
+Names of private class fields `endWithUnderscore_`.
+
+Include Guards
+~~~~~~~~~~~~~~
+The project uses `#pragma once` as include guard.
+It is de facto supported by all modern compilers, more robust, and saves typing, in comparison to classic guards.
+
+All header files in the project must have `#include <nc/config.h>` as its first include.
+
+Pointers and Ownership
+~~~~~~~~~~~~~~~~~~~~~~
+We use `std::make_unique` to create and acquire exclusive ownership over an object on the heap.
+The ownership is transferred by passing the `std::unique_ptr` object.
+
+Doxygen
+~~~~~~~
+We use http://www.doxygen.org/[Doxygen] comments for documenting code.
+
+When describing function's parameters or return values having (plain or smart) pointer types, we use phrases 'Valid pointer to XXX' and 'Pointer to XXX. Can be nullptr'.

doc/tests.asciidoc

@@ -0,0 +1,83 @@
+Snowman: Integration Tests
+==========================
+:toc:
+Yegor Derevenets <yegor.derevenets@gmail.com>
+
+Introduction
+------------
+Snowman has some integration/regression tests. These tests consist in
+running the decompiler against some input files and checking its output
+against the reference output. Currently two kinds of comparisons are
+supported: comparisons against a reference file, using diff, and
+checking whether the output file contains strings matching given regular
+expression, using grep.
+
+Running tests consists of two steps: launching a Python tool that
+generates a Ninja build file containing the test commands, and starting
+Ninja that actually runs the decompiler and checks its output.
+
+Prerequisites
+-------------
+To run the tests, you will need:
+
+    * http://python.org/[Python] >= 2.7
+    * https://martine.github.io/ninja/[Ninja]
+
+Running Tests
+-------------
+1. link:build.asciidoc[Build the decompiler].
+
+2. Clone the tests:
++
+-------------------------------------------------------
+git clone https://github.com/yegord/snowman-tests tests
+-------------------------------------------------------
++
+3. Create the Ninja build file:
++
+---------------------------------------------------------------
+tests/configure.py --decompiler build/nocode/nocode build/tests
+---------------------------------------------------------------
++
+Here we assume that the decompiler was built in the `build` directory.
++
+4. Run the tests:
++
+---------------------------
+ninja -C build/tests -k 100
+---------------------------
++
+Here, `-k 100` specifies that Ninja should stop only after 100 tests
+fail. To run the decompiler only on the tests for which output checks
+are provided, add `check` target name to the above command line. To
+update correct outputs for all the tests, use `update` target.
+
+Adding Tests
+------------
+To add a test, you need to add a test input file to some directory where
+the `configure.py` will find it (read `configure.py` for the list of
+file patterns being looked for). Assuming you have saved the test input
+file as `tests/hand-made/100_my_test.exe`, you can put correct output
+for this test into `tests/hand-made/cookies/100_my_test.exe.stdout`. You
+can specify a list of regular expressions that the standard output must
+match in `tests/hand-made/cookies/100_my_test.exe.stdout.regexp`, one
+expression by line, lines starting starting with `#` are ignored. You
+can add checks on the stderr content in a similar way. You can specify
+the desired exit code of the decompiler in
+`tests/hand-made/cookies/100_my_test.exe.exitCode`. By default, 0 is
+expected.
+
+[NOTE]
+Once you added or updated a test, you will need to rerun `configure.py`
+to update the Ninja build script.
+
+FAQ
+---
+    * *Q:* Why not CTest?
+
+    * *A:* It is really painful to write automatic generation of test
+      cases in CMake language.
+
+//////////////////////////////
+# vim:set et sts=4 sw=4 tw=72:
+//////////////////////////////

doc/todo.asciidoc

@@ -0,0 +1,59 @@
+Snowman: Things to be done
+==========================
+:toc:
+Yegor Derevenets <yegor.derevenets@gmail.com>
+
+Here is a list of things that should be done, sorted by descending priority.
+
+Robustness against Fuzzying
+---------------------------
+Snowman might crash or eat all the memory on some malformed input files, obtained, e.g., via fuzzying.
+See `tests/malformed-elf` for examples.
+One must debug these examples and add additional checks to fix the crashes.
+
+Custom Shortcuts in IDA plugin
+------------------------------
+One should make F3 and Ctrl-F3 changeable to something else.
+
+No-return Functions
+-------------------
+One should compute the set of no-return functions (or basic blocks, or addresses) and use this information when building the control-flow graph of the whole program, namely, chop basic blocks after no-return function calls.
+
+Use Names from IDA
+------------------
+Use names assigned to registers and structs created by the user in IDA in the decompiler's output.
+
+Better support for ARM
+----------------------
+Needed: more descriptions of instructions, description of the calling convention, testing.
+
+x86 Floating-Point Arithmetic
+-----------------------------
+Needed: descriptions of floating-point instructions.
+Idea: implement pushes and pops from/to FPU stack as a sequence of assignments, e.g.: `st(7)=st(6), st(6)=st(5), ..., st(1) = st(0)`.
+Might be a bit much of code, but it is much better than tracking the FPU stack pointer value (that may come different from different branches).
+Will require more clever code generation concerning elimination of unnecessary copies.
+Will require support for floating types in `likec`.
+
+[[SessionSaving]]
+Session Saving
+--------------
+One should be able to store a session and reopen it, with all decompilation results being there.
+
+Session Saving in IDA
+---------------------
+One should restore windows in IDA on reopening the project.
+Depends on <<SessionSaving>>.
+
+Refactoring
+-----------
+Currently, it is unclear how to remember the names given by the user and reuse them in further decompilations.
+Related to this topic: changing calling convention by the user.
+
+Eliminating Term Access Types
+-----------------------------
+Term access types should go: they are not some property of a term.
+
+Pass Manager
+------------
+`MasterAnalyzer` should eventually become a `PassManager`.

modules/FindIDA.cmake

@@ -0,0 +1,143 @@
+# Detect the bitness.
+if(CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT NC_M32)
+    set(prefix "x64")
+else()
+    set(prefix "x86")
+endif()
+
+# Detect the platform.
+set(platform "unknown")
+if(WIN32)
+    set(platform "win")
+endif()
+if(UNIX)
+    set(platform "linux")
+endif()
+if(APPLE)
+    set(platform "mac")
+endif()
+
+# Detect the compiler.
+set(compiler "unknown")
+if(BORLAND)
+    set(compiler "bcc")
+endif()
+
+if(CMAKE_COMPILER_IS_GNUCXX OR ${CMAKE_CXX_COMPILER_ID} MATCHES "Clang")
+    set(compiler "gcc")
+endif()
+
+if(MSVC)
+    set(compiler "vc")
+endif()
+
+set(IDA_64_BIT_EA_T OFF CACHE BOOL "Use 64-bit ea_t. Set this to build 64-bit code capable IDA plugins.")
+
+if(IDA_64_BIT_EA_T)
+    set(suffix "64")
+else()
+    set(suffix "32")
+endif()
+
+if(CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT NC_M32)
+    set(library_dir "lib/${prefix}_${platform}_${compiler}_${suffix}")
+else()
+    set(library_dir "lib/${prefix}_${platform}_${compiler}_${suffix}")
+endif()
+
+#
+# Find IDA SDK.
+#
+find_path(IDA_SDK_DIR
+    NAME ${library_dir}
+    HINTS $ENV{IDA_SDK_DIR}
+    DOC "IDA SDK directory.")
+
+if(IDA_SDK_DIR)
+    set(IDA_INCLUDE_DIR "${IDA_SDK_DIR}/include")
+    set(IDA_LIBRARY_DIR "${IDA_SDK_DIR}/${library_dir}")
+
+    file(READ "${IDA_INCLUDE_DIR}/pro.h" pro_h)
+    string(REGEX MATCH "#define +IDA_SDK_VERSION +([0-9]+)" CMAKE_MATCH_0 ${pro_h})
+    set(IDA_SDK_VERSION ${CMAKE_MATCH_1})
+    unset(pro_h)
+
+    if(MSVC)
+        file(GLOB IDA_LIBRARIES "${IDA_LIBRARY_DIR}/*.lib")
+    elseif(APPLE)
+        file(GLOB IDA_LIBRARIES "${IDA_LIBRARY_DIR}/*.dylib")
+    else()
+        file(GLOB IDA_LIBRARIES "${IDA_LIBRARY_DIR}/*.a")
+    endif()
+
+    set(IDA_DEFINITIONS -D__IDP__)
+    if(WIN32)
+        set(IDA_DEFINITIONS ${IDA_DEFINITIONS} -D__NT__)
+    elseif(APPLE)
+        set(IDA_DEFINITIONS ${IDA_DEFINITIONS} -D__MAC__)
+    else()
+        set(IDA_DEFINITIONS ${IDA_DEFINITIONS} -D__LINUX__)
+    endif()
+    if(CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT NC_M32)
+        set(IDA_DEFINITIONS ${IDA_DEFINITIONS} -D__X64__)
+    endif()
+    if(IDA_64_BIT_EA_T)
+        set(IDA_DEFINITIONS ${IDA_DEFINITIONS} -D__EA64__)
+    endif()
+
+    if(WIN32)
+        if(${IDA_64_BIT_EA_T})
+            if(${IDA_SDK_VERSION} GREATER_EQUAL 700)
+                set(IDA_PLUGIN_EXT "64.dll")
+            else()
+                set(IDA_PLUGIN_EXT ".p64")
+            endif()
+        else()
+            if(${IDA_SDK_VERSION} GREATER_EQUAL 700)
+                set(IDA_PLUGIN_EXT ".dll")
+            else()
+                set(IDA_PLUGIN_EXT ".plw")
+            endif()
+        endif()
+    elseif(APPLE)
+        if(${IDA_64_BIT_EA_T})
+            if(${IDA_SDK_VERSION} GREATER_EQUAL 700)
+                set(IDA_PLUGIN_EXT "64.dylib")
+            else()
+                set(IDA_PLUGIN_EXT ".pmc64")
+            endif()
+        else()
+            if(${IDA_SDK_VERSION} GREATER_EQUAL 700)
+                set(IDA_PLUGIN_EXT ".dylib")
+            else()
+                set(IDA_PLUGIN_EXT ".pmc")
+            endif()
+        endif()
+    else()
+        if(${IDA_64_BIT_EA_T})
+            if(${IDA_SDK_VERSION} GREATER_EQUAL 700)
+                set(IDA_PLUGIN_EXT "64.so")
+            else()
+                set(IDA_PLUGIN_EXT ".plx64")
+            endif()
+        else()
+            if(${IDA_SDK_VERSION} GREATER_EQUAL 700)
+                set(IDA_PLUGIN_EXT ".so")
+            else()
+                set(IDA_PLUGIN_EXT ".plx")
+            endif()
+        endif()
+    endif()
+
+    message(STATUS "Looking for IDA SDK - found version ${IDA_SDK_VERSION} at ${IDA_SDK_DIR}")
+else()
+    message(STATUS "Looking for IDA SDK - not found")
+endif()
+
+unset(prefix)
+unset(platform)
+unset(compiler)
+unset(suffix)
+unset(library_dir)
+
+# vim:set et sts=4 sw=4 nospell:

modules/GetGitRevisionDescription.cmake

@@ -0,0 +1,116 @@
+# - Returns a version string from Git
+#
+# These functions force a re-configure on each git commit so that you can
+# trust the values of the variables in your build system.
+#
+#  get_git_head_revision(<refspecvar> <hashvar> [<additional arguments to git describe> ...])
+#
+# Returns the refspec and sha hash of the current head revision
+#
+#  git_describe(<var> [<additional arguments to git describe> ...])
+#
+# Returns the results of git describe on the source tree, and adjusting
+# the output so that it tests false if an error occurs.
+#
+#  git_get_exact_tag(<var> [<additional arguments to git describe> ...])
+#
+# Returns the results of git describe --exact-match on the source tree,
+# and adjusting the output so that it tests false if there was no exact
+# matching tag.
+#
+# Requires CMake 2.6 or newer (uses the 'function' command)
+#
+# Original Author:
+# 2009-2010 Ryan Pavlik <rpavlik@iastate.edu> <abiryan@ryand.net>
+# http://academic.cleardefinition.com
+# Iowa State University HCI Graduate Program/VRAC
+#
+# Copyright Iowa State University 2009-2010.
+# Distributed under the Boost Software License, Version 1.0.
+# (See accompanying file LICENSE_1_0.txt or copy at
+# http://www.boost.org/LICENSE_1_0.txt)
+
+if(__get_git_revision_description)
+	return()
+endif()
+set(__get_git_revision_description YES)
+
+# We must run the following at "include" time, not at function call time,
+# to find the path to this module rather than the path to a calling list file
+get_filename_component(_gitdescmoddir ${CMAKE_CURRENT_LIST_FILE} PATH)
+
+function(get_git_head_revision _refspecvar _hashvar)
+	set(GIT_PARENT_DIR "${CMAKE_SOURCE_DIR}")
+	set(GIT_DIR "${GIT_PARENT_DIR}/.git")
+	while(NOT EXISTS "${GIT_DIR}")	# .git dir not found, search parent directories
+		set(GIT_PREVIOUS_PARENT "${GIT_PARENT_DIR}")
+		get_filename_component(GIT_PARENT_DIR ${GIT_PARENT_DIR} PATH)
+		if(GIT_PARENT_DIR STREQUAL GIT_PREVIOUS_PARENT)
+			# We have reached the root directory, we are not in git
+			set(${_refspecvar} "GITDIR-NOTFOUND" PARENT_SCOPE)
+			set(${_hashvar} "GITDIR-NOTFOUND" PARENT_SCOPE)
+			return()
+		endif()
+		set(GIT_DIR "${GIT_PARENT_DIR}/.git")
+	endwhile()
+	set(GIT_DATA "${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/git-data")
+	if(NOT EXISTS "${GIT_DATA}")
+		file(MAKE_DIRECTORY "${GIT_DATA}")
+	endif()
+
+	if(NOT EXISTS "${GIT_DIR}/HEAD")
+		return()
+	endif()
+	set(HEAD_FILE "${GIT_DATA}/HEAD")
+	configure_file("${GIT_DIR}/HEAD" "${HEAD_FILE}" COPYONLY)
+
+	configure_file("${_gitdescmoddir}/GetGitRevisionDescription.cmake.in"
+		"${GIT_DATA}/grabRef.cmake"
+		@ONLY)
+	include("${GIT_DATA}/grabRef.cmake")
+
+	set(${_refspecvar} "${HEAD_REF}" PARENT_SCOPE)
+	set(${_hashvar} "${HEAD_HASH}" PARENT_SCOPE)
+endfunction()
+
+function(git_describe _var)
+	if(NOT GIT_FOUND)
+		find_package(Git QUIET)
+	endif()
+	get_git_head_revision(refspec hash)
+	if(NOT GIT_FOUND)
+		set(${_var} "GIT-NOTFOUND" PARENT_SCOPE)
+		return()
+	endif()
+	if(NOT hash)
+		set(${_var} "HEAD-HASH-NOTFOUND" PARENT_SCOPE)
+		return()
+	endif()
+
+	# TODO sanitize
+	#if((${ARGN}" MATCHES "&&") OR
+	#	(ARGN MATCHES "||") OR
+	#	(ARGN MATCHES "\\;"))
+	#	message("Please report the following error to the project!")
+	#	message(FATAL_ERROR "Looks like someone's doing something nefarious with git_describe! Passed arguments ${ARGN}")
+	#endif()
+
+	#message(STATUS "Arguments to execute_process: ${ARGN}")
+
+	execute_process(COMMAND "${GIT_EXECUTABLE}" describe ${hash} ${ARGN}
+		WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+		RESULT_VARIABLE res
+		OUTPUT_VARIABLE out
+		ERROR_QUIET
+		OUTPUT_STRIP_TRAILING_WHITESPACE)
+	if(NOT res EQUAL 0)
+		set(out "${out}-${res}-NOTFOUND")
+	endif()
+
+	set(${_var} "${out}" PARENT_SCOPE)
+endfunction()
+
+function(git_get_exact_tag _var)
+	git_describe(out --exact-match ${ARGN})
+	set(${_var} "${out}" PARENT_SCOPE)
+endfunction()

modules/GetGitRevisionDescription.cmake.in

@@ -0,0 +1,38 @@
+# 
+# Internal file for GetGitRevisionDescription.cmake
+#
+# Requires CMake 2.6 or newer (uses the 'function' command)
+#
+# Original Author:
+# 2009-2010 Ryan Pavlik <rpavlik@iastate.edu> <abiryan@ryand.net>
+# http://academic.cleardefinition.com
+# Iowa State University HCI Graduate Program/VRAC
+#
+# Copyright Iowa State University 2009-2010.
+# Distributed under the Boost Software License, Version 1.0.
+# (See accompanying file LICENSE_1_0.txt or copy at
+# http://www.boost.org/LICENSE_1_0.txt)
+
+set(HEAD_HASH)
+
+file(READ "@HEAD_FILE@" HEAD_CONTENTS LIMIT 1024)
+
+string(STRIP "${HEAD_CONTENTS}" HEAD_CONTENTS)
+if(HEAD_CONTENTS MATCHES "ref")
+	# named branch
+	string(REPLACE "ref: " "" HEAD_REF "${HEAD_CONTENTS}")
+	if(EXISTS "@GIT_DIR@/${HEAD_REF}")
+		configure_file("@GIT_DIR@/${HEAD_REF}" "@GIT_DATA@/head-ref" COPYONLY)
+	elseif(EXISTS "@GIT_DIR@/logs/${HEAD_REF}")
+		configure_file("@GIT_DIR@/logs/${HEAD_REF}" "@GIT_DATA@/head-ref" COPYONLY)
+		set(HEAD_HASH "${HEAD_REF}")
+	endif()
+else()
+	# detached HEAD
+	configure_file("@GIT_DIR@/HEAD" "@GIT_DATA@/head-ref" COPYONLY)
+endif()
+
+if(NOT HEAD_HASH)
+	file(READ "@GIT_DATA@/head-ref" HEAD_HASH LIMIT 1024)
+	string(STRIP "${HEAD_HASH}" HEAD_HASH)
+endif()

src/3rd-party/CMakeLists.txt

@@ -0,0 +1,6 @@
+add_subdirectory(capstone)
+add_subdirectory(libudis86)
+add_subdirectory(libiberty)
+add_subdirectory(undname)
+
+# vim:set et sts=4 sw=4 nospell:

src/3rd-party/capstone/CMakeLists.txt

@@ -0,0 +1,53 @@
+#
+# Ugly. Is there a better way?
+#
+
+set(CAPSTONE_BUILD_DIET OFF CACHE BOOL "")
+set(CAPSTONE_BUILD_STATIC ON CACHE BOOL "")
+set(CAPSTONE_BUILD_SHARED OFF CACHE BOOL "")
+set(CAPSTONE_BUILD_TESTS OFF CACHE BOOL "")
+set(CAPSTONE_ARM_SUPPORT ON CACHE BOOL "")
+set(CAPSTONE_ARM64_SUPPORT OFF CACHE BOOL "")
+set(CAPSTONE_MIPS_SUPPORT OFF CACHE BOOL "")
+set(CAPSTONE_PPC_SUPPORT OFF CACHE BOOL "")
+set(CAPSTONE_SPARC_SUPPORT OFF CACHE BOOL "")
+set(CAPSTONE_SYSZ_SUPPORT OFF CACHE BOOL "")
+set(CAPSTONE_XCORE_SUPPORT OFF CACHE BOOL "")
+set(CAPSTONE_X86_SUPPORT OFF CACHE BOOL "")
+set(CAPSTONE_X86_REDUCE OFF CACHE BOOL "")
+set(CAPSTONE_USE_DEFAULT_ALLOC ON CACHE BOOL "")
+
+mark_as_advanced(
+    CAPSTONE_BUILD_DIET
+    CAPSTONE_BUILD_STATIC
+    CAPSTONE_BUILD_SHARED
+    CAPSTONE_BUILD_TESTS
+    CAPSTONE_ARM_SUPPORT
+    CAPSTONE_ARM64_SUPPORT
+    CAPSTONE_MIPS_SUPPORT
+    CAPSTONE_PPC_SUPPORT
+    CAPSTONE_SPARC_SUPPORT
+    CAPSTONE_SYSZ_SUPPORT
+    CAPSTONE_XCORE_SUPPORT
+    CAPSTONE_X86_SUPPORT
+    CAPSTONE_X86_REDUCE
+    CAPSTONE_USE_DEFAULT_ALLOC
+    CAPSTONE_X86_ATT_DISABLE
+    CAPSTONE_BUILD_STATIC_RUNTIME
+    CAPSTONE_OSXKERNEL_SUPPORT)
+
+if(${CMAKE_CXX_COMPILER_ID} MATCHES "GNU")
+    add_definitions(-Wno-extra -Wno-unused-function -Wno-unknown-pragmas)
+endif()
+
+if(${CMAKE_CXX_COMPILER_ID} MATCHES "Clang")
+    add_definitions(-Wno-extra)
+endif()
+
+if(${MSVC})
+    add_definitions(/wd4244)
+endif()
+
+add_subdirectory(capstone)
+
+# vim:set et sts=4 sw=4 nospell:

src/3rd-party/capstone/capstone.h

@@ -0,0 +1 @@
+#include "capstone/include/capstone.h"

src/3rd-party/capstone/capstone/.gitignore

@@ -0,0 +1,95 @@
+# Object files
+*.o
+*.ko
+
+# Gcc dependency-tracking files
+*.d
+
+# Libraries
+*.lib
+*.a
+
+# Shared objects (inc. Windows DLLs)
+*.dll
+*.so
+*.so.*
+*.dylib
+
+# Executables
+*.exe
+*.out
+*.app
+
+# python
+bindings/python/build/
+bindings/python/capstone.egg-info/
+*.pyc
+
+# java
+bindings/java/capstone.jar
+
+# ocaml
+bindings/ocaml/*.cmi
+bindings/ocaml/*.cmx
+bindings/ocaml/*.cmxa
+bindings/ocaml/*.mli
+bindings/ocaml/test
+bindings/ocaml/test_arm
+bindings/ocaml/test_arm64
+bindings/ocaml/test_mips
+bindings/ocaml/test_x86
+bindings/ocaml/test_detail
+bindings/ocaml/test_ppc
+bindings/ocaml/test_sparc
+bindings/ocaml/test_systemz
+bindings/ocaml/test_xcore
+
+
+# test binaries
+tests/test
+tests/test_detail
+tests/test_iter
+tests/test_arm
+tests/test_arm64
+tests/test_mips
+tests/test_x86
+tests/test_ppc
+tests/test_skipdata
+tests/test_sparc
+tests/test_systemz
+tests/test_xcore
+tests/*.static
+
+# vim tmp file
+*.swp
+*~
+
+capstone.pc
+
+# local files
+_*
+
+# freebsd ports: generated file with "make makesum" command
+packages/freebsd/ports/devel/capstone/distinfo
+
+# VisualStudio
+Debug/
+Release/
+ipch/
+*.sdf
+*.opensdf
+*.suo
+*.user
+
+# Xcode
+xcode/Capstone.xcodeproj/xcuserdata
+xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
+
+# suite/
+test_arm_regression
+test_arm_regression.o
+fuzz_harness
+fuzz_harness.o
+
+
+*.s

src/3rd-party/capstone/capstone/CMakeLists.txt

@@ -0,0 +1,391 @@
+cmake_minimum_required(VERSION 2.6)
+project(capstone)
+
+set(VERSION_MAJOR 3)
+set(VERSION_MINOR 0)
+set(VERSION_PATCH 4)
+
+# to configure the options specify them in in the command line or change them in the cmake UI.
+# Don't edit the makefile!
+option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" OFF)
+option(CAPSTONE_BUILD_STATIC "Build static library" ON)
+option(CAPSTONE_BUILD_SHARED "Build shared library" ON)
+option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
+option(CAPSTONE_BUILD_TESTS "Build tests" ON)
+option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
+
+option(CAPSTONE_ARM_SUPPORT "ARM support" ON)
+option(CAPSTONE_ARM64_SUPPORT "ARM64 support" ON)
+option(CAPSTONE_MIPS_SUPPORT "MIPS support" ON)
+option(CAPSTONE_PPC_SUPPORT "PowerPC support" ON)
+option(CAPSTONE_SPARC_SUPPORT "Sparc support" ON)
+option(CAPSTONE_SYSZ_SUPPORT "SystemZ support" ON)
+option(CAPSTONE_XCORE_SUPPORT "XCore support" ON)
+option(CAPSTONE_X86_SUPPORT "x86 support" ON)
+option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF)
+option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF)
+option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF)
+
+if (CAPSTONE_BUILD_DIET)
+    add_definitions(-DCAPSTONE_DIET)
+endif ()
+
+if (CAPSTONE_USE_DEFAULT_ALLOC)
+    add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM)
+endif ()
+
+if (CAPSTONE_X86_REDUCE)
+    add_definitions(-DCAPSTONE_X86_REDUCE)
+endif ()
+
+if (CAPSTONE_X86_ATT_DISABLE)
+    add_definitions(-DCAPSTONE_X86_ATT_DISABLE)
+endif ()
+
+## sources
+set(SOURCES_ENGINE
+    cs.c
+    MCInst.c
+    MCInstrDesc.c
+    MCRegisterInfo.c
+    SStream.c
+    utils.c
+    )
+
+set(HEADERS_ENGINE
+    include/capstone.h
+    utils.h
+    MCRegisterInfo.h
+    MCInst.h
+    MCInstrDesc.h
+    SStream.h
+    cs_priv.h
+    myinttypes.h
+    include/platform.h
+    )
+
+set(HEADERS_COMMON
+    include/arm64.h
+    include/arm.h
+    include/capstone.h
+    include/mips.h
+    include/ppc.h
+    include/x86.h
+    include/sparc.h
+    include/systemz.h
+    include/xcore.h
+    include/platform.h
+    )
+
+
+set(TEST_SOURCES test.c test_detail.c test_skipdata.c test_iter.c)
+
+## architecture support
+if (CAPSTONE_ARM_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_ARM)
+    set(SOURCES_ARM
+        arch/ARM/ARMDisassembler.c
+        arch/ARM/ARMInstPrinter.c
+        arch/ARM/ARMMapping.c
+        arch/ARM/ARMModule.c
+        )
+    set(HEADERS_ARM
+        arch/ARM/ARMAddressingModes.h
+        arch/ARM/ARMBaseInfo.h
+        arch/ARM/ARMDisassembler.h
+        arch/ARM/ARMGenAsmWriter.inc
+        arch/ARM/ARMGenDisassemblerTables.inc
+        arch/ARM/ARMGenInstrInfo.inc
+        arch/ARM/ARMGenRegisterInfo.inc
+        arch/ARM/ARMGenSubtargetInfo.inc
+        arch/ARM/ARMInstPrinter.h
+        arch/ARM/ARMMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
+endif ()
+
+if (CAPSTONE_ARM64_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_ARM64)
+    set(SOURCES_ARM64
+        arch/AArch64/AArch64BaseInfo.c
+        arch/AArch64/AArch64Disassembler.c
+        arch/AArch64/AArch64InstPrinter.c
+        arch/AArch64/AArch64Mapping.c
+        arch/AArch64/AArch64Module.c
+        )
+    set(HEADERS_ARM64
+        arch/AArch64/AArch64AddressingModes.h
+        arch/AArch64/AArch64BaseInfo.h
+        arch/AArch64/AArch64Disassembler.h
+        arch/AArch64/AArch64GenAsmWriter.inc
+        arch/AArch64/AArch64GenDisassemblerTables.inc
+        arch/AArch64/AArch64GenInstrInfo.inc
+        arch/AArch64/AArch64GenRegisterInfo.inc
+        arch/AArch64/AArch64GenSubtargetInfo.inc
+        arch/AArch64/AArch64InstPrinter.h
+        arch/AArch64/AArch64Mapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
+endif ()
+
+if (CAPSTONE_MIPS_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_MIPS)
+    set(SOURCES_MIPS
+        arch/Mips/MipsDisassembler.c
+        arch/Mips/MipsInstPrinter.c
+        arch/Mips/MipsMapping.c
+        arch/Mips/MipsModule.c
+        )
+    set(HEADERS_MIPS
+        arch/Mips/MipsDisassembler.h
+        arch/Mips/MipsGenAsmWriter.inc
+        arch/Mips/MipsGenDisassemblerTables.inc
+        arch/Mips/MipsGenInstrInfo.inc
+        arch/Mips/MipsGenRegisterInfo.inc
+        arch/Mips/MipsGenSubtargetInfo.inc
+        arch/Mips/MipsInstPrinter.h
+        arch/Mips/MipsMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_mips.c)
+endif ()
+
+if (CAPSTONE_PPC_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_POWERPC)
+    set(SOURCES_PPC
+        arch/PowerPC/PPCDisassembler.c
+        arch/PowerPC/PPCInstPrinter.c
+        arch/PowerPC/PPCMapping.c
+        arch/PowerPC/PPCModule.c
+        )
+    set(HEADERS_PPC
+        arch/PowerPC/PPCDisassembler.h
+        arch/PowerPC/PPCGenAsmWriter.inc
+        arch/PowerPC/PPCGenDisassemblerTables.inc
+        arch/PowerPC/PPCGenInstrInfo.inc
+        arch/PowerPC/PPCGenRegisterInfo.inc
+        arch/PowerPC/PPCGenSubtargetInfo.inc
+        arch/PowerPC/PPCInstPrinter.h
+        arch/PowerPC/PPCMapping.h
+        arch/PowerPC/PPCPredicates.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
+endif ()
+
+if (CAPSTONE_X86_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_X86)
+    set(SOURCES_X86
+        arch/X86/X86Disassembler.c
+        arch/X86/X86DisassemblerDecoder.c
+        arch/X86/X86IntelInstPrinter.c
+        arch/X86/X86Mapping.c
+        arch/X86/X86Module.c
+        )
+    set(HEADERS_X86
+        arch/X86/X86BaseInfo.h
+        arch/X86/X86Disassembler.h
+        arch/X86/X86DisassemblerDecoder.h
+        arch/X86/X86DisassemblerDecoderCommon.h
+        arch/X86/X86GenAsmWriter.inc
+        arch/X86/X86GenAsmWriter1.inc
+        arch/X86/X86GenAsmWriter1_reduce.inc
+        arch/X86/X86GenAsmWriter_reduce.inc
+        arch/X86/X86GenDisassemblerTables.inc
+        arch/X86/X86GenDisassemblerTables_reduce.inc
+        arch/X86/X86GenInstrInfo.inc
+        arch/X86/X86GenInstrInfo_reduce.inc
+        arch/X86/X86GenRegisterInfo.inc
+        arch/X86/X86InstPrinter.h
+        arch/X86/X86Mapping.h
+        )
+    if (NOT CAPSTONE_BUILD_DIET)
+        set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
+    endif ()
+    set(TEST_SOURCES ${TEST_SOURCES} test_x86.c)
+endif ()
+
+if (CAPSTONE_SPARC_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_SPARC)
+    set(SOURCES_SPARC
+        arch/Sparc/SparcDisassembler.c
+        arch/Sparc/SparcInstPrinter.c
+        arch/Sparc/SparcMapping.c
+        arch/Sparc/SparcModule.c
+        )
+    set(HEADERS_SPARC
+        arch/Sparc/Sparc.h
+        arch/Sparc/SparcDisassembler.h
+        arch/Sparc/SparcGenAsmWriter.inc
+        arch/Sparc/SparcGenDisassemblerTables.inc
+        arch/Sparc/SparcGenInstrInfo.inc
+        arch/Sparc/SparcGenRegisterInfo.inc
+        arch/Sparc/SparcGenSubtargetInfo.inc
+        arch/Sparc/SparcInstPrinter.h
+        arch/Sparc/SparcMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c)
+endif ()
+
+if (CAPSTONE_SYSZ_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_SYSZ)
+    set(SOURCES_SYSZ
+        arch/SystemZ/SystemZDisassembler.c
+        arch/SystemZ/SystemZInstPrinter.c
+        arch/SystemZ/SystemZMapping.c
+        arch/SystemZ/SystemZModule.c
+        arch/SystemZ/SystemZMCTargetDesc.c
+        )
+    set(HEADERS_SYSZ
+        arch/SystemZ/SystemZDisassembler.h
+        arch/SystemZ/SystemZGenAsmWriter.inc
+        arch/SystemZ/SystemZGenDisassemblerTables.inc
+        arch/SystemZ/SystemZGenInstrInfo.inc
+        arch/SystemZ/SystemZGenRegisterInfo.inc
+        arch/SystemZ/SystemZGenSubtargetInfo.inc
+        arch/SystemZ/SystemZInstPrinter.h
+        arch/SystemZ/SystemZMCTargetDesc.h
+        arch/SystemZ/SystemZMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c)
+endif ()
+
+if (CAPSTONE_XCORE_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_XCORE)
+    set(SOURCES_XCORE
+        arch/XCore/XCoreDisassembler.c
+        arch/XCore/XCoreInstPrinter.c
+        arch/XCore/XCoreMapping.c
+        arch/XCore/XCoreModule.c
+        )
+    set(HEADERS_XCORE
+        arch/XCore/XCoreDisassembler.h
+        arch/XCore/XCoreGenAsmWriter.inc
+        arch/XCore/XCoreGenDisassemblerTables.inc
+        arch/XCore/XCoreGenInstrInfo.inc
+        arch/XCore/XCoreGenRegisterInfo.inc
+        arch/XCore/XCoreInstPrinter.h
+        arch/XCore/XCoreMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c)
+endif ()
+
+if (CAPSTONE_OSXKERNEL_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
+endif ()
+
+set(ALL_SOURCES
+    ${SOURCES_ENGINE}
+    ${SOURCES_ARM}
+    ${SOURCES_ARM64}
+    ${SOURCES_MIPS}
+    ${SOURCES_PPC}
+    ${SOURCES_X86}
+    ${SOURCES_SPARC}
+    ${SOURCES_SYSZ}
+    ${SOURCES_XCORE}
+    )
+
+set(ALL_HEADERS
+    ${HEADERS_COMMON}
+    ${HEADERS_ENGINE}
+    ${HEADERS_ARM}
+    ${HEADERS_ARM64}
+    ${HEADERS_MIPS}
+    ${HEADERS_PPC}
+    ${HEADERS_X86}
+    ${HEADERS_SPARC}
+    ${HEADERS_SYSZ}
+    ${HEADERS_XCORE}
+    )
+
+include_directories("${PROJECT_SOURCE_DIR}/include")
+
+## properties
+# version info
+set_property(GLOBAL PROPERTY VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH})
+set_property(GLOBAL PROPERTY SOVERSION SOVERSION ${VERSION_MAJOR})
+
+## targets
+if (CAPSTONE_BUILD_STATIC)
+    add_library(capstone-static STATIC ${ALL_SOURCES} ${ALL_HEADERS})
+    set_property(TARGET capstone-static PROPERTY OUTPUT_NAME capstone)
+    set(default-target capstone-static)
+endif ()
+
+# Force static runtime libraries
+if (CAPSTONE_BUILD_STATIC_RUNTIME)
+    FOREACH(flag
+        CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO
+        CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT
+        CMAKE_CXX_FLAGS_RELEASE  CMAKE_CXX_FLAGS_RELWITHDEBINFO
+        CMAKE_CXX_FLAGS_DEBUG  CMAKE_CXX_FLAGS_DEBUG_INIT)
+        STRING(REPLACE "/MD"  "/MT" "${flag}" "${${flag}}")
+        SET("${flag}" "${${flag}} /EHsc")
+    ENDFOREACH()
+endif ()
+
+if (CAPSTONE_BUILD_SHARED)
+    add_library(capstone-shared SHARED ${ALL_SOURCES} ${ALL_HEADERS})
+    set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone)
+    set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED)
+
+    if (MSVC)
+        set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib)
+    endif ()
+
+    if(NOT DEFINED default-target)      # honor `capstone-static` for tests first.
+        set(default-target capstone-shared)
+        add_definitions(-DCAPSTONE_SHARED)
+    endif ()
+endif ()
+
+if (CAPSTONE_BUILD_TESTS)
+    foreach (TSRC ${TEST_SOURCES})
+        STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC})
+        add_executable(${TBIN} "tests/${TSRC}")
+        target_link_libraries(${TBIN} ${default-target})
+    endforeach ()
+    if (CAPSTONE_ARM_SUPPORT)
+        set(ARM_REGRESS_TEST test_arm_regression.c)
+        STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST})
+        add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}")
+        target_link_libraries(${ARM_REGRESS_BIN} ${default-target})
+    endif()
+endif ()
+
+source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
+source_group("Source\\ARM" FILES ${SOURCES_ARM})
+source_group("Source\\ARM64" FILES ${SOURCES_ARM64})
+source_group("Source\\Mips" FILES ${SOURCES_MIPS})
+source_group("Source\\PowerPC" FILES ${SOURCES_PPC})
+source_group("Source\\Sparc" FILES ${SOURCES_SPARC})
+source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ})
+source_group("Source\\X86" FILES ${SOURCES_X86})
+source_group("Source\\XCore" FILES ${SOURCES_XCORE})
+
+source_group("Include\\Common" FILES ${HEADERS_COMMON})
+source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
+source_group("Include\\ARM" FILES ${HEADERS_ARM})
+source_group("Include\\ARM64" FILES ${HEADERS_ARM64})
+source_group("Include\\Mips" FILES ${HEADERS_MIPS})
+source_group("Include\\PowerPC" FILES ${HEADERS_PPC})
+source_group("Include\\Sparc" FILES ${HEADERS_SPARC})
+source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ})
+source_group("Include\\X86" FILES ${HEADERS_X86})
+source_group("Include\\XCore" FILES ${HEADERS_XCORE})
+
+## installation
+install(FILES ${HEADERS_COMMON} DESTINATION include/capstone)
+
+if (CAPSTONE_BUILD_STATIC)
+    install(TARGETS capstone-static
+            RUNTIME DESTINATION bin
+            LIBRARY DESTINATION lib
+            ARCHIVE DESTINATION lib)
+endif ()
+
+if (CAPSTONE_BUILD_SHARED)
+    install(TARGETS capstone-shared
+            RUNTIME DESTINATION bin
+            LIBRARY DESTINATION lib
+            ARCHIVE DESTINATION lib)
+endif ()

src/3rd-party/capstone/capstone/COMPILE.TXT

@@ -0,0 +1,193 @@
+This documentation explains how to compile, install & run Capstone on MacOSX,
+Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows.
+
+To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT.
+
+To compile using CMake, see COMPILE_CMAKE.TXT.
+
+To compile using XCode on MacOSX, see xcode/README.md.
+
+                        *-*-*-*-*-*
+
+Capstone requires no prerequisite packages, so it is easy to compile & install.
+
+
+
+(0) Tailor Capstone to your need.
+
+  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
+  SystemZ, XCore & X86), if you just need several selected archs, choose which
+  ones you want to compile in by editing "config.mk" before going to next steps.
+
+  By default, all 8 architectures are compiled.
+
+  The other way of customize Capstone without having to edit config.mk is to
+  pass the desired options on the commandline to ./make.sh. Currently,
+  Capstone supports 5 options, as followings.
+
+  - CAPSTONE_ARCHS: specify list of architectures to compiled in.
+  - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management.
+  - CAPSTONE_DIET: use this to make the output binaries more compact.
+  - CAPSTONE_X86_REDUCE: another option to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86.
+  - CAPSTONE_STATIC: build static library.
+  - CAPSTONE_SHARED: build dynamic (shared) library.
+
+  By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE
+  modes are disable, and builds all the static & shared libraries.
+
+  To avoid editing config.mk for these customization, we can pass their values to
+  make.sh, as followings.
+
+  $ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh
+
+  NOTE: on commandline, put these values in front of ./make.sh, not after it.
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) Compile from source
+
+  On *nix (such as MacOSX, Linux, *BSD, Solaris):
+
+  - To compile for current platform, run:
+
+		$ ./make.sh
+
+  - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary:
+
+		$ ./make.sh nix32
+
+
+
+(2) Install Capstone on *nix
+
+  To install Capstone, run:
+
+	$ sudo ./make.sh install
+
+	For FreeBSD/OpenBSD, where sudo is unavailable, run:
+
+		$ su; ./make.sh install
+
+  Users are then required to enter root password to copy Capstone into machine
+  system directories.
+
+  Afterwards, run ./tests/test* to see the tests disassembling sample code.
+
+
+  NOTE: The core framework installed by "./make.sh install" consist of
+  following files:
+
+	/usr/include/capstone/capstone.h
+	/usr/include/capstone/x86.h
+	/usr/include/capstone/arm.h
+	/usr/include/capstone/arm64.h
+	/usr/include/capstone/mips.h
+	/usr/include/capstone/ppc.h
+	/usr/include/capstone/sparc.h
+	/usr/include/capstone/systemz.h
+	/usr/include/capstone/xcore.h
+	/usr/include/capstone/platform.h
+	/usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
+	/usr/lib/libcapstone.a
+
+
+
+(3) Cross-compile for Windows from *nix
+
+  To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64
+  for 64-bit binaries) are required.
+
+	- To cross-compile Windows 32-bit binary, simply run:
+
+		$ ./make.sh cross-win32
+
+	- To cross-compile Windows 64-bit binary, run:
+
+		$ ./make.sh cross-win64
+
+  Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
+  be used on Windows machine.
+
+
+
+(4) Cross-compile for iOS from Mac OSX.
+
+  To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required. 
+
+	- To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run:
+		$ ./make.sh ios_armv7
+
+	- To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run:
+		$ ./make.sh ios_armv7s
+
+	- To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run:
+		$ ./make.sh ios_arm64
+
+	- To cross-compile for all iDevices (armv7 + armv7s + arm64), run:
+		$ ./make.sh ios
+
+  Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then
+  be used on iOS devices.
+
+
+
+(5) Cross-compile for Android
+
+  To cross-compile for Android (smartphone/tablet), Android NDK is required.
+  NOTE: Only ARM and ARM64 are currently supported.
+
+       $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
+       or
+       $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64
+
+  Resulted files libcapstone.so, libcapstone.a & tests/test* can then
+  be used on Android devices.
+
+
+
+(6) Compile on Windows with Cygwin
+
+  To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run:
+
+        - To compile Windows 32-bit binary under Cygwin, run:
+
+                $ ./make.sh cygwin-mingw32
+
+        - To compile Windows 64-bit binary under Cygwin, run:
+
+                $ ./make.sh cygwin-mingw64
+
+  Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
+  be used on Windows machine.
+
+
+
+(7) By default, "cc" (default C compiler on the system) is used as compiler.
+
+	- To use "clang" compiler instead, run the command below:
+
+		$ ./make.sh clang
+
+	- To use "gcc" compiler instead, run:
+
+		$ ./make.sh gcc
+
+
+
+(8) To uninstall Capstone, run the command below:
+
+		$ sudo ./make.sh uninstall
+
+
+
+(9) Language bindings
+
+  So far, Python, Ocaml & Java are supported by bindings in the main code.
+  Look for the bindings under directory bindings/, and refer to README file
+  of corresponding languages.
+
+  Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to
+  these can be found at address http://capstone-engine.org/download.html

src/3rd-party/capstone/capstone/COMPILE_CMAKE.TXT

@@ -0,0 +1,81 @@
+This documentation explains how to compile Capstone with CMake, focus on
+using Microsoft Visual C as the compiler.
+
+To compile Capstone on *nix, see COMPILE.TXT.
+
+To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT.
+
+                        *-*-*-*-*-*
+
+This documentation requires CMake & Windows SDK or MS Visual Studio installed on
+your machine.
+
+Get CMake for free from http://www.cmake.org.
+
+
+
+(0) Tailor Capstone to your need.
+
+  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
+  SystemZ, X86 & XCore), if you just need several selected archs, run "cmake"
+  with the unwanted archs disabled (set to 0) as followings.
+
+  - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
+  - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64.
+  - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
+  - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC.
+  - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
+  - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
+  - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
+  - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
+
+  By default, all 8 architectures are compiled in.
+
+
+  Besides, Capstone also allows some more customization via following macros.
+
+  - CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management.
+  - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact.
+  - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86.
+
+  By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
+  modes are disabled. To use your own memory allocations, turn ON both DIET &
+  X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1
+
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) CMake allows you to generate different generators to build Capstone. Below is
+    some examples on how to build Capstone on Windows with CMake.
+
+
+  (*) To build Capstone using Nmake of Windows SDK, do:
+
+      mkdir build
+      cd build
+      cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" ..
+      nmake
+
+  After this, find the samples test*.exe, libcapstone_static.lib & libcapstone.dll
+  in the same directory.
+
+
+
+  (*) To build Capstone using Visual Studio, choose the generator accordingly to the
+  version of Visual Studio on your machine. For example, with Visual Studio 2013, do:
+
+      mkdir build
+      cd build
+      cmake -G "Visual Studio 12" ..
+
+  After this, find capstone.sln in the same directory. Open it with Visual Studio
+  and build the solution including libraries & all test as usual.
+
+
+
+(2) You can make sure the prior steps successfully worked by launching one of the
+  testing binary (test*.exe).
+

src/3rd-party/capstone/capstone/COMPILE_MSVC.TXT

@@ -0,0 +1,66 @@
+This documentation explains how to compile Capstone on Windows using
+Microsoft Visual Studio version 2010 or newer.
+
+To compile Capstone on *nix, see COMPILE.TXT
+
+To compile Capstone with CMake, see COMPILE_CMAKE.TXT
+
+                        *-*-*-*-*-*
+
+Capstone requires no prerequisite packages, so it is easy to compile & install.
+Open the Visual Studio solution "msvc/capstone.sln" and follow the instructions
+below.
+
+NOTE: This requires Visual Studio 2010 or newer versions.
+
+
+(0) Tailor Capstone to your need.
+
+  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
+  SystemZ, X86 & XCore), if you just need several selected archs, choose the ones
+  you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
+  then directly editing the projects "capstone_static" & "capstone_dll" for static
+  and dynamic libraries, respectively. This must be done before going to the
+  next steps.
+
+  In VisualStudio interface, modify the preprocessor definitions via
+  "Project Properties" -> "Configuration Propertis" -> "C/C++" -> "Preprocessor"
+  to customize Capstone library, as followings.
+
+  - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
+  - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support.
+  - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
+  - CAPSTONE_HAS_PPC: support PPC. Delete this to remove PPC support.
+  - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support.
+  - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
+  - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
+  - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
+
+  By default, all 8 architectures are compiled in.
+
+
+  Besides, Capstone also allows some more customization via following macros.
+
+  - CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management.
+  - CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact.
+  - CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable
+    AT&T syntax on x86.
+
+  By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
+  modes are disable.
+
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) Compile from source on Windows with Visual Studio
+
+  - Choose the configuration and the platform you want: Release/Debug & Win32/Win64.
+  - Build only the libraries, or the libraries along with all the tests.
+
+
+
+(2) You can make sure the prior steps successfully worked by launching one of the
+  testing binary (test*.exe).

src/3rd-party/capstone/capstone/CREDITS.TXT

@@ -0,0 +1,59 @@
+This file credits all the contributors of the Capstone engine project.
+
+Key developers
+==============
+1. Nguyen Anh Quynh <aquynh -at- gmail.com>
+	- Core engine
+	- Bindings: Python, Ruby, OCaml, Java, C#
+
+2. Tan Sheng Di <shengdi -at- coseinc.com>
+	- Bindings: Ruby
+
+3. Ben Nagy <ben -at- coseinc.com>
+	- Bindings: Ruby, Go
+
+4. Dang Hoang Vu <dang.hvu -at- gmail.com>
+	- Bindings: Java
+
+
+Beta testers (in random order)
+==============================
+Pancake
+Van Hauser
+FX of Phenoelit
+The Grugq, The Grugq   <-- our hero for submitting the first ever patch!
+Isaac Dawson, Veracode Inc
+Patroklos Argyroudis, Census Inc. (http://census-labs.com)
+Attila Suszter
+Le Dinh Long
+Nicolas Ruff
+Gunther
+Alex Ionescu, Winsider Seminars & Solutions Inc.
+Snare
+Daniel Godas-Lopez
+Joshua J. Drake
+Edgar Barbosa
+Ralf-Philipp Weinmann
+Hugo Fortier
+Joxean Koret
+Bruce Dang
+Andrew Dunham
+
+
+Contributors (in no particular order)
+=====================================
+(Please let us know if you want to have your name here)
+
+Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
+Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
+Daniel Pistelli: Cmake support.
+Peter Hlavaty: integrate Capstone for Windows kernel drivers.
+Guillaume Jeanne: Ocaml binding.
+Martin Tofall, Obsidium Software: Optimize X86 performance & size.
+David Martínez Moreno & Hilko Bengen: Debian package.
+Félix Cloutier: Xcode project.
+Benoit Lecocq: OpenBSD package.
+Christophe Avoinne (Hlide): Improve memory management for better performance.
+Michael Cohen & Nguyen Tan Cong: Python module installer.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.

src/3rd-party/capstone/capstone/ChangeLog

@@ -0,0 +1,432 @@
+This file details the changelog of Capstone.
+
+---------------------------------
+Version 3.0.4: July 15th, 2015
+
+
+[ Library ]
+
+- Improve cross-compile for Android using Android NDK.
+- Support cross-compile for AArch64 Android (with Linux GCC).
+- Removed osxkernel_inttypes.h that is incompatible with BSD license.
+- Make it possible to compile with CC having a space inside (like "ccache gcc").
+
+
+[ X86 ]
+
+- Fix a null pointer dereference bug on handling code with special prefixes.
+- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
+- Print immediate operand in positive form in some algorithm instructions.
+- Properly decode some SSE instructions.
+
+
+[ PowerPC ]
+
+- Fixed a memory corruption bug.
+- Fixed a memory corruption bug for the engine built in DIET mode.
+
+
+[ Mips ]
+
+- Fixed instruction ID of SUBU instruction.
+- Fixed a memory corruption bug.
+
+
+[ Arm ]
+
+- Fixed a memory corruption bug on IT instruction.
+
+
+[ XCore ]
+
+- Fixed a memory corruption bug when instruction has a memory operand.
+
+
+[ Python ]
+
+- Support Virtualenv.
+- setup.py supports option --user if not in a virtualenv to allow for local usage.
+- Properly handle the destruction of Cs object in the case the shared library
+  was already unloaded.
+
+---------------------------------
+Version 3.0.3: May 08th, 2015
+
+
+[ Library ]
+
+- Support to embed into Mac OS X kernel extensions.
+- Now it is possible to compile Capstone with older C compilers, such as
+  GCC 4.8 on Ubuntu 12.04.
+- Add "test_iter" to MSVC project.
+
+
+[ X86 ]
+
+- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
+  $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
+  "rcll %edx").
+- CMPXCHG16B is a valid instruction with LOCK prefix.
+- Fixed a segfault on the input of 0xF3.
+
+
+[ Arm ]
+
+- BLX instruction modifies PC & LR registers.
+
+
+[ Sparc ]
+
+- Improved displacement decoding for sparc banching instructions.
+
+
+[ Python binding ]
+
+- Fix for Cython so it can properly initialize.
+- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
+- Properly support compile with Cygwin & install binding (setup.py).
+
+---------------------------------
+Version 3.0.2: March 11th, 2015
+
+
+[ Library ]
+
+- On *nix, only export symbols that are part of the API (instead of all
+  the internal symbols).
+
+
+[ X86 ]
+
+- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
+- Fix implicit registers read/written & instruction groups of some instructions.
+- More flexible on the order of prefixes, so better handle some tricky
+  instructions.
+- REPNE prefix can go with STOS & MOVS instructions.
+- Fix a compilation bug for X86_REDUCE mode.
+- Fix operand size of instructions with operand PTR []
+
+
+[ Arm ]
+
+- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
+- Fix a bug on handling the If-Then block.
+
+
+[ Mips ]
+
+- Sanity check for the input size for MIPS64 mode.
+
+
+[ MSVC ]
+
+- Compile capstone.dll with static runtime MSVCR built in.
+
+
+[ Python binding ]
+
+- Fix a compiling issue of Cython binding with gcc 4.9.
+
+---------------------------------
+Version 3.0.1: February 03rd, 2015
+
+[ X86 ]
+
+- Properly handle LOCK, REP, REPE & REPNE prefixes.
+- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
+- Print LJUMP/LCALL without * as prefix for Intel syntax.
+- Handle REX prefix properly for segment/MMX related instructions (x86_64).
+- Instruction with length > 15 is consider invalid.
+- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
+  FSTP, FSTPNCE, NOP.
+- Handle some tricky code for some X86_64 instructions with REX prefix.
+- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
+- MOV32ms & MOV32sm should reference word rather than dword.
+
+
+[ Arm64 ]
+
+- BL & BLR instructions do not read SP register.
+- Print absolute (rather than relative) address for instructions B, BL,
+  CBNZ, ADR.
+
+
+[ Arm ]
+
+- Instructions ADC & SBC do not update flags.
+- BL & BLX do not read SP, but PC register.
+- Alias LDR instruction with operands [sp], 4 to POP.
+- Print immediate operand of MVN instruction in positive hexadecimal form.
+
+
+[ PowerPC ]
+
+- Fix some compilation bugs when DIET mode is enable.
+- Populate SLWI/SRWI instruction details with SH operand.
+
+
+[ Python binding ]
+
+- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
+- Fixed a memory leak for Cython disasm functions when we immaturely quit
+  the enumeration of disassembled instructions.
+- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
+  at the same time.
+- Fix a memory leaking bug when when we stop enumeration over the disassembled
+  instructions prematurely.
+- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
+
+---------------------------------
+Version 3.0: November 19th, 2014
+
+[ API ]
+
+- New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials.
+- Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but
+  marked obsolete to be removed in future)
+- Support SKIPDATA mode, so Capstone can jump over unknown data and keep going
+  from the next legitimate instruction. See docs/README for tutorials.
+- More details provided in cs_detail struct for all architectures.
+- API version was bumped to 3.0.
+
+
+[ Bindings ]
+
+- Python binding supports Python3 (besides Python2).
+- Support Ocaml binding.
+- Java: add close() method to be used to deinitialize a Capstone object when
+  no longer use it.
+
+
+[ Architectures ]
+
+- New architectures: Sparc, SystemZ & XCore.
+- Important bugfixes for Arm, Arm64, Mips, PowerPC & X86.
+- Support more instructions for Arm, Arm64, Mips, PowerPC & X86.
+- Always expose absolute addresses rather than relative addresses (Arm, Arm64,
+  Mips, PPC, Sparc, X86).
+- Use common instruction operand types REG, IMM, MEM & FP across all
+  architectures (to enable cross-architecture analysis).
+- Use common instruction group types across all architectures (to enable
+  cross-architecture analysis).
+
+
+[ X86 ]
+
+- X86 engine is mature & handles all the malware tricks (that we are aware of).
+- Added a lot of new instructions (such as AVX512, 3DNow, etc).
+- Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE.
+- Print immediate in positive form & hexadecimal for AND/OR/XOR instructions.
+- More friendly disassembly for JMP16i (in the form segment:offset)
+
+
+[ Mips ]
+
+- Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) &
+  MipsGP64 (CS_MODE_MIPSGP64).
+- Removed the ABI-only mode CS_MODE_N64.
+- New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 &
+  CS_MODE_64).
+
+
+[ ARM ]
+
+- Support new mode CS_MODE_V8 for Armv8 A32 encodings.
+- Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions
+
+
+[ ARM64 ]
+
+- Print immediate in hexadecimal for AND/ORR/EOR/TST instructions.
+
+
+[ PowerPC ]
+
+- Do not print a dot in front of absolute address.
+
+
+[ Other features ]
+
+- Support for Microsoft Visual Studio (so enable Windows native compilation).
+- Support CMake compilation.
+- Cross-compile for Android.
+- Build libraries/tests using XCode project
+- Much faster, while consuming less memory for all architectures.
+
+---------------------------------
+Version 2.1.2: April 3rd, 2014
+
+This is a stable release to fix some bugs deep in the core. There is no update
+to any architectures or bindings, so bindings version 2.1 can be used with this
+version 2.1.2 just fine.
+
+[ Core changes]
+
+- Support cross-compilation for all iDevices (iPhone/iPad/iPod).
+- X86: do not print memory offset in negative form.
+- Fix a bug in X86 when Capstone cannot handle short instruction.
+- Print negative number above -9 without prefix 0x (arm64, mips, arm).
+- Correct the SONAME setup for library versioning (Linux, *BSD, Solaris).
+- Set library versioning for dylib of OSX.
+
+---------------------------------
+Version 2.1.1: March 13th, 2014
+
+This is a stable release to fix some bugs deep in the core. There is no update
+to any architectures or bindings, so bindings version 2.1 can be used with this
+version 2.1.1 just fine.
+
+[ Core changes]
+
+- Fix a buffer overflow bug in Thumb mode (ARM). Some special input can
+  trigger this flaw.
+- Fix a crash issue when embedding Capstone into OSX kernel. This should
+  also enable Capstone to be embedded into other systems with limited stack
+  memory size such as Linux kernel or some firmwares.
+- Use a proper SONAME for library versioning (Linux).
+
+---------------------------------
+Version 2.1: March 5th, 2014
+
+[ API changes ]
+
+- API version has been bumped to 2.1.
+- Change prototype of cs_close() to be able to invalidate closed handle.
+  See http://capstone-engine.org/version_2.1_API.html for more information.
+- Extend cs_support() to handle more query types, not only about supported
+  architectures. This change is backward compatible, however, so existent code
+  do not need to be modified to support this.
+- New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of
+  the engine.
+- New error code CS_ERR_DIET to report errors about newly added diet mode.
+- New error code CS_ERR_VERSION to report issue of incompatible versions between
+  bindings & core engine.
+
+
+[ Core changes ]
+
+- On memory usage, Capstone uses about 40% less memory, while still faster
+  than version 2.0.
+- All architectures are much smaller: binaries size reduce at least 30%.
+  Especially, X86-only binary reduces from 1.9MB to just 720KB.
+- Support "diet" mode, in which engine size is further reduced (by around 40%)
+  for embedding purpose. The price to pay is that we have to sacrifice some
+  non-critical data fields. See http://capstone-engine.org/diet.html for more
+  details.
+
+
+[ Architectures ]
+
+- Update all 5 architectures to fix bugs.
+- PowerPC:
+	- New instructions: FMR & MSYNC.
+- Mips:
+	- New instruction: DLSA
+- X86:
+	- Properly handle AVX-512 instructions.
+	- New instructions: PSETPM, SALC, INT1, GETSEC.
+	- Fix some memory leaking issues in case of prefixed instructions such
+	  as LOCK, REP, REPNE.
+
+
+[ Python binding ]
+
+- Verify the core version at initialization time. Refuse to run if its version
+  is different from the core's version.
+- New API disasm_lite() added to Cs class. This light API only returns tuples of
+  (address, size, mnemonic, op_str), rather than list of CsInsn objects. This
+  improves performance by around 30% in some benchmarks.
+- New API version_bind() returns binding's version, which might differ from
+  the core's API version if the binding is out-of-date.
+- New API debug() returns information on Cython support, diet status & archs
+  compiled in.
+- Fixed some memory leaking bugs for Cython binding.
+- Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups.
+- Support diet mode.
+
+
+[ Java binding ]
+
+- Fix some memory leaking bugs.
+- New API version() returns combined version.
+- Support diet mode.
+- Better support for detail option.
+
+
+[ Miscellaneous ]
+
+- make.sh now can uninstall the core engine. This is done with:
+
+	$ sudo ./make.sh uninstall
+
+----------------------------------
+Version 2.0: January 22nd, 2014
+
+Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
+
+[ API changes ]
+
+- API version has been bumped to 2.0 (see cs_version() API)
+- New API cs_strerror(errno) returns a string describing error code given
+  in its only argument.
+- cs_version() now returns combined version encoding both major & minor versions.
+- New option CS_OPT_MODE allows to change engine’s mode at run-time with
+  cs_option().
+- New option CS_OPT_MEM allows to specify user-defined functions for dynamically
+  memory management used internally by Capstone. This is useful to embed Capstone
+  into special environments such as kernel or firware.
+- New API cs_support() can be used to check if this lib supports a particular
+  architecture (this is necessary since we now allow to choose which architectures
+  to compile in).
+- The detail option is OFF by default now. To get detail information, it should be
+  explicitly turned ON. The details then can be accessed using cs_insn.detail
+  pointer (to newly added structure cs_detail)
+
+
+[ Core changes ]
+
+- On memory usage, Capstone uses much less memory, but a lot faster now.
+- User now can choose which architectures to be supported by modifying config.mk
+  before compiling/installing.
+
+
+[ Architectures ]
+
+- Arm
+     - Support Big-Endian mode (besides Little-Endian mode).
+     - Support friendly register, so instead of output sub "r12,r11,0x14",
+	 we have "sub ip,fp,0x14".
+- Arm64: support Big-Endian mode (besides Little-Endian mode).
+- PowerPC: newly added.
+- Mips: support friendly register, so instead of output "srl $2,$1,0x1f",
+     we have "srl $v0,$at,0x1f".
+- X86: bug fixes.
+
+
+[ Python binding ]
+
+- Python binding is vastly improved in performance: around 3 ~ 4 times faster
+  than in 1.0.
+- Cython support has been added, which can further speed up over the default
+  pure Python binding (up to 30% in some cases)
+- Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list)
+  to return succesfully disassembled instructions. This improves the performance
+  and reduces memory usage.
+
+
+[ Java binding ]
+
+- Better performance & bug fixes.
+
+
+[ Miscellaneous ]
+
+- Fixed some installation issues with Gentoo Linux.
+- Capstone now can easily compile/install on all *nix, including Linux, OSX,
+  {Net, Free, Open}BSD & Solaris.
+
+----------------------------------
+[Version 1.0]: December 18th, 2013
+
+- Initial public release.
+

src/3rd-party/capstone/capstone/HACK.TXT

@@ -0,0 +1,40 @@
+Capstone source is organized as followings.
+
+
+.                   <- core engine + README + COMPILE.TXT etc
+├── arch            <- code handling disasm engine for each arch
+│   ├── AArch64     <- ARM64 (aka ARMv8) engine
+│   ├── ARM         <- ARM engine
+│   ├── Mips        <- Mips engine
+│   ├── PowerPC     <- PowerPC engine
+│   ├── Sparc       <- Sparc engine
+│   ├── SystemZ     <- SystemZ engine
+│   ├── X86         <- X86 engine
+│   └── XCore       <- XCore engine
+├── bindings        <- all bindings are under this dir
+│   ├── java        <- Java bindings + test code
+│   ├── ocaml       <- Ocaml bindings + test code
+│   └── python      <- Python bindings + test code
+├── contrib         <- Code contributed by community to help Capstone integration
+├── docs            <- Documentation
+├── include         <- API headers in C language (*.h)
+├── msvc            <- Microsoft Visual Studio support (for Windows compile)
+├── packages        <- Packages for Linux/OSX/BSD.
+├── suite           <- Development test tools - for Capstone developers only
+├── tests           <- Test code (in C language)
+└── xcode           <- Xcode support (for MacOSX compile)
+
+
+Follow instructions in COMPILE.TXT for how to compile and run test code.
+
+Note: if you find some strange bugs, it is recommended to firstly clean
+the code and try to recompile/reinstall again. This can be done with:
+
+	$ ./make.sh
+	$ sudo ./make.sh install
+
+At the same time, for Java/Ocaml/Python bindings, be sure to always use
+the bindings coming with the core to avoid potential incompatility issue
+with older versions.
+See bindings/<language>/README for detail instructions on how to compile &
+install the bindings.

src/3rd-party/capstone/capstone/LEB128.h

@@ -0,0 +1,38 @@
+//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares some utility functions for encoding SLEB128 and
+// ULEB128 values.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_SUPPORT_LEB128_H
+#define CS_LLVM_SUPPORT_LEB128_H
+
+#include <stdint.h>
+
+/// Utility function to decode a ULEB128 value.
+static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
+{
+	const uint8_t *orig_p = p;
+	uint64_t Value = 0;
+	unsigned Shift = 0;
+	do {
+		Value += (*p & 0x7f) << Shift;
+		Shift += 7;
+	} while (*p++ >= 128);
+	if (n)
+		*n = (unsigned)(p - orig_p);
+	return Value;
+}
+
+#endif  // LLVM_SYSTEM_LEB128_H

src/3rd-party/capstone/capstone/LICENSE.TXT

@@ -0,0 +1,31 @@
+This is the software license for Capstone disassembly framework.
+Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
+
+See http://www.capstone-engine.org for further information.
+
+Copyright (c) 2013, COSEINC.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+* Neither the name of the developer(s) nor the names of its
+  contributors may be used to endorse or promote products derived from this
+  software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.

src/3rd-party/capstone/capstone/LICENSE_LLVM.TXT

@@ -0,0 +1,71 @@
+==============================================================================
+LLVM Release License
+==============================================================================
+University of Illinois/NCSA
+Open Source License
+
+Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign.
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+==============================================================================
+Copyrights and Licenses for Third Party Software Distributed with LLVM:
+==============================================================================
+The LLVM software contains code written by third parties.  Such software will
+have its own individual LICENSE.TXT file in the directory in which it appears.
+This file will describe the copyrights, license, and restrictions which apply
+to that code.
+
+The disclaimer of warranty in the University of Illinois Open Source License
+applies to all code in the LLVM Distribution, and nothing in any of the
+other licenses gives permission to use the names of the LLVM Team or the
+University of Illinois to endorse or promote products derived from this
+Software.
+
+The following pieces of software have additional or alternate copyrights,
+licenses, and/or restrictions:
+
+Program             Directory
+-------             ---------
+Autoconf            llvm/autoconf
+                    llvm/projects/ModuleMaker/autoconf
+                    llvm/projects/sample/autoconf
+Google Test         llvm/utils/unittest/googletest
+OpenBSD regex       llvm/lib/Support/{reg*, COPYRIGHT.regex}
+pyyaml tests        llvm/test/YAMLParser/{*.data, LICENSE.TXT}
+ARM contributions   llvm/lib/Target/ARM/LICENSE.TXT
+md5 contributions   llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h

src/3rd-party/capstone/capstone/MCDisassembler.h

@@ -0,0 +1,14 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_MCDISASSEMBLER_H
+#define CS_MCDISASSEMBLER_H
+
+typedef enum DecodeStatus {
+	MCDisassembler_Fail = 0,
+	MCDisassembler_SoftFail = 1,
+	MCDisassembler_Success = 3,
+} DecodeStatus;
+
+#endif
+

src/3rd-party/capstone/capstone/MCFixedLenDisassembler.h

@@ -0,0 +1,30 @@
+//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// Fixed length disassembler decoder state machine driver.
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
+#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
+
+// Disassembler state machine opcodes.
+enum DecoderOps {
+	MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
+	MCD_OPC_FilterValue,      // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
+	MCD_OPC_CheckField,       // OPC_CheckField(uint8_t Start, uint8_t Len,
+							  //                uleb128 Val, uint16_t NumToSkip)
+	MCD_OPC_CheckPredicate,   // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
+	MCD_OPC_Decode,           // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
+	MCD_OPC_SoftFail,         // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
+	MCD_OPC_Fail              // OPC_Fail()
+};
+
+#endif

src/3rd-party/capstone/capstone/MCInst.c

@@ -0,0 +1,176 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <libkern/libkern.h>
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+#include <string.h>
+
+#include "MCInst.h"
+#include "utils.h"
+
+#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
+
+void MCInst_Init(MCInst *inst)
+{
+	inst->OpcodePub = 0;
+	inst->size = 0;
+	inst->has_imm = false;
+	inst->op1_size = 0;
+	inst->writeback = false;
+}
+
+void MCInst_clear(MCInst *inst)
+{
+	inst->size = 0;
+}
+
+// do not free @Op
+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
+{
+	int i;
+
+	for(i = inst->size; i > index; i--)
+		//memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
+		inst->Operands[i] = inst->Operands[i-1];
+
+	inst->Operands[index] = *Op;
+	inst->size++;
+}
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op)
+{
+	inst->Opcode = Op;
+}
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
+{
+	inst->OpcodePub = Op;
+}
+
+unsigned MCInst_getOpcode(const MCInst *inst)
+{
+	return inst->Opcode;
+}
+
+unsigned MCInst_getOpcodePub(const MCInst *inst)
+{
+	return inst->OpcodePub;
+}
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
+{
+	return &inst->Operands[i];
+}
+
+unsigned MCInst_getNumOperands(const MCInst *inst)
+{
+	return inst->size;
+}
+
+// This addOperand2 function doesnt free Op
+void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
+{
+	inst->Operands[inst->size] = *Op;
+
+	inst->size++;
+}
+
+void MCOperand_Init(MCOperand *op)
+{
+	op->Kind = kInvalid;
+	op->FPImmVal = 0.0;
+}
+
+bool MCOperand_isValid(const MCOperand *op)
+{
+	return op->Kind != kInvalid;
+}
+
+bool MCOperand_isReg(const MCOperand *op)
+{
+	return op->Kind == kRegister;
+}
+
+bool MCOperand_isImm(const MCOperand *op)
+{
+	return op->Kind == kImmediate;
+}
+
+bool MCOperand_isFPImm(const MCOperand *op)
+{
+	return op->Kind == kFPImmediate;
+}
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op)
+{
+	return op->RegVal;
+}
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg)
+{
+	op->RegVal = Reg;
+}
+
+int64_t MCOperand_getImm(MCOperand *op)
+{
+	return op->ImmVal;
+}
+
+void MCOperand_setImm(MCOperand *op, int64_t Val)
+{
+	op->ImmVal = Val;
+}
+
+double MCOperand_getFPImm(const MCOperand *op)
+{
+	return op->FPImmVal;
+}
+
+void MCOperand_setFPImm(MCOperand *op, double Val)
+{
+	op->FPImmVal = Val;
+}
+
+MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
+{
+	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+
+	op->Kind = kRegister;
+	op->RegVal = Reg;
+
+	return op;
+}
+
+void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
+{
+	MCOperand *op = &(mcInst->Operands[mcInst->size]);
+	mcInst->size++;
+
+	op->Kind = kRegister;
+	op->RegVal = Reg;
+}
+
+MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
+{
+	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+
+	op->Kind = kImmediate;
+	op->ImmVal = Val;
+
+	return op;
+}
+
+void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
+{
+	MCOperand *op = &(mcInst->Operands[mcInst->size]);
+	mcInst->size++;
+
+	op->Kind = kImmediate;
+	op->ImmVal = Val;
+}

src/3rd-party/capstone/capstone/MCInst.h

@@ -0,0 +1,134 @@
+//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the MCInst and MCOperand classes, which
+// is the basic representation used to represent low-level machine code
+// instructions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_MCINST_H
+#define CS_MCINST_H
+
+#include <stdint.h>
+
+#include "include/capstone.h"
+
+typedef struct MCInst MCInst;
+typedef struct cs_struct cs_struct;
+typedef struct MCOperand MCOperand;
+
+/// MCOperand - Instances of this class represent operands of the MCInst class.
+/// This is a simple discriminated union.
+struct MCOperand {
+	enum {
+		kInvalid = 0,                 ///< Uninitialized.
+		kRegister,                ///< Register operand.
+		kImmediate,               ///< Immediate operand.
+		kFPImmediate,             ///< Floating-point immediate operand.
+	} MachineOperandType;
+	unsigned char Kind;
+
+	union {
+		unsigned RegVal;
+		int64_t ImmVal;
+		double FPImmVal;
+	};
+};
+
+bool MCOperand_isValid(const MCOperand *op);
+
+bool MCOperand_isReg(const MCOperand *op);
+
+bool MCOperand_isImm(const MCOperand *op);
+
+bool MCOperand_isFPImm(const MCOperand *op);
+
+bool MCOperand_isInst(const MCOperand *op);
+
+void MCInst_clear(MCInst *m);
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op);
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg);
+
+int64_t MCOperand_getImm(MCOperand *op);
+
+void MCOperand_setImm(MCOperand *op, int64_t Val);
+
+double MCOperand_getFPImm(const MCOperand *op);
+
+void MCOperand_setFPImm(MCOperand *op, double Val);
+
+const MCInst *MCOperand_getInst(const MCOperand *op);
+
+void MCOperand_setInst(MCOperand *op, const MCInst *Val);
+
+// create Reg operand in the next slot
+void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);
+
+// create Reg operand use the last-unused slot
+MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg);
+
+// create Imm operand in the next slot
+void MCOperand_CreateImm0(MCInst *inst, int64_t Val);
+
+// create Imm operand in the last-unused slot
+MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val);
+
+/// MCInst - Instances of this class represent a single low-level machine
+/// instruction.
+struct MCInst {
+	unsigned OpcodePub;
+	uint8_t size;	// number of operands
+	bool has_imm;	// indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
+	uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
+	unsigned Opcode;
+	MCOperand Operands[48];
+	cs_insn *flat_insn;	// insn to be exposed to public
+	uint64_t address;	// address of this insn
+	cs_struct *csh;	// save the main csh
+	uint8_t x86opsize;	// opsize for [mem] operand
+
+	// (Optional) instruction prefix, which can be up to 4 bytes.
+	// A prefix byte gets value 0 when irrelevant.
+	// This is copied from cs_x86 struct
+	uint8_t x86_prefix[4];
+	uint8_t imm_size;	// immediate size for X86_OP_IMM operand
+	bool writeback;	// writeback for ARM
+};
+
+void MCInst_Init(MCInst *inst);
+
+void MCInst_clear(MCInst *inst);
+
+// do not free operand after inserting
+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op);
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcode(const MCInst*);
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcodePub(const MCInst*);
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
+
+unsigned MCInst_getNumOperands(const MCInst *inst);
+
+// This addOperand2 function doesnt free Op
+void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
+
+#endif

src/3rd-party/capstone/capstone/MCInstrDesc.c

@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include "MCInstrDesc.h"
+
+/// isPredicate - Set if this is one of the operands that made up of
+/// the predicate operand that controls an isPredicable() instruction.
+bool MCOperandInfo_isPredicate(MCOperandInfo *m)
+{
+	return m->Flags & (1 << MCOI_Predicate);
+}
+
+/// isOptionalDef - Set if this operand is a optional def.
+///
+bool MCOperandInfo_isOptionalDef(MCOperandInfo *m)
+{
+	return m->Flags & (1 << MCOI_OptionalDef);
+}

src/3rd-party/capstone/capstone/MCInstrDesc.h

@@ -0,0 +1,143 @@
+//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCOperandInfo and MCInstrDesc classes, which
+// are used to describe target instructions and their operands.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_MC_MCINSTRDESC_H
+#define CS_LLVM_MC_MCINSTRDESC_H
+
+#include <stdint.h>
+#include "include/platform.h"
+
+//===----------------------------------------------------------------------===//
+// Machine Operand Flags and Description
+//===----------------------------------------------------------------------===//
+
+// Operand constraints
+enum MCOI_OperandConstraint {
+	MCOI_TIED_TO = 0,    // Must be allocated the same register as.
+	MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
+};
+
+/// OperandFlags - These are flags set on operands, but should be considered
+/// private, all access should go through the MCOperandInfo accessors.
+/// See the accessors for a description of what these are.
+enum MCOI_OperandFlags {
+	MCOI_LookupPtrRegClass = 0,
+	MCOI_Predicate,
+	MCOI_OptionalDef
+};
+
+/// Operand Type - Operands are tagged with one of the values of this enum.
+enum MCOI_OperandType {
+	MCOI_OPERAND_UNKNOWN,
+	MCOI_OPERAND_IMMEDIATE,
+	MCOI_OPERAND_REGISTER,
+	MCOI_OPERAND_MEMORY,
+	MCOI_OPERAND_PCREL
+};
+
+
+/// MCOperandInfo - This holds information about one operand of a machine
+/// instruction, indicating the register class for register operands, etc.
+///
+typedef struct MCOperandInfo {
+	/// RegClass - This specifies the register class enumeration of the operand
+	/// if the operand is a register.  If isLookupPtrRegClass is set, then this is
+	/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
+	/// get a dynamic register class.
+	int16_t RegClass;
+
+	/// Flags - These are flags from the MCOI::OperandFlags enum.
+	uint8_t Flags;
+
+	/// OperandType - Information about the type of the operand.
+	uint8_t OperandType;
+
+	/// Lower 16 bits are used to specify which constraints are set. The higher 16
+	/// bits are used to specify the value of constraints (4 bits each).
+	uint32_t Constraints;
+	/// Currently no other information.
+} MCOperandInfo;
+
+
+//===----------------------------------------------------------------------===//
+// Machine Instruction Flags and Description
+//===----------------------------------------------------------------------===//
+
+/// MCInstrDesc flags - These should be considered private to the
+/// implementation of the MCInstrDesc class.  Clients should use the predicate
+/// methods on MCInstrDesc, not use these directly.  These all correspond to
+/// bitfields in the MCInstrDesc::Flags field.
+enum {
+	MCID_Variadic = 0,
+	MCID_HasOptionalDef,
+	MCID_Pseudo,
+	MCID_Return,
+	MCID_Call,
+	MCID_Barrier,
+	MCID_Terminator,
+	MCID_Branch,
+	MCID_IndirectBranch,
+	MCID_Compare,
+	MCID_MoveImm,
+	MCID_Bitcast,
+	MCID_Select,
+	MCID_DelaySlot,
+	MCID_FoldableAsLoad,
+	MCID_MayLoad,
+	MCID_MayStore,
+	MCID_Predicable,
+	MCID_NotDuplicable,
+	MCID_UnmodeledSideEffects,
+	MCID_Commutable,
+	MCID_ConvertibleTo3Addr,
+	MCID_UsesCustomInserter,
+	MCID_HasPostISelHook,
+	MCID_Rematerializable,
+	MCID_CheapAsAMove,
+	MCID_ExtraSrcRegAllocReq,
+	MCID_ExtraDefRegAllocReq,
+	MCID_RegSequence,
+};
+
+/// MCInstrDesc - Describe properties that are true of each instruction in the
+/// target description file.  This captures information about side effects,
+/// register use and many other things.  There is one instance of this struct
+/// for each target instruction class, and the MachineInstr class points to
+/// this struct directly to describe itself.
+typedef struct MCInstrDesc {
+	unsigned short  Opcode;        // The opcode number
+	unsigned char  NumOperands;   // Num of args (may be more if variable_ops)
+	unsigned char  NumDefs;       // Num of args that are definitions
+	unsigned short  SchedClass;    // enum identifying instr sched class
+	unsigned char  Size;          // Number of bytes in encoding.
+	unsigned        Flags;         // Flags identifying machine instr class
+	uint64_t        TSFlags;       // Target Specific Flag values
+	char ImplicitUses;  // Registers implicitly read by this instr
+	char ImplicitDefs;  // Registers implicitly defined by this instr
+	MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
+	uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any     
+	// A complex method to determine is a certain is deprecated or not, and return        
+	// the reason for deprecation.
+	//bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);           
+	unsigned char ComplexDeprecationInfo;	// dummy field, just to satisfy initializer
+} MCInstrDesc;
+
+bool MCOperandInfo_isPredicate(MCOperandInfo *m);
+
+bool MCOperandInfo_isOptionalDef(MCOperandInfo *m);
+
+#endif

src/3rd-party/capstone/capstone/MCRegisterInfo.c

@@ -0,0 +1,143 @@
+//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements MCRegisterInfo functions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include "MCRegisterInfo.h"
+
+/// DiffListIterator - Base iterator class that can traverse the
+/// differentially encoded register and regunit lists in DiffLists.
+/// Don't use this class directly, use one of the specialized sub-classes
+/// defined below.
+typedef struct DiffListIterator {
+	uint16_t Val;
+	MCPhysReg *List;
+} DiffListIterator;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+		MCRegisterDesc *D, unsigned NR,
+		unsigned RA, unsigned PC,
+		MCRegisterClass *C, unsigned NC,
+		uint16_t (*RURoots)[2], unsigned NRU,
+		MCPhysReg *DL,
+		char *Strings,
+		uint16_t *SubIndices, unsigned NumIndices,
+		uint16_t *RET)
+{
+	RI->Desc = D;
+	RI->NumRegs = NR;
+	RI->RAReg = RA;
+	RI->PCReg = PC;
+	RI->Classes = C;
+	RI->DiffLists = DL;
+	RI->RegStrings = Strings;
+	RI->NumClasses = NC;
+	RI->RegUnitRoots = RURoots;
+	RI->NumRegUnits = NRU;
+	RI->SubRegIndices = SubIndices;
+	RI->NumSubRegIndices = NumIndices;
+	RI->RegEncodingTable = RET;
+}
+
+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList)
+{
+	d->Val = InitVal;
+	d->List = DiffList;
+}
+
+static uint16_t DiffListIterator_getVal(DiffListIterator *d)
+{
+	return d->Val;
+}
+
+static bool DiffListIterator_next(DiffListIterator *d)
+{
+	MCPhysReg D;
+
+	if (d->List == 0)
+		return false;
+
+	D = *d->List;
+	d->List++;
+	d->Val += D;
+
+	if (!D)
+		d->List = 0;
+
+	return (D != 0);
+}
+
+static bool DiffListIterator_isValid(DiffListIterator *d)
+{
+	return (d->List != 0);
+}
+
+unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC)
+{
+	DiffListIterator iter;
+
+	if (Reg >= RI->NumRegs) {
+		return 0;
+	}
+
+	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
+	DiffListIterator_next(&iter);
+
+	while(DiffListIterator_isValid(&iter)) {
+		uint16_t val = DiffListIterator_getVal(&iter);
+		if (MCRegisterClass_contains(RC, val) && Reg ==  MCRegisterInfo_getSubReg(RI, val, SubIdx))
+			return val;
+
+		DiffListIterator_next(&iter);
+	}
+
+	return 0;
+}
+
+unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
+{
+	DiffListIterator iter;
+	uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
+
+	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
+	DiffListIterator_next(&iter);
+
+	while(DiffListIterator_isValid(&iter)) {
+		if (*SRI == Idx)
+			return DiffListIterator_getVal(&iter);
+		DiffListIterator_next(&iter);
+		++SRI;
+	}
+
+	return 0;
+}
+
+MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i)
+{
+	//assert(i < getNumRegClasses() && "Register Class ID out of range");
+	if (i >= RI->NumClasses)
+		return 0;
+	return &(RI->Classes[i]);
+}
+
+bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg)
+{
+	unsigned InByte = Reg % 8;
+	unsigned Byte = Reg / 8;
+
+	if (Byte >= c->RegSetSize)
+		return false;
+
+	return (c->RegSet[Byte] & (1 << InByte)) != 0;
+}

src/3rd-party/capstone/capstone/MCRegisterInfo.h

@@ -0,0 +1,114 @@
+//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes an abstract interface used to get information about a
+// target machines register file.  This information is used for a variety of
+// purposed, especially register allocation.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_MC_MCREGISTERINFO_H
+#define CS_LLVM_MC_MCREGISTERINFO_H
+
+#include <stdint.h>
+#include "include/platform.h"
+
+/// An unsigned integer type large enough to represent all physical registers,
+/// but not necessarily virtual registers.
+typedef uint16_t MCPhysReg;
+typedef MCPhysReg* iterator;
+
+typedef struct MCRegisterClass {
+	char *Name;
+	iterator RegsBegin;
+	uint8_t *RegSet;
+	uint16_t RegsSize;
+	uint16_t RegSetSize;
+	uint16_t ID;
+	uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
+	int8_t CopyCost;
+	bool Allocatable;
+} MCRegisterClass;
+
+/// MCRegisterDesc - This record contains information about a particular
+/// register.  The SubRegs field is a zero terminated array of registers that
+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
+/// of AX. The SuperRegs field is a zero terminated array of registers that are
+/// super-registers of the specific register, e.g. RAX, EAX, are
+/// super-registers of AX.
+///
+typedef struct MCRegisterDesc {
+	uint32_t Name;      // Printable name for the reg (for debugging)
+	uint32_t SubRegs;   // Sub-register set, described above
+	uint32_t SuperRegs; // Super-register set, described above
+
+	// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
+	// sub-register in SubRegs.
+	uint32_t SubRegIndices;
+
+	// RegUnits - Points to the list of register units. The low 4 bits holds the
+	// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
+	uint32_t RegUnits;
+} MCRegisterDesc;
+
+/// MCRegisterInfo base class - We assume that the target defines a static
+/// array of MCRegisterDesc objects that represent all of the machine
+/// registers that the target has.  As such, we simply have to track a pointer
+/// to this array so that we can turn register number into a register
+/// descriptor.
+///
+/// Note this class is designed to be a base class of TargetRegisterInfo, which
+/// is the interface used by codegen. However, specific targets *should never*
+/// specialize this class. MCRegisterInfo should only contain getters to access
+/// TableGen generated physical register data. It must not be extended with
+/// virtual methods.
+///
+typedef struct MCRegisterInfo {
+	MCRegisterDesc *Desc;                 // Pointer to the descriptor array
+	unsigned NumRegs;                           // Number of entries in the array
+	unsigned RAReg;                             // Return address register
+	unsigned PCReg;                             // Program counter register
+	MCRegisterClass *Classes;             // Pointer to the regclass array
+	unsigned NumClasses;                        // Number of entries in the array
+	unsigned NumRegUnits;                       // Number of regunits.
+	uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
+	MCPhysReg *DiffLists;                 // Pointer to the difflists array
+	char *RegStrings;                     // Pointer to the string table.
+	uint16_t *SubRegIndices;              // Pointer to the subreg lookup
+	// array.
+	unsigned NumSubRegIndices;                  // Number of subreg indices.
+	uint16_t *RegEncodingTable;           // Pointer to array of register
+	// encodings.
+} MCRegisterInfo;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+		MCRegisterDesc *D, unsigned NR, unsigned RA,
+		unsigned PC,
+		MCRegisterClass *C, unsigned NC,
+		uint16_t (*RURoots)[2],
+		unsigned NRU,
+		MCPhysReg *DL,
+		char *Strings,
+		uint16_t *SubIndices,
+		unsigned NumIndices,
+		uint16_t *RET);
+
+
+unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC);
+
+unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
+
+MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i);
+
+bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg);
+
+#endif

src/3rd-party/capstone/capstone/Makefile

@@ -0,0 +1,466 @@
+# Capstone Disassembly Engine
+# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014
+
+include config.mk
+include pkgconfig.mk	# package version
+include functions.mk
+
+# Verbose output?
+V ?= 0
+
+ifeq ($(PKG_EXTRA),)
+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR)
+else
+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA)
+endif
+
+ifeq ($(CROSS),)
+CC ?= cc
+AR ?= ar
+RANLIB ?= ranlib
+STRIP ?= strip
+else
+CC = $(CROSS)gcc
+AR = $(CROSS)ar
+RANLIB = $(CROSS)ranlib
+STRIP = $(CROSS)strip
+endif
+
+ifneq (,$(findstring yes,$(CAPSTONE_DIET)))
+CFLAGS ?= -Os
+CFLAGS += -DCAPSTONE_DIET
+else
+CFLAGS ?= -O3
+endif
+
+ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
+CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
+endif
+
+CFLAGS += -fPIC -Wall -Iinclude
+
+ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
+CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
+endif
+
+ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes)
+CFLAGS += -DCAPSTONE_HAS_OSXKERNEL
+endif
+
+CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
+LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
+
+PREFIX ?= /usr
+DESTDIR ?=
+ifndef BUILDDIR
+BLDIR = .
+OBJDIR = .
+else
+BLDIR = $(abspath $(BUILDDIR))
+OBJDIR = $(BLDIR)/obj
+endif
+INCDIR = $(DESTDIR)$(PREFIX)/include
+
+UNAME_S := $(shell uname -s)
+
+LIBDIRARCH ?= lib
+# Uncomment the below line to installs x86_64 libs to lib64/ directory.
+# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'.
+#LIBDIRARCH ?= lib64
+LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH)
+
+LIBDATADIR = $(LIBDIR)
+ifeq ($(UNAME_S), FreeBSD)
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+endif
+ifeq ($(UNAME_S), DragonFly)
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+endif
+
+INSTALL_BIN ?= install
+INSTALL_DATA ?= $(INSTALL_BIN) -m0644
+INSTALL_LIB ?= $(INSTALL_BIN) -m0755
+
+LIBNAME = capstone
+
+
+DEP_ARM =
+DEP_ARM += arch/ARM/ARMGenAsmWriter.inc
+DEP_ARM += arch/ARM/ARMGenDisassemblerTables.inc
+DEP_ARM += arch/ARM/ARMGenInstrInfo.inc
+DEP_ARM += arch/ARM/ARMGenRegisterInfo.inc
+DEP_ARM += arch/ARM/ARMGenSubtargetInfo.inc
+
+LIBOBJ_ARM =
+ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_ARM
+	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMDisassembler.o
+	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMInstPrinter.o
+	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMMapping.o
+	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMModule.o
+endif
+
+DEP_ARM64 =
+DEP_ARM64 += arch/AArch64/AArch64GenAsmWriter.inc
+DEP_ARM64 += arch/AArch64/AArch64GenInstrInfo.inc
+DEP_ARM64 += arch/AArch64/AArch64GenSubtargetInfo.inc
+DEP_ARM64 += arch/AArch64/AArch64GenDisassemblerTables.inc
+DEP_ARM64 += arch/AArch64/AArch64GenRegisterInfo.inc
+
+LIBOBJ_ARM64 =
+ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_ARM64
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64BaseInfo.o
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Disassembler.o
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64InstPrinter.o
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Mapping.o
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Module.o
+endif
+
+
+DEP_MIPS =
+DEP_MIPS += arch/Mips/MipsGenAsmWriter.inc
+DEP_MIPS += arch/Mips/MipsGenDisassemblerTables.inc
+DEP_MIPS += arch/Mips/MipsGenInstrInfo.inc
+DEP_MIPS += arch/Mips/MipsGenRegisterInfo.inc
+DEP_MIPS += arch/Mips/MipsGenSubtargetInfo.inc
+
+LIBOBJ_MIPS =
+ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_MIPS
+	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsDisassembler.o
+	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsInstPrinter.o
+	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsMapping.o
+	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsModule.o
+endif
+
+
+DEP_PPC =
+DEP_PPC += arch/PowerPC/PPCGenAsmWriter.inc
+DEP_PPC += arch/PowerPC/PPCGenInstrInfo.inc
+DEP_PPC += arch/PowerPC/PPCGenSubtargetInfo.inc
+DEP_PPC += arch/PowerPC/PPCGenDisassemblerTables.inc
+DEP_PPC += arch/PowerPC/PPCGenRegisterInfo.inc
+
+LIBOBJ_PPC =
+ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_POWERPC
+	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCDisassembler.o
+	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCInstPrinter.o
+	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCMapping.o
+	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCModule.o
+endif
+
+
+DEP_SPARC =
+DEP_SPARC += arch/Sparc/SparcGenAsmWriter.inc
+DEP_SPARC += arch/Sparc/SparcGenInstrInfo.inc
+DEP_SPARC += arch/Sparc/SparcGenSubtargetInfo.inc
+DEP_SPARC += arch/Sparc/SparcGenDisassemblerTables.inc
+DEP_SPARC += arch/Sparc/SparcGenRegisterInfo.inc
+
+LIBOBJ_SPARC =
+ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_SPARC
+	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcDisassembler.o
+	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcInstPrinter.o
+	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcMapping.o
+	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcModule.o
+endif
+
+
+DEP_SYSZ =
+DEP_SYSZ += arch/SystemZ/SystemZGenAsmWriter.inc
+DEP_SYSZ += arch/SystemZ/SystemZGenInstrInfo.inc
+DEP_SYSZ += arch/SystemZ/SystemZGenSubtargetInfo.inc
+DEP_SYSZ += arch/SystemZ/SystemZGenDisassemblerTables.inc
+DEP_SYSZ += arch/SystemZ/SystemZGenRegisterInfo.inc
+
+LIBOBJ_SYSZ =
+ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_SYSZ
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZDisassembler.o
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZInstPrinter.o
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZMapping.o
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZModule.o
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZMCTargetDesc.o
+endif
+
+
+# by default, we compile full X86 instruction sets
+X86_REDUCE =
+ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE)))
+X86_REDUCE = _reduce
+CFLAGS += -DCAPSTONE_X86_REDUCE -Os
+endif
+
+DEP_X86 =
+DEP_X86 += arch/X86/X86GenAsmWriter$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenRegisterInfo.inc
+
+LIBOBJ_X86 =
+ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_X86
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
+# assembly syntax is irrelevant in Diet mode, when this info is suppressed
+ifeq (,$(findstring yes,$(CAPSTONE_DIET)))
+ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
+endif
+endif
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
+endif
+
+
+DEP_XCORE =
+DEP_XCORE += arch/XCore/XCoreGenAsmWriter.inc
+DEP_XCORE += arch/XCore/XCoreGenInstrInfo.inc
+DEP_XCORE += arch/XCore/XCoreGenDisassemblerTables.inc
+DEP_XCORE += arch/XCore/XCoreGenRegisterInfo.inc
+
+LIBOBJ_XCORE =
+ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_XCORE
+	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreDisassembler.o
+	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreInstPrinter.o
+	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreMapping.o
+	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreModule.o
+endif
+
+
+LIBOBJ =
+LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE)
+LIBOBJ += $(OBJDIR)/MCInst.o
+
+
+PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig
+API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
+VERSION_EXT =
+
+IS_APPLE := $(shell $(CC) -dM -E - < /dev/null | grep __apple_build_version__ | wc -l | tr -d " ")
+ifeq ($(IS_APPLE),1)
+EXT = dylib
+VERSION_EXT = $(API_MAJOR).$(EXT)
+$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR)
+AR_EXT = a
+# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE
+# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default
+ifneq ($(HOMEBREW_CAPSTONE),1)
+ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
+# remove string check because OSX kernel complains about missing symbols
+CFLAGS += -D_FORTIFY_SOURCE=0
+endif
+endif
+else
+$(LIBNAME)_LDFLAGS += -shared
+# Cygwin?
+IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l)
+ifeq ($(IS_CYGWIN),1)
+EXT = dll
+AR_EXT = lib
+# Cygwin doesn't like -fPIC
+CFLAGS := $(CFLAGS:-fPIC=)
+# On Windows we need the shared library to be executable
+else
+# mingw?
+IS_MINGW := $(shell $(CC) --version | grep -i mingw | wc -l)
+ifeq ($(IS_MINGW),1)
+EXT = dll
+AR_EXT = lib
+# mingw doesn't like -fPIC either
+CFLAGS := $(CFLAGS:-fPIC=)
+# On Windows we need the shared library to be executable
+else
+# Linux, *BSD
+EXT = so
+VERSION_EXT = $(EXT).$(API_MAJOR)
+AR_EXT = a
+$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT)
+endif
+endif
+endif
+
+ifeq ($(CAPSTONE_SHARED),yes)
+ifeq ($(IS_MINGW),1)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
+else ifeq ($(IS_CYGWIN),1)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
+else	# *nix
+LIBRARY = $(BLDIR)/lib$(LIBNAME).$(EXT)
+CFLAGS += -fvisibility=hidden
+endif
+endif
+
+ifeq ($(CAPSTONE_STATIC),yes)
+ifeq ($(IS_MINGW),1)
+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
+else ifeq ($(IS_CYGWIN),1)
+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
+else
+ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT)
+endif
+endif
+
+PKGCFGF = $(BLDIR)/$(LIBNAME).pc
+
+.PHONY: all clean install uninstall dist
+
+all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+ifndef BUILDDIR
+	cd tests && $(MAKE)
+else
+	cd tests && $(MAKE) BUILDDIR=$(BLDIR)
+endif
+ifeq ($(CAPSTONE_SHARED),yes)
+	$(INSTALL_DATA) $(LIBRARY) $(BLDIR)/tests/
+endif
+endif
+
+ifeq ($(CAPSTONE_SHARED),yes)
+$(LIBRARY): $(LIBOBJ)
+ifeq ($(V),0)
+	$(call log,LINK,$(@:$(BLDIR)/%=%))
+	@$(create-library)
+else
+	$(create-library)
+endif
+endif
+
+$(LIBOBJ): config.mk
+
+$(LIBOBJ_ARM): $(DEP_ARM)
+$(LIBOBJ_ARM64): $(DEP_ARM64)
+$(LIBOBJ_MIPS): $(DEP_MIPS)
+$(LIBOBJ_PPC): $(DEP_PPC)
+$(LIBOBJ_SPARC): $(DEP_SPARC)
+$(LIBOBJ_SYSZ): $(DEP_SYSZ)
+$(LIBOBJ_X86): $(DEP_X86)
+$(LIBOBJ_XCORE): $(DEP_XCORE)
+
+ifeq ($(CAPSTONE_STATIC),yes)
+$(ARCHIVE): $(LIBOBJ)
+	@rm -f $(ARCHIVE)
+ifeq ($(V),0)
+	$(call log,AR,$(@:$(BLDIR)/%=%))
+	@$(create-archive)
+else
+	$(create-archive)
+endif
+endif
+
+$(PKGCFGF):
+ifeq ($(V),0)
+	$(call log,GEN,$(@:$(BLDIR)/%=%))
+	@$(generate-pkgcfg)
+else
+	$(generate-pkgcfg)
+endif
+
+install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
+	mkdir -p $(LIBDIR)
+ifeq ($(CAPSTONE_SHARED),yes)
+	$(INSTALL_LIB) $(LIBRARY) $(LIBDIR)
+ifneq ($(VERSION_EXT),)
+	cd $(LIBDIR) && \
+	mv lib$(LIBNAME).$(EXT) lib$(LIBNAME).$(VERSION_EXT) && \
+	ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT)
+endif
+endif
+ifeq ($(CAPSTONE_STATIC),yes)
+	$(INSTALL_DATA) $(ARCHIVE) $(LIBDIR)
+endif
+	mkdir -p $(INCDIR)/$(LIBNAME)
+	$(INSTALL_DATA) include/*.h $(INCDIR)/$(LIBNAME)
+	mkdir -p $(PKGCFGDIR)
+	$(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)/
+
+uninstall:
+	rm -rf $(INCDIR)/$(LIBNAME)
+	rm -f $(LIBDIR)/lib$(LIBNAME).*
+	rm -f $(PKGCFGDIR)/$(LIBNAME).pc
+
+clean:
+	rm -f $(LIBOBJ)
+	rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).*
+	rm -f $(PKGCFGF)
+
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	cd tests && $(MAKE) clean
+	rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT)
+endif
+
+ifdef BUILDDIR
+	rm -rf $(BUILDDIR)
+endif
+
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	cd bindings/python && $(MAKE) clean
+	cd bindings/java && $(MAKE) clean
+	cd bindings/ocaml && $(MAKE) clean
+endif
+
+
+TAG ?= HEAD
+ifeq ($(TAG), HEAD)
+DIST_VERSION = latest
+else
+DIST_VERSION = $(TAG)
+endif
+
+dist:
+	git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
+	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
+
+
+TESTS = test test_detail test_arm test_arm64 test_mips test_ppc test_sparc
+TESTS += test_systemz test_x86 test_xcore test_iter
+TESTS += test.static test_detail.static test_arm.static test_arm64.static
+TESTS += test_mips.static test_ppc.static test_sparc.static
+TESTS += test_systemz.static test_x86.static test_xcore.static
+TESTS += test_skipdata test_skipdata.static test_iter.static
+check:
+	@for t in $(TESTS); do \
+		echo Check $$t ... ; \
+		./tests/$$t > /dev/null && echo OK || echo FAILED; \
+	done
+
+$(OBJDIR)/%.o: %.c
+	@mkdir -p $(@D)
+ifeq ($(V),0)
+	$(call log,CC,$(@:$(OBJDIR)/%=%))
+	@$(compile)
+else
+	$(compile)
+endif
+
+
+define create-archive
+	$(AR) q $(ARCHIVE) $(LIBOBJ)
+	$(RANLIB) $(ARCHIVE)
+endef
+
+
+define create-library
+	$(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
+endef
+
+
+define generate-pkgcfg
+	echo 'Name: capstone' > $(PKGCFGF)
+	echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
+	echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
+	echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
+	echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF)
+	echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
+	echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
+	echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
+endef
+

src/3rd-party/capstone/capstone/MathExtras.h

@@ -0,0 +1,439 @@
+//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains some functions that are useful for math stuff.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
+#define CS_LLVM_SUPPORT_MATHEXTRAS_H
+
+#include <stdint.h>
+
+#ifdef _MSC_VER
+# include <intrin.h>
+#endif
+
+#ifndef __cplusplus
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#define inline /* inline */
+#endif
+#endif
+
+// NOTE: The following support functions use the _32/_64 extensions instead of
+// type overloading so that signed and unsigned integers can be used without
+// ambiguity.
+
+/// Hi_32 - This function returns the high 32 bits of a 64 bit value.
+static inline uint32_t Hi_32(uint64_t Value) {
+	return (uint32_t)(Value >> 32);
+}
+
+/// Lo_32 - This function returns the low 32 bits of a 64 bit value.
+static inline uint32_t Lo_32(uint64_t Value) {
+	return (uint32_t)(Value);
+}
+
+/// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
+/// bit width.
+static inline bool isUIntN(unsigned N, uint64_t x) {
+	return x == (x & (~0ULL >> (64 - N)));
+}
+
+/// isIntN - Checks if an signed integer fits into the given (dynamic)
+/// bit width.
+//static inline bool isIntN(unsigned N, int64_t x) {
+//  return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
+//}
+
+/// isMask_32 - This function returns true if the argument is a sequence of ones
+/// starting at the least significant bit with the remainder zero (32 bit
+/// version).   Ex. isMask_32(0x0000FFFFU) == true.
+static inline bool isMask_32(uint32_t Value) {
+	return Value && ((Value + 1) & Value) == 0;
+}
+
+/// isMask_64 - This function returns true if the argument is a sequence of ones
+/// starting at the least significant bit with the remainder zero (64 bit
+/// version).
+static inline bool isMask_64(uint64_t Value) {
+	return Value && ((Value + 1) & Value) == 0;
+}
+
+/// isShiftedMask_32 - This function returns true if the argument contains a
+/// sequence of ones with the remainder zero (32 bit version.)
+/// Ex. isShiftedMask_32(0x0000FF00U) == true.
+static inline bool isShiftedMask_32(uint32_t Value) {
+	return isMask_32((Value - 1) | Value);
+}
+
+/// isShiftedMask_64 - This function returns true if the argument contains a
+/// sequence of ones with the remainder zero (64 bit version.)
+static inline bool isShiftedMask_64(uint64_t Value) {
+	return isMask_64((Value - 1) | Value);
+}
+
+/// isPowerOf2_32 - This function returns true if the argument is a power of
+/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
+static inline bool isPowerOf2_32(uint32_t Value) {
+	return Value && !(Value & (Value - 1));
+}
+
+/// CountLeadingZeros_32 - this function performs the platform optimal form of
+/// counting the number of zeros from the most significant bit to the first one
+/// bit.  Ex. CountLeadingZeros_32(0x00F000FF) == 8.
+/// Returns 32 if the word is zero.
+static inline unsigned CountLeadingZeros_32(uint32_t Value) {
+	unsigned Count; // result
+#if __GNUC__ >= 4
+	// PowerPC is defined for __builtin_clz(0)
+#if !defined(__ppc__) && !defined(__ppc64__)
+	if (!Value) return 32;
+#endif
+	Count = __builtin_clz(Value);
+#else
+	unsigned Shift;
+	if (!Value) return 32;
+	Count = 0;
+	// bisection method for count leading zeros
+	for (Shift = 32 >> 1; Shift; Shift >>= 1) {
+		uint32_t Tmp = Value >> Shift;
+		if (Tmp) {
+			Value = Tmp;
+		} else {
+			Count |= Shift;
+		}
+	}
+#endif
+	return Count;
+}
+
+/// CountLeadingOnes_32 - this function performs the operation of
+/// counting the number of ones from the most significant bit to the first zero
+/// bit.  Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
+/// Returns 32 if the word is all ones.
+static inline unsigned CountLeadingOnes_32(uint32_t Value) {
+	return CountLeadingZeros_32(~Value);
+}
+
+/// CountLeadingZeros_64 - This function performs the platform optimal form
+/// of counting the number of zeros from the most significant bit to the first
+/// one bit (64 bit edition.)
+/// Returns 64 if the word is zero.
+static inline unsigned CountLeadingZeros_64(uint64_t Value) {
+	unsigned Count; // result
+#if __GNUC__ >= 4
+	// PowerPC is defined for __builtin_clzll(0)
+#if !defined(__ppc__) && !defined(__ppc64__)
+	if (!Value) return 64;
+#endif
+	Count = __builtin_clzll(Value);
+#else
+#ifndef _MSC_VER
+	unsigned Shift;
+	if (sizeof(long) == sizeof(int64_t))
+	{
+		if (!Value) return 64;
+		Count = 0;
+		// bisection method for count leading zeros
+		for (Shift = 64 >> 1; Shift; Shift >>= 1) {
+			uint64_t Tmp = Value >> Shift;
+			if (Tmp) {
+				Value = Tmp;
+			} else {
+				Count |= Shift;
+			}
+		}
+	}
+	else
+#endif
+	{
+		// get hi portion
+		uint32_t Hi = Hi_32(Value);
+
+		// if some bits in hi portion
+		if (Hi) {
+			// leading zeros in hi portion plus all bits in lo portion
+			Count = CountLeadingZeros_32(Hi);
+		} else {
+			// get lo portion
+			uint32_t Lo = Lo_32(Value);
+			// same as 32 bit value
+			Count = CountLeadingZeros_32(Lo)+32;
+		}
+	}
+#endif
+	return Count;
+}
+
+/// CountLeadingOnes_64 - This function performs the operation
+/// of counting the number of ones from the most significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+static inline unsigned CountLeadingOnes_64(uint64_t Value) {
+	return CountLeadingZeros_64(~Value);
+}
+
+/// CountTrailingZeros_32 - this function performs the platform optimal form of
+/// counting the number of zeros from the least significant bit to the first one
+/// bit.  Ex. CountTrailingZeros_32(0xFF00FF00) == 8.
+/// Returns 32 if the word is zero.
+static inline unsigned CountTrailingZeros_32(uint32_t Value) {
+#if __GNUC__ >= 4
+	return Value ? __builtin_ctz(Value) : 32;
+#else
+	static const unsigned Mod37BitPosition[] = {
+		32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
+		4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
+		5, 20, 8, 19, 18
+	};
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return Mod37BitPosition[(-Value & Value) % 37];
+	return Mod37BitPosition[((1 + ~Value) & Value) % 37];
+#endif
+}
+
+/// CountTrailingOnes_32 - this function performs the operation of
+/// counting the number of ones from the least significant bit to the first zero
+/// bit.  Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
+/// Returns 32 if the word is all ones.
+static inline unsigned CountTrailingOnes_32(uint32_t Value) {
+	return CountTrailingZeros_32(~Value);
+}
+
+/// CountTrailingZeros_64 - This function performs the platform optimal form
+/// of counting the number of zeros from the least significant bit to the first
+/// one bit (64 bit edition.)
+/// Returns 64 if the word is zero.
+static inline unsigned CountTrailingZeros_64(uint64_t Value) {
+#if __GNUC__ >= 4
+	return Value ? __builtin_ctzll(Value) : 64;
+#else
+	static const unsigned Mod67Position[] = {
+		64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
+		4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
+		47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
+		29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
+		7, 48, 35, 6, 34, 33, 0
+	};
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return Mod67Position[(-Value & Value) % 67];
+	return Mod67Position[((1 + ~Value) & Value) % 67];
+#endif
+}
+
+/// CountTrailingOnes_64 - This function performs the operation
+/// of counting the number of ones from the least significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+static inline unsigned CountTrailingOnes_64(uint64_t Value) {
+	return CountTrailingZeros_64(~Value);
+}
+
+/// CountPopulation_32 - this function counts the number of set bits in a value.
+/// Ex. CountPopulation(0xF000F000) = 8
+/// Returns 0 if the word is zero.
+static inline unsigned CountPopulation_32(uint32_t Value) {
+#if __GNUC__ >= 4
+	return __builtin_popcount(Value);
+#else
+	uint32_t v = Value - ((Value >> 1) & 0x55555555);
+	v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
+	return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
+#endif
+}
+
+/// CountPopulation_64 - this function counts the number of set bits in a value,
+/// (64 bit edition.)
+static inline unsigned CountPopulation_64(uint64_t Value) {
+#if __GNUC__ >= 4
+	return __builtin_popcountll(Value);
+#else
+	uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
+	v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
+	v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
+	return (uint64_t)((v * 0x0101010101010101ULL) >> 56);
+#endif
+}
+
+/// Log2_32 - This function returns the floor log base 2 of the specified value,
+/// -1 if the value is zero. (32 bit edition.)
+/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
+static inline unsigned Log2_32(uint32_t Value) {
+	return 31 - CountLeadingZeros_32(Value);
+}
+
+/// Log2_64 - This function returns the floor log base 2 of the specified value,
+/// -1 if the value is zero. (64 bit edition.)
+static inline unsigned Log2_64(uint64_t Value) {
+	return 63 - CountLeadingZeros_64(Value);
+}
+
+/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified
+/// value, 32 if the value is zero. (32 bit edition).
+/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
+static inline unsigned Log2_32_Ceil(uint32_t Value) {
+	return 32-CountLeadingZeros_32(Value-1);
+}
+
+/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified
+/// value, 64 if the value is zero. (64 bit edition.)
+static inline unsigned Log2_64_Ceil(uint64_t Value) {
+	return 64-CountLeadingZeros_64(Value-1);
+}
+
+/// GreatestCommonDivisor64 - Return the greatest common divisor of the two
+/// values using Euclid's algorithm.
+static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
+	while (B) {
+		uint64_t T = B;
+		B = A % B;
+		A = T;
+	}
+	return A;
+}
+
+/// BitsToDouble - This function takes a 64-bit integer and returns the bit
+/// equivalent double.
+static inline double BitsToDouble(uint64_t Bits) {
+	union {
+		uint64_t L;
+		double D;
+	} T;
+	T.L = Bits;
+	return T.D;
+}
+
+/// BitsToFloat - This function takes a 32-bit integer and returns the bit
+/// equivalent float.
+static inline float BitsToFloat(uint32_t Bits) {
+	union {
+		uint32_t I;
+		float F;
+	} T;
+	T.I = Bits;
+	return T.F;
+}
+
+/// DoubleToBits - This function takes a double and returns the bit
+/// equivalent 64-bit integer.  Note that copying doubles around
+/// changes the bits of NaNs on some hosts, notably x86, so this
+/// routine cannot be used if these bits are needed.
+static inline uint64_t DoubleToBits(double Double) {
+	union {
+		uint64_t L;
+		double D;
+	} T;
+	T.D = Double;
+	return T.L;
+}
+
+/// FloatToBits - This function takes a float and returns the bit
+/// equivalent 32-bit integer.  Note that copying floats around
+/// changes the bits of NaNs on some hosts, notably x86, so this
+/// routine cannot be used if these bits are needed.
+static inline uint32_t FloatToBits(float Float) {
+	union {
+		uint32_t I;
+		float F;
+	} T;
+	T.F = Float;
+	return T.I;
+}
+
+/// MinAlign - A and B are either alignments or offsets.  Return the minimum
+/// alignment that may be assumed after adding the two together.
+static inline uint64_t MinAlign(uint64_t A, uint64_t B) {
+	// The largest power of 2 that divides both A and B.
+	//
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return (A | B) & -(A | B);
+	return (A | B) & (1 + ~(A | B));
+}
+
+/// NextPowerOf2 - Returns the next power of two (in 64-bits)
+/// that is strictly greater than A.  Returns zero on overflow.
+static inline uint64_t NextPowerOf2(uint64_t A) {
+	A |= (A >> 1);
+	A |= (A >> 2);
+	A |= (A >> 4);
+	A |= (A >> 8);
+	A |= (A >> 16);
+	A |= (A >> 32);
+	return A + 1;
+}
+
+/// Returns the next integer (mod 2**64) that is greater than or equal to
+/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
+///
+/// Examples:
+/// \code
+///   RoundUpToAlignment(5, 8) = 8
+///   RoundUpToAlignment(17, 8) = 24
+///   RoundUpToAlignment(~0LL, 8) = 0
+/// \endcode
+static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
+	return ((Value + Align - 1) / Align) * Align;
+}
+
+/// Returns the offset to the next integer (mod 2**64) that is greater than
+/// or equal to \p Value and is a multiple of \p Align. \p Align must be
+/// non-zero.
+static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
+	return RoundUpToAlignment(Value, Align) - Value;
+}
+
+/// abs64 - absolute value of a 64-bit int.  Not all environments support
+/// "abs" on whatever their name for the 64-bit int type is.  The absolute
+/// value of the largest negative number is undefined, as with "abs".
+static inline int64_t abs64(int64_t x) {
+	return (x < 0) ? -x : x;
+}
+
+/// \brief Sign extend number in the bottom B bits of X to a 32-bit int.
+/// Requires 0 < B <= 32.
+static inline int32_t SignExtend32(uint32_t X, unsigned B) {
+	return (int32_t)(X << (32 - B)) >> (32 - B);
+}
+
+/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
+/// Requires 0 < B <= 64.
+static inline int64_t SignExtend64(uint64_t X, unsigned B) {
+	return (int64_t)(X << (64 - B)) >> (64 - B);
+}
+
+/// \brief Count number of 0's from the most significant bit to the least
+///   stopping at the first 1.
+///
+/// Only unsigned integral types are allowed.
+///
+/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
+///   valid arguments.
+static inline unsigned int countLeadingZeros(int x)
+{
+	unsigned count = 0;
+	int i;
+	const unsigned bits = sizeof(x) * 8;
+
+	for (i = bits; --i; ) {
+		if (x < 0) break;
+		count++;
+		x <<= 1;
+	}
+
+	return count;
+}
+
+#endif

src/3rd-party/capstone/capstone/README

@@ -0,0 +1,54 @@
+Capstone is a disassembly framework with the target of becoming the ultimate
+disasm engine for binary analysis and reversing in the security community.
+
+Created by Nguyen Anh Quynh, then developed and maintained by a small community,
+Capstone offers some unparalleled features:
+
+- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc,
+  SystemZ, XCore and X86 (including X86_64).
+
+- Having clean/simple/lightweight/intuitive architecture-neutral API.
+
+- Provide details on disassembled instruction (called “decomposer” by others).
+
+- Provide semantics of the disassembled instruction, such as list of implicit
+  registers read & written.
+
+- Implemented in pure C language, with lightweight wrappers for C++, C#, Go,
+  Java, Lua, NodeJS, Ocaml, Python, Ruby, Rust & Vala ready (available in
+  main code, or provided externally by the community).
+
+- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
+  Linux, *BSD, Solaris, etc.
+
+- Thread-safe by design.
+
+- Special support for embedding into firmware or OS kernel.
+
+- High performance & suitable for malware analysis (capable of handling various
+  X86 malware tricks).
+
+- Distributed under the open source BSD license.
+
+Further information is available at http://www.capstone-engine.org
+
+
+[Compile]
+
+See COMPILE.TXT file for how to compile and install Capstone.
+
+
+[Documentation]
+
+See docs/README for how to customize & program your own tools with Capstone.
+
+
+[Hack]
+
+See HACK.TXT file for the structuture of the source code.
+
+
+[License]
+
+This project is released under the BSD license. If you redistribute the binary
+or source code of Capstone, please attach file LICENSE.TXT with your products.

src/3rd-party/capstone/capstone/SStream.c

@@ -0,0 +1,166 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include <stdint.h>
+#include <stdarg.h>
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <libkern/libkern.h>
+#else
+#include <stdio.h>
+#endif
+#include <string.h>
+
+#include "SStream.h"
+#include "cs_priv.h"
+#include "myinttypes.h"
+#include "utils.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable: 4996) // disable MSVC's warning on strcpy()
+#endif
+
+void SStream_Init(SStream *ss)
+{
+	ss->index = 0;
+	ss->buffer[0] = '\0';
+}
+
+void SStream_concat0(SStream *ss, char *s)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int len = (unsigned int) strlen(s);
+
+	memcpy(ss->buffer + ss->index, s, len);
+	ss->index += len;
+	ss->buffer[ss->index] = '\0';
+#endif
+}
+
+void SStream_concat(SStream *ss, const char *fmt, ...)
+{
+#ifndef CAPSTONE_DIET
+	va_list ap;
+	int ret;
+
+	va_start(ap, fmt);
+	ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
+	va_end(ap);
+	ss->index += ret;
+#endif
+}
+
+// print number with prefix #
+void printInt64Bang(SStream *O, int64_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "#0x%"PRIx64, val);
+		else
+			SStream_concat(O, "#%"PRIu64, val);
+	} else {
+		if (val <- HEX_THRESHOLD)
+			SStream_concat(O, "#-0x%"PRIx64, -val);
+		else
+			SStream_concat(O, "#-%"PRIu64, -val);
+	}
+}
+
+void printUInt64Bang(SStream *O, uint64_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "#0x%"PRIx64, val);
+	else
+		SStream_concat(O, "#%"PRIu64, val);
+}
+
+// print number
+void printInt64(SStream *O, int64_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "0x%"PRIx64, val);
+		else
+			SStream_concat(O, "%"PRIu64, val);
+	} else {
+		if (val <- HEX_THRESHOLD)
+			SStream_concat(O, "-0x%"PRIx64, -val);
+		else
+			SStream_concat(O, "-%"PRIu64, -val);
+	}
+}
+
+// print number in decimal mode
+void printInt32BangDec(SStream *O, int32_t val)
+{
+	if (val >= 0)
+		SStream_concat(O, "#%u", val);
+	else
+		SStream_concat(O, "#-%u", -val);
+}
+
+void printInt32Bang(SStream *O, int32_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "#0x%x", val);
+		else
+			SStream_concat(O, "#%u", val);
+	} else {
+		if (val <- HEX_THRESHOLD)
+			SStream_concat(O, "#-0x%x", -val);
+		else
+			SStream_concat(O, "#-%u", -val);
+	}
+}
+
+void printInt32(SStream *O, int32_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "0x%x", val);
+		else
+			SStream_concat(O, "%u", val);
+	} else {
+		if (val <- HEX_THRESHOLD)
+			SStream_concat(O, "-0x%x", -val);
+		else
+			SStream_concat(O, "-%u", -val);
+	}
+}
+
+void printUInt32Bang(SStream *O, uint32_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "#0x%x", val);
+	else
+		SStream_concat(O, "#%u", val);
+}
+
+void printUInt32(SStream *O, uint32_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "0x%x", val);
+	else
+		SStream_concat(O, "%u", val);
+}
+
+/*
+   int main()
+   {
+   SStream ss;
+   int64_t i;
+
+   SStream_Init(&ss);
+
+   SStream_concat(&ss, "hello ");
+   SStream_concat(&ss, "%d - 0x%x", 200, 16);
+
+   i = 123;
+   SStream_concat(&ss, " + %ld", i);
+   SStream_concat(&ss, "%s", "haaaaa");
+
+   printf("%s\n", ss.buffer);
+
+   return 0;
+   }
+ */

src/3rd-party/capstone/capstone/SStream.h

@@ -0,0 +1,35 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_SSTREAM_H_
+#define CS_SSTREAM_H_
+
+typedef struct SStream {
+	char buffer[512];
+	int index;
+} SStream;
+
+void SStream_Init(SStream *ss);
+
+void SStream_concat(SStream *ss, const char *fmt, ...);
+
+void SStream_concat0(SStream *ss, char *s);
+
+void printInt64Bang(SStream *O, int64_t val);
+
+void printUInt64Bang(SStream *O, uint64_t val);
+
+void printInt64(SStream *O, int64_t val);
+
+void printInt32Bang(SStream *O, int32_t val);
+
+void printInt32(SStream *O, int32_t val);
+
+void printUInt32Bang(SStream *O, uint32_t val);
+
+void printUInt32(SStream *O, uint32_t val);
+
+// print number in decimal mode
+void printInt32BangDec(SStream *O, int32_t val);
+
+#endif

src/3rd-party/capstone/capstone/TODO

@@ -0,0 +1,16 @@
+Issues to be solved in next versions
+
+
+[Core]
+
+- X86 can already handle all the malware tricks we are aware of. If you find
+  any such instruction sequence that Capstone disassembles wrongly or fails
+  completely, please report. Fixing this issue is always the top priority of
+  our project.
+
+- More optimization for better performance.
+
+
+[Bindings]
+
+- OCaml binding is working, but still needs to support the core API better.

src/3rd-party/capstone/capstone/arch/AArch64/AArch64AddressingModes.h

@@ -0,0 +1,228 @@
+//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the AArch64 addressing mode implementation stuff.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_AARCH64_ADDRESSINGMODES_H
+#define CS_AARCH64_ADDRESSINGMODES_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+
+#include "../../MathExtras.h"
+
+/// AArch64_AM - AArch64 Addressing Mode Stuff
+
+//===----------------------------------------------------------------------===//
+// Shifts
+//
+
+typedef enum AArch64_AM_ShiftExtendType {
+	AArch64_AM_InvalidShiftExtend = -1,
+	AArch64_AM_LSL = 0,
+	AArch64_AM_LSR,
+	AArch64_AM_ASR,
+	AArch64_AM_ROR,
+	AArch64_AM_MSL,
+
+	AArch64_AM_UXTB,
+	AArch64_AM_UXTH,
+	AArch64_AM_UXTW,
+	AArch64_AM_UXTX,
+
+	AArch64_AM_SXTB,
+	AArch64_AM_SXTH,
+	AArch64_AM_SXTW,
+	AArch64_AM_SXTX,
+} AArch64_AM_ShiftExtendType;
+
+/// getShiftName - Get the string encoding for the shift type.
+static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
+{
+	switch (ST) {
+		default: return NULL; // never reach
+		case AArch64_AM_LSL: return "lsl";
+		case AArch64_AM_LSR: return "lsr";
+		case AArch64_AM_ASR: return "asr";
+		case AArch64_AM_ROR: return "ror";
+		case AArch64_AM_MSL: return "msl";
+		case AArch64_AM_UXTB: return "uxtb";
+		case AArch64_AM_UXTH: return "uxth";
+		case AArch64_AM_UXTW: return "uxtw";
+		case AArch64_AM_UXTX: return "uxtx";
+		case AArch64_AM_SXTB: return "sxtb";
+		case AArch64_AM_SXTH: return "sxth";
+		case AArch64_AM_SXTW: return "sxtw";
+		case AArch64_AM_SXTX: return "sxtx";
+	}
+}
+
+/// getShiftType - Extract the shift type.
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
+{
+	switch ((Imm >> 6) & 0x7) {
+		default: return AArch64_AM_InvalidShiftExtend;
+		case 0: return AArch64_AM_LSL;
+		case 1: return AArch64_AM_LSR;
+		case 2: return AArch64_AM_ASR;
+		case 3: return AArch64_AM_ROR;
+		case 4: return AArch64_AM_MSL;
+	}
+}
+
+/// getShiftValue - Extract the shift value.
+static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
+{
+	return Imm & 0x3f;
+}
+
+//===----------------------------------------------------------------------===//
+// Extends
+//
+
+/// getArithShiftValue - get the arithmetic shift value.
+static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
+{
+	return Imm & 0x7;
+}
+
+/// getExtendType - Extract the extend type for operands of arithmetic ops.
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
+{
+	// assert((Imm & 0x7) == Imm && "invalid immediate!");
+	switch (Imm) {
+		default: // llvm_unreachable("Compiler bug!");
+		case 0: return AArch64_AM_UXTB;
+		case 1: return AArch64_AM_UXTH;
+		case 2: return AArch64_AM_UXTW;
+		case 3: return AArch64_AM_UXTX;
+		case 4: return AArch64_AM_SXTB;
+		case 5: return AArch64_AM_SXTH;
+		case 6: return AArch64_AM_SXTW;
+		case 7: return AArch64_AM_SXTX;
+	}
+}
+
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm)
+{
+	return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
+}
+
+static inline uint64_t ror(uint64_t elt, unsigned size)
+{
+	return ((elt & 1) << (size-1)) | (elt >> 1);
+}
+
+/// decodeLogicalImmediate - Decode a logical immediate value in the form
+/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
+/// integer value it represents with regSize bits.
+static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize)
+{
+	// Extract the N, imms, and immr fields.
+	unsigned N = (val >> 12) & 1;
+	unsigned immr = (val >> 6) & 0x3f;
+	unsigned imms = val & 0x3f;
+	unsigned i;
+
+	// assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
+	int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+	// assert(len >= 0 && "undefined logical immediate encoding");
+	unsigned size = (1 << len);
+	unsigned R = immr & (size - 1);
+	unsigned S = imms & (size - 1);
+	// assert(S != size - 1 && "undefined logical immediate encoding");
+	uint64_t pattern = (1ULL << (S + 1)) - 1;
+	for (i = 0; i < R; ++i)
+		pattern = ror(pattern, size);
+
+	// Replicate the pattern to fill the regSize.
+	while (size != regSize) {
+		pattern |= (pattern << size);
+		size *= 2;
+	}
+
+	return pattern;
+}
+
+/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
+/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
+/// is a valid encoding for an integer value with regSize bits.
+static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
+{
+	unsigned size;
+	unsigned S;
+	int len;
+	// Extract the N and imms fields needed for checking.
+	unsigned N = (val >> 12) & 1;
+	unsigned imms = val & 0x3f;
+
+	if (regSize == 32 && N != 0) // undefined logical immediate encoding
+		return false;
+	len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+	if (len < 0) // undefined logical immediate encoding
+		return false;
+	size = (1 << len);
+	S = imms & (size - 1);
+	if (S == size - 1) // undefined logical immediate encoding
+		return false;
+
+	return true;
+}
+
+//===----------------------------------------------------------------------===//
+// Floating-point Immediates
+//
+static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
+{
+	// We expect an 8-bit binary encoding of a floating-point number here.
+	union {
+		uint32_t I;
+		float F;
+	} FPUnion;
+
+	uint8_t Sign = (Imm >> 7) & 0x1;
+	uint8_t Exp = (Imm >> 4) & 0x7;
+	uint8_t Mantissa = Imm & 0xf;
+
+	//   8-bit FP    iEEEE Float Encoding
+	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
+	//
+	// where B = NOT(b);
+
+	FPUnion.I = 0;
+	FPUnion.I |= Sign << 31;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	FPUnion.I |= (Exp & 0x3) << 23;
+	FPUnion.I |= Mantissa << 19;
+
+	return FPUnion.F;
+}
+
+//===--------------------------------------------------------------------===//
+// AdvSIMD Modified Immediates
+//===--------------------------------------------------------------------===//
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
+{
+	uint64_t EncVal = 0;
+	if (Imm & 0x80) EncVal |= 0xff00000000000000ULL;
+	if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL;
+	if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL;
+	if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL;
+	if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL;
+	if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL;
+	if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL;
+	if (Imm & 0x01) EncVal |= 0x00000000000000ffULL;
+	return EncVal;
+}
+
+#endif

src/3rd-party/capstone/capstone/arch/AArch64/AArch64BaseInfo.c

@@ -0,0 +1,944 @@
+//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for AArch64.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_ARM64
+
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#pragma warning(disable:4996)
+#endif
+
+#include "../../utils.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "AArch64BaseInfo.h"
+
+char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid)
+{
+	unsigned i;
+	for (i = 0; i < N->NumPairs; ++i) {
+		if (N->Pairs[i].Value == Value) {
+			*Valid = true;
+			return N->Pairs[i].Name;
+		}
+	}
+
+	*Valid = false;
+	return 0;
+}
+
+// compare s1 with lower(s2)
+// return true if s1 == lower(f2), and false otherwise
+static bool compare_lower_str(char *s1, char *s2)
+{
+	bool res;
+	char *lower = cs_strdup(s2), *c;
+	for (c = lower; *c; c++)
+		*c = (char)tolower((int) *c);
+
+	res = (strcmp(s1, lower) == 0);
+	cs_mem_free(lower);
+
+	return res;
+}
+
+uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid)
+{
+	unsigned i;
+	for (i = 0; i < N->NumPairs; ++i) {
+		if (compare_lower_str(N->Pairs[i].Name, Name)) {
+			*Valid = true;
+			return N->Pairs[i].Value;
+		}
+	}
+
+	*Valid = false;
+	return (uint32_t)-1;
+}
+
+bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value)
+{
+	return Value < N->TooBigImm;
+}
+
+// return a string representing the number X
+// NOTE: caller must free() the result itself to avoid memory leak
+static char *utostr(uint64_t X, bool isNeg)
+{
+	char Buffer[22];
+	char *BufPtr = Buffer+21;
+	char *result;
+
+	Buffer[21] = '\0';
+	if (X == 0) *--BufPtr = '0';  // Handle special case...
+
+	while (X) {
+		*--BufPtr = X % 10 + '0';
+		X /= 10;
+	}
+
+	if (isNeg) *--BufPtr = '-';   // Add negative sign...
+
+	result = cs_strdup(BufPtr);
+	return result;
+}
+
+static A64NamedImmMapper_Mapping SysRegPairs[] = {
+	{"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
+	{"osdtrtx_el1",  A64SysReg_OSDTRTX_EL1},
+	{"teecr32_el1", A64SysReg_TEECR32_EL1},
+	{"mdccint_el1", A64SysReg_MDCCINT_EL1},
+	{"mdscr_el1", A64SysReg_MDSCR_EL1},
+	{"dbgdtr_el0", A64SysReg_DBGDTR_EL0},
+	{"oseccr_el1", A64SysReg_OSECCR_EL1},
+	{"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2},
+	{"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1},
+	{"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1},
+	{"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1},
+	{"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1},
+	{"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1},
+	{"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1},
+	{"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1},
+	{"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1},
+	{"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1},
+	{"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1},
+	{"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1},
+	{"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1},
+	{"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1},
+	{"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1},
+	{"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1},
+	{"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1},
+	{"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1},
+	{"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1},
+	{"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1},
+	{"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1},
+	{"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1},
+	{"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1},
+	{"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1},
+	{"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1},
+	{"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1},
+	{"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1},
+	{"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1},
+	{"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1},
+	{"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1},
+	{"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1},
+	{"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1},
+	{"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1},
+	{"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1},
+	{"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1},
+	{"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1},
+	{"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1},
+	{"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1},
+	{"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1},
+	{"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1},
+	{"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1},
+	{"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1},
+	{"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1},
+	{"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1},
+	{"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1},
+	{"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1},
+	{"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1},
+	{"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1},
+	{"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1},
+	{"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1},
+	{"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1},
+	{"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1},
+	{"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1},
+	{"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1},
+	{"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1},
+	{"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1},
+	{"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1},
+	{"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1},
+	{"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1},
+	{"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1},
+	{"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1},
+	{"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1},
+	{"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1},
+	{"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1},
+	{"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1},
+	{"teehbr32_el1", A64SysReg_TEEHBR32_EL1},
+	{"osdlr_el1", A64SysReg_OSDLR_EL1},
+	{"dbgprcr_el1", A64SysReg_DBGPRCR_EL1},
+	{"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1},
+	{"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1},
+	{"csselr_el1", A64SysReg_CSSELR_EL1},
+	{"vpidr_el2", A64SysReg_VPIDR_EL2},
+	{"vmpidr_el2", A64SysReg_VMPIDR_EL2},
+	{"sctlr_el1", A64SysReg_SCTLR_EL1},
+	{"sctlr_el2", A64SysReg_SCTLR_EL2},
+	{"sctlr_el3", A64SysReg_SCTLR_EL3},
+	{"actlr_el1", A64SysReg_ACTLR_EL1},
+	{"actlr_el2", A64SysReg_ACTLR_EL2},
+	{"actlr_el3", A64SysReg_ACTLR_EL3},
+	{"cpacr_el1", A64SysReg_CPACR_EL1},
+	{"hcr_el2", A64SysReg_HCR_EL2},
+	{"scr_el3", A64SysReg_SCR_EL3},
+	{"mdcr_el2", A64SysReg_MDCR_EL2},
+	{"sder32_el3", A64SysReg_SDER32_EL3},
+	{"cptr_el2", A64SysReg_CPTR_EL2},
+	{"cptr_el3", A64SysReg_CPTR_EL3},
+	{"hstr_el2", A64SysReg_HSTR_EL2},
+	{"hacr_el2", A64SysReg_HACR_EL2},
+	{"mdcr_el3", A64SysReg_MDCR_EL3},
+	{"ttbr0_el1", A64SysReg_TTBR0_EL1},
+	{"ttbr0_el2", A64SysReg_TTBR0_EL2},
+	{"ttbr0_el3", A64SysReg_TTBR0_EL3},
+	{"ttbr1_el1", A64SysReg_TTBR1_EL1},
+	{"tcr_el1", A64SysReg_TCR_EL1},
+	{"tcr_el2", A64SysReg_TCR_EL2},
+	{"tcr_el3", A64SysReg_TCR_EL3},
+	{"vttbr_el2", A64SysReg_VTTBR_EL2},
+	{"vtcr_el2", A64SysReg_VTCR_EL2},
+	{"dacr32_el2", A64SysReg_DACR32_EL2},
+	{"spsr_el1", A64SysReg_SPSR_EL1},
+	{"spsr_el2", A64SysReg_SPSR_EL2},
+	{"spsr_el3", A64SysReg_SPSR_EL3},
+	{"elr_el1", A64SysReg_ELR_EL1},
+	{"elr_el2", A64SysReg_ELR_EL2},
+	{"elr_el3", A64SysReg_ELR_EL3},
+	{"sp_el0", A64SysReg_SP_EL0},
+	{"sp_el1", A64SysReg_SP_EL1},
+	{"sp_el2", A64SysReg_SP_EL2},
+	{"spsel", A64SysReg_SPSel},
+	{"nzcv", A64SysReg_NZCV},
+	{"daif", A64SysReg_DAIF},
+	{"currentel", A64SysReg_CurrentEL},
+	{"spsr_irq", A64SysReg_SPSR_irq},
+	{"spsr_abt", A64SysReg_SPSR_abt},
+	{"spsr_und", A64SysReg_SPSR_und},
+	{"spsr_fiq", A64SysReg_SPSR_fiq},
+	{"fpcr", A64SysReg_FPCR},
+	{"fpsr", A64SysReg_FPSR},
+	{"dspsr_el0", A64SysReg_DSPSR_EL0},
+	{"dlr_el0", A64SysReg_DLR_EL0},
+	{"ifsr32_el2", A64SysReg_IFSR32_EL2},
+	{"afsr0_el1", A64SysReg_AFSR0_EL1},
+	{"afsr0_el2", A64SysReg_AFSR0_EL2},
+	{"afsr0_el3", A64SysReg_AFSR0_EL3},
+	{"afsr1_el1", A64SysReg_AFSR1_EL1},
+	{"afsr1_el2", A64SysReg_AFSR1_EL2},
+	{"afsr1_el3", A64SysReg_AFSR1_EL3},
+	{"esr_el1", A64SysReg_ESR_EL1},
+	{"esr_el2", A64SysReg_ESR_EL2},
+	{"esr_el3", A64SysReg_ESR_EL3},
+	{"fpexc32_el2", A64SysReg_FPEXC32_EL2},
+	{"far_el1", A64SysReg_FAR_EL1},
+	{"far_el2", A64SysReg_FAR_EL2},
+	{"far_el3", A64SysReg_FAR_EL3},
+	{"hpfar_el2", A64SysReg_HPFAR_EL2},
+	{"par_el1", A64SysReg_PAR_EL1},
+	{"pmcr_el0", A64SysReg_PMCR_EL0},
+	{"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0},
+	{"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0},
+	{"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0},
+	{"pmselr_el0", A64SysReg_PMSELR_EL0},
+	{"pmccntr_el0", A64SysReg_PMCCNTR_EL0},
+	{"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0},
+	{"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0},
+	{"pmuserenr_el0", A64SysReg_PMUSERENR_EL0},
+	{"pmintenset_el1", A64SysReg_PMINTENSET_EL1},
+	{"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
+	{"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
+	{"mair_el1", A64SysReg_MAIR_EL1},
+	{"mair_el2", A64SysReg_MAIR_EL2},
+	{"mair_el3", A64SysReg_MAIR_EL3},
+	{"amair_el1", A64SysReg_AMAIR_EL1},
+	{"amair_el2", A64SysReg_AMAIR_EL2},
+	{"amair_el3", A64SysReg_AMAIR_EL3},
+	{"vbar_el1", A64SysReg_VBAR_EL1},
+	{"vbar_el2", A64SysReg_VBAR_EL2},
+	{"vbar_el3", A64SysReg_VBAR_EL3},
+	{"rmr_el1", A64SysReg_RMR_EL1},
+	{"rmr_el2", A64SysReg_RMR_EL2},
+	{"rmr_el3", A64SysReg_RMR_EL3},
+	{"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
+	{"tpidr_el0", A64SysReg_TPIDR_EL0},
+	{"tpidr_el2", A64SysReg_TPIDR_EL2},
+	{"tpidr_el3", A64SysReg_TPIDR_EL3},
+	{"tpidrro_el0", A64SysReg_TPIDRRO_EL0},
+	{"tpidr_el1", A64SysReg_TPIDR_EL1},
+	{"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
+	{"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
+	{"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
+	{"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
+	{"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
+	{"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
+	{"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
+	{"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
+	{"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
+	{"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
+	{"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
+	{"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
+	{"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
+	{"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
+	{"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
+	{"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
+	{"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
+	{"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
+	{"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
+	{"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0},
+	{"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0},
+	{"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0},
+	{"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0},
+	{"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0},
+	{"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0},
+	{"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0},
+	{"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0},
+	{"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0},
+	{"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0},
+	{"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0},
+	{"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0},
+	{"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0},
+	{"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0},
+	{"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0},
+	{"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0},
+	{"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0},
+	{"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0},
+	{"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0},
+	{"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0},
+	{"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0},
+	{"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0},
+	{"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0},
+	{"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0},
+	{"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0},
+	{"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0},
+	{"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0},
+	{"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0},
+	{"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0},
+	{"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0},
+	{"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0},
+	{"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0},
+	{"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0},
+	{"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0},
+	{"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0},
+	{"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0},
+	{"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0},
+	{"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0},
+	{"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0},
+	{"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0},
+	{"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0},
+	{"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0},
+	{"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0},
+	{"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0},
+	{"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0},
+	{"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0},
+	{"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0},
+	{"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0},
+	{"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0},
+	{"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0},
+	{"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0},
+	{"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0},
+	{"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0},
+	{"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0},
+	{"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0},
+	{"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0},
+	{"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0},
+	{"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
+	{"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
+	{"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
+
+	// Trace registers
+	{"trcprgctlr", A64SysReg_TRCPRGCTLR},
+	{"trcprocselr", A64SysReg_TRCPROCSELR},
+	{"trcconfigr", A64SysReg_TRCCONFIGR},
+	{"trcauxctlr", A64SysReg_TRCAUXCTLR},
+	{"trceventctl0r", A64SysReg_TRCEVENTCTL0R},
+	{"trceventctl1r", A64SysReg_TRCEVENTCTL1R},
+	{"trcstallctlr", A64SysReg_TRCSTALLCTLR},
+	{"trctsctlr", A64SysReg_TRCTSCTLR},
+	{"trcsyncpr", A64SysReg_TRCSYNCPR},
+	{"trcccctlr", A64SysReg_TRCCCCTLR},
+	{"trcbbctlr", A64SysReg_TRCBBCTLR},
+	{"trctraceidr", A64SysReg_TRCTRACEIDR},
+	{"trcqctlr", A64SysReg_TRCQCTLR},
+	{"trcvictlr", A64SysReg_TRCVICTLR},
+	{"trcviiectlr", A64SysReg_TRCVIIECTLR},
+	{"trcvissctlr", A64SysReg_TRCVISSCTLR},
+	{"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR},
+	{"trcvdctlr", A64SysReg_TRCVDCTLR},
+	{"trcvdsacctlr", A64SysReg_TRCVDSACCTLR},
+	{"trcvdarcctlr", A64SysReg_TRCVDARCCTLR},
+	{"trcseqevr0", A64SysReg_TRCSEQEVR0},
+	{"trcseqevr1", A64SysReg_TRCSEQEVR1},
+	{"trcseqevr2", A64SysReg_TRCSEQEVR2},
+	{"trcseqrstevr", A64SysReg_TRCSEQRSTEVR},
+	{"trcseqstr", A64SysReg_TRCSEQSTR},
+	{"trcextinselr", A64SysReg_TRCEXTINSELR},
+	{"trccntrldvr0", A64SysReg_TRCCNTRLDVR0},
+	{"trccntrldvr1", A64SysReg_TRCCNTRLDVR1},
+	{"trccntrldvr2", A64SysReg_TRCCNTRLDVR2},
+	{"trccntrldvr3", A64SysReg_TRCCNTRLDVR3},
+	{"trccntctlr0", A64SysReg_TRCCNTCTLR0},
+	{"trccntctlr1", A64SysReg_TRCCNTCTLR1},
+	{"trccntctlr2", A64SysReg_TRCCNTCTLR2},
+	{"trccntctlr3", A64SysReg_TRCCNTCTLR3},
+	{"trccntvr0", A64SysReg_TRCCNTVR0},
+	{"trccntvr1", A64SysReg_TRCCNTVR1},
+	{"trccntvr2", A64SysReg_TRCCNTVR2},
+	{"trccntvr3", A64SysReg_TRCCNTVR3},
+	{"trcimspec0", A64SysReg_TRCIMSPEC0},
+	{"trcimspec1", A64SysReg_TRCIMSPEC1},
+	{"trcimspec2", A64SysReg_TRCIMSPEC2},
+	{"trcimspec3", A64SysReg_TRCIMSPEC3},
+	{"trcimspec4", A64SysReg_TRCIMSPEC4},
+	{"trcimspec5", A64SysReg_TRCIMSPEC5},
+	{"trcimspec6", A64SysReg_TRCIMSPEC6},
+	{"trcimspec7", A64SysReg_TRCIMSPEC7},
+	{"trcrsctlr2", A64SysReg_TRCRSCTLR2},
+	{"trcrsctlr3", A64SysReg_TRCRSCTLR3},
+	{"trcrsctlr4", A64SysReg_TRCRSCTLR4},
+	{"trcrsctlr5", A64SysReg_TRCRSCTLR5},
+	{"trcrsctlr6", A64SysReg_TRCRSCTLR6},
+	{"trcrsctlr7", A64SysReg_TRCRSCTLR7},
+	{"trcrsctlr8", A64SysReg_TRCRSCTLR8},
+	{"trcrsctlr9", A64SysReg_TRCRSCTLR9},
+	{"trcrsctlr10", A64SysReg_TRCRSCTLR10},
+	{"trcrsctlr11", A64SysReg_TRCRSCTLR11},
+	{"trcrsctlr12", A64SysReg_TRCRSCTLR12},
+	{"trcrsctlr13", A64SysReg_TRCRSCTLR13},
+	{"trcrsctlr14", A64SysReg_TRCRSCTLR14},
+	{"trcrsctlr15", A64SysReg_TRCRSCTLR15},
+	{"trcrsctlr16", A64SysReg_TRCRSCTLR16},
+	{"trcrsctlr17", A64SysReg_TRCRSCTLR17},
+	{"trcrsctlr18", A64SysReg_TRCRSCTLR18},
+	{"trcrsctlr19", A64SysReg_TRCRSCTLR19},
+	{"trcrsctlr20", A64SysReg_TRCRSCTLR20},
+	{"trcrsctlr21", A64SysReg_TRCRSCTLR21},
+	{"trcrsctlr22", A64SysReg_TRCRSCTLR22},
+	{"trcrsctlr23", A64SysReg_TRCRSCTLR23},
+	{"trcrsctlr24", A64SysReg_TRCRSCTLR24},
+	{"trcrsctlr25", A64SysReg_TRCRSCTLR25},
+	{"trcrsctlr26", A64SysReg_TRCRSCTLR26},
+	{"trcrsctlr27", A64SysReg_TRCRSCTLR27},
+	{"trcrsctlr28", A64SysReg_TRCRSCTLR28},
+	{"trcrsctlr29", A64SysReg_TRCRSCTLR29},
+	{"trcrsctlr30", A64SysReg_TRCRSCTLR30},
+	{"trcrsctlr31", A64SysReg_TRCRSCTLR31},
+	{"trcssccr0", A64SysReg_TRCSSCCR0},
+	{"trcssccr1", A64SysReg_TRCSSCCR1},
+	{"trcssccr2", A64SysReg_TRCSSCCR2},
+	{"trcssccr3", A64SysReg_TRCSSCCR3},
+	{"trcssccr4", A64SysReg_TRCSSCCR4},
+	{"trcssccr5", A64SysReg_TRCSSCCR5},
+	{"trcssccr6", A64SysReg_TRCSSCCR6},
+	{"trcssccr7", A64SysReg_TRCSSCCR7},
+	{"trcsscsr0", A64SysReg_TRCSSCSR0},
+	{"trcsscsr1", A64SysReg_TRCSSCSR1},
+	{"trcsscsr2", A64SysReg_TRCSSCSR2},
+	{"trcsscsr3", A64SysReg_TRCSSCSR3},
+	{"trcsscsr4", A64SysReg_TRCSSCSR4},
+	{"trcsscsr5", A64SysReg_TRCSSCSR5},
+	{"trcsscsr6", A64SysReg_TRCSSCSR6},
+	{"trcsscsr7", A64SysReg_TRCSSCSR7},
+	{"trcsspcicr0", A64SysReg_TRCSSPCICR0},
+	{"trcsspcicr1", A64SysReg_TRCSSPCICR1},
+	{"trcsspcicr2", A64SysReg_TRCSSPCICR2},
+	{"trcsspcicr3", A64SysReg_TRCSSPCICR3},
+	{"trcsspcicr4", A64SysReg_TRCSSPCICR4},
+	{"trcsspcicr5", A64SysReg_TRCSSPCICR5},
+	{"trcsspcicr6", A64SysReg_TRCSSPCICR6},
+	{"trcsspcicr7", A64SysReg_TRCSSPCICR7},
+	{"trcpdcr", A64SysReg_TRCPDCR},
+	{"trcacvr0", A64SysReg_TRCACVR0},
+	{"trcacvr1", A64SysReg_TRCACVR1},
+	{"trcacvr2", A64SysReg_TRCACVR2},
+	{"trcacvr3", A64SysReg_TRCACVR3},
+	{"trcacvr4", A64SysReg_TRCACVR4},
+	{"trcacvr5", A64SysReg_TRCACVR5},
+	{"trcacvr6", A64SysReg_TRCACVR6},
+	{"trcacvr7", A64SysReg_TRCACVR7},
+	{"trcacvr8", A64SysReg_TRCACVR8},
+	{"trcacvr9", A64SysReg_TRCACVR9},
+	{"trcacvr10", A64SysReg_TRCACVR10},
+	{"trcacvr11", A64SysReg_TRCACVR11},
+	{"trcacvr12", A64SysReg_TRCACVR12},
+	{"trcacvr13", A64SysReg_TRCACVR13},
+	{"trcacvr14", A64SysReg_TRCACVR14},
+	{"trcacvr15", A64SysReg_TRCACVR15},
+	{"trcacatr0", A64SysReg_TRCACATR0},
+	{"trcacatr1", A64SysReg_TRCACATR1},
+	{"trcacatr2", A64SysReg_TRCACATR2},
+	{"trcacatr3", A64SysReg_TRCACATR3},
+	{"trcacatr4", A64SysReg_TRCACATR4},
+	{"trcacatr5", A64SysReg_TRCACATR5},
+	{"trcacatr6", A64SysReg_TRCACATR6},
+	{"trcacatr7", A64SysReg_TRCACATR7},
+	{"trcacatr8", A64SysReg_TRCACATR8},
+	{"trcacatr9", A64SysReg_TRCACATR9},
+	{"trcacatr10", A64SysReg_TRCACATR10},
+	{"trcacatr11", A64SysReg_TRCACATR11},
+	{"trcacatr12", A64SysReg_TRCACATR12},
+	{"trcacatr13", A64SysReg_TRCACATR13},
+	{"trcacatr14", A64SysReg_TRCACATR14},
+	{"trcacatr15", A64SysReg_TRCACATR15},
+	{"trcdvcvr0", A64SysReg_TRCDVCVR0},
+	{"trcdvcvr1", A64SysReg_TRCDVCVR1},
+	{"trcdvcvr2", A64SysReg_TRCDVCVR2},
+	{"trcdvcvr3", A64SysReg_TRCDVCVR3},
+	{"trcdvcvr4", A64SysReg_TRCDVCVR4},
+	{"trcdvcvr5", A64SysReg_TRCDVCVR5},
+	{"trcdvcvr6", A64SysReg_TRCDVCVR6},
+	{"trcdvcvr7", A64SysReg_TRCDVCVR7},
+	{"trcdvcmr0", A64SysReg_TRCDVCMR0},
+	{"trcdvcmr1", A64SysReg_TRCDVCMR1},
+	{"trcdvcmr2", A64SysReg_TRCDVCMR2},
+	{"trcdvcmr3", A64SysReg_TRCDVCMR3},
+	{"trcdvcmr4", A64SysReg_TRCDVCMR4},
+	{"trcdvcmr5", A64SysReg_TRCDVCMR5},
+	{"trcdvcmr6", A64SysReg_TRCDVCMR6},
+	{"trcdvcmr7", A64SysReg_TRCDVCMR7},
+	{"trccidcvr0", A64SysReg_TRCCIDCVR0},
+	{"trccidcvr1", A64SysReg_TRCCIDCVR1},
+	{"trccidcvr2", A64SysReg_TRCCIDCVR2},
+	{"trccidcvr3", A64SysReg_TRCCIDCVR3},
+	{"trccidcvr4", A64SysReg_TRCCIDCVR4},
+	{"trccidcvr5", A64SysReg_TRCCIDCVR5},
+	{"trccidcvr6", A64SysReg_TRCCIDCVR6},
+	{"trccidcvr7", A64SysReg_TRCCIDCVR7},
+	{"trcvmidcvr0", A64SysReg_TRCVMIDCVR0},
+	{"trcvmidcvr1", A64SysReg_TRCVMIDCVR1},
+	{"trcvmidcvr2", A64SysReg_TRCVMIDCVR2},
+	{"trcvmidcvr3", A64SysReg_TRCVMIDCVR3},
+	{"trcvmidcvr4", A64SysReg_TRCVMIDCVR4},
+	{"trcvmidcvr5", A64SysReg_TRCVMIDCVR5},
+	{"trcvmidcvr6", A64SysReg_TRCVMIDCVR6},
+	{"trcvmidcvr7", A64SysReg_TRCVMIDCVR7},
+	{"trccidcctlr0", A64SysReg_TRCCIDCCTLR0},
+	{"trccidcctlr1", A64SysReg_TRCCIDCCTLR1},
+	{"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0},
+	{"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1},
+	{"trcitctrl", A64SysReg_TRCITCTRL},
+	{"trcclaimset", A64SysReg_TRCCLAIMSET},
+	{"trcclaimclr", A64SysReg_TRCCLAIMCLR},
+
+	// GICv3 registers
+	{"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1},
+	{"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1},
+	{"icc_pmr_el1", A64SysReg_ICC_PMR_EL1},
+	{"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1},
+	{"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3},
+	{"icc_sre_el1", A64SysReg_ICC_SRE_EL1},
+	{"icc_sre_el2", A64SysReg_ICC_SRE_EL2},
+	{"icc_sre_el3", A64SysReg_ICC_SRE_EL3},
+	{"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1},
+	{"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1},
+	{"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3},
+	{"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1},
+	{"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1},
+	{"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1},
+	{"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1},
+	{"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1},
+	{"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1},
+	{"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1},
+	{"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1},
+	{"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1},
+	{"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2},
+	{"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2},
+	{"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2},
+	{"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2},
+	{"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2},
+	{"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2},
+	{"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2},
+	{"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2},
+	{"ich_hcr_el2", A64SysReg_ICH_HCR_EL2},
+	{"ich_misr_el2", A64SysReg_ICH_MISR_EL2},
+	{"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2},
+	{"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2},
+	{"ich_lr0_el2", A64SysReg_ICH_LR0_EL2},
+	{"ich_lr1_el2", A64SysReg_ICH_LR1_EL2},
+	{"ich_lr2_el2", A64SysReg_ICH_LR2_EL2},
+	{"ich_lr3_el2", A64SysReg_ICH_LR3_EL2},
+	{"ich_lr4_el2", A64SysReg_ICH_LR4_EL2},
+	{"ich_lr5_el2", A64SysReg_ICH_LR5_EL2},
+	{"ich_lr6_el2", A64SysReg_ICH_LR6_EL2},
+	{"ich_lr7_el2", A64SysReg_ICH_LR7_EL2},
+	{"ich_lr8_el2", A64SysReg_ICH_LR8_EL2},
+	{"ich_lr9_el2", A64SysReg_ICH_LR9_EL2},
+	{"ich_lr10_el2", A64SysReg_ICH_LR10_EL2},
+	{"ich_lr11_el2", A64SysReg_ICH_LR11_EL2},
+	{"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
+	{"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
+	{"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
+	{"ich_lr15_el2", A64SysReg_ICH_LR15_EL2}
+};
+
+static A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
+	{"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3}
+};
+
+// result must be a big enough buffer: 128 bytes is more than enough
+void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
+{
+	int dummy;
+	uint32_t Op0, Op1, CRn, CRm, Op2;
+	char *Op1S, *CRnS, *CRmS, *Op2S;
+	unsigned i;
+
+	// First search the registers shared by all
+	for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
+		if (SysRegPairs[i].Value == Bits) {
+			*Valid = true;
+			strcpy(result, SysRegPairs[i].Name);
+			return;
+		}
+	}
+
+	// Next search for target specific registers
+	// if (FeatureBits & AArch64_ProcCyclone) {
+	if (true) {
+		for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) {
+			if (CycloneSysRegPairs[i].Value == Bits) {
+				*Valid = true;
+				strcpy(result, CycloneSysRegPairs[i].Name);
+				return;
+			}
+		}
+	}
+
+	// Now try the instruction-specific registers (either read-only or
+	// write-only).
+	for (i = 0; i < S->NumInstPairs; ++i) {
+		if (S->InstPairs[i].Value == Bits) {
+			*Valid = true;
+			strcpy(result, S->InstPairs[i].Name);
+			return;
+		}
+	}
+
+	Op0 = (Bits >> 14) & 0x3;
+	Op1 = (Bits >> 11) & 0x7;
+	CRn = (Bits >> 7) & 0xf;
+	CRm = (Bits >> 3) & 0xf;
+	Op2 = Bits & 0x7;
+
+	// Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
+	// name.
+	if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
+		*Valid = false;
+		return;
+	}
+
+	//assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
+
+	*Valid = true;
+
+	Op1S = utostr(Op1, false);
+	CRnS = utostr(CRn, false);
+	CRmS = utostr(CRm, false);
+	Op2S = utostr(Op2, false);
+
+	//printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
+	dummy = sprintf(result, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
+	(void)dummy;
+
+	cs_mem_free(Op1S);
+	cs_mem_free(CRnS);
+	cs_mem_free(CRmS);
+	cs_mem_free(Op2S);
+}
+
+static A64NamedImmMapper_Mapping TLBIPairs[] = {
+	{"ipas2e1is", A64TLBI_IPAS2E1IS},
+	{"ipas2le1is", A64TLBI_IPAS2LE1IS},
+	{"vmalle1is", A64TLBI_VMALLE1IS},
+	{"alle2is", A64TLBI_ALLE2IS},
+	{"alle3is", A64TLBI_ALLE3IS},
+	{"vae1is", A64TLBI_VAE1IS},
+	{"vae2is", A64TLBI_VAE2IS},
+	{"vae3is", A64TLBI_VAE3IS},
+	{"aside1is", A64TLBI_ASIDE1IS},
+	{"vaae1is", A64TLBI_VAAE1IS},
+	{"alle1is", A64TLBI_ALLE1IS},
+	{"vale1is", A64TLBI_VALE1IS},
+	{"vale2is", A64TLBI_VALE2IS},
+	{"vale3is", A64TLBI_VALE3IS},
+	{"vmalls12e1is", A64TLBI_VMALLS12E1IS},
+	{"vaale1is", A64TLBI_VAALE1IS},
+	{"ipas2e1", A64TLBI_IPAS2E1},
+	{"ipas2le1", A64TLBI_IPAS2LE1},
+	{"vmalle1", A64TLBI_VMALLE1},
+	{"alle2", A64TLBI_ALLE2},
+	{"alle3", A64TLBI_ALLE3},
+	{"vae1", A64TLBI_VAE1},
+	{"vae2", A64TLBI_VAE2},
+	{"vae3", A64TLBI_VAE3},
+	{"aside1", A64TLBI_ASIDE1},
+	{"vaae1", A64TLBI_VAAE1},
+	{"alle1", A64TLBI_ALLE1},
+	{"vale1", A64TLBI_VALE1},
+	{"vale2", A64TLBI_VALE2},
+	{"vale3", A64TLBI_VALE3},
+	{"vmalls12e1", A64TLBI_VMALLS12E1},
+	{"vaale1", A64TLBI_VAALE1}
+};
+
+A64NamedImmMapper A64TLBI_TLBIMapper = {
+	TLBIPairs,
+	ARR_SIZE(TLBIPairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping ATPairs[] = {
+	{"s1e1r", A64AT_S1E1R},
+	{"s1e2r", A64AT_S1E2R},
+	{"s1e3r", A64AT_S1E3R},
+	{"s1e1w", A64AT_S1E1W},
+	{"s1e2w", A64AT_S1E2W},
+	{"s1e3w", A64AT_S1E3W},
+	{"s1e0r", A64AT_S1E0R},
+	{"s1e0w", A64AT_S1E0W},
+	{"s12e1r", A64AT_S12E1R},
+	{"s12e1w", A64AT_S12E1W},
+	{"s12e0r", A64AT_S12E0R},
+	{"s12e0w", A64AT_S12E0W},
+};
+
+A64NamedImmMapper A64AT_ATMapper = {
+	ATPairs,
+	ARR_SIZE(ATPairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping DBarrierPairs[] = {
+	{"oshld", A64DB_OSHLD},
+	{"oshst", A64DB_OSHST},
+	{"osh", A64DB_OSH},
+	{"nshld", A64DB_NSHLD},
+	{"nshst", A64DB_NSHST},
+	{"nsh", A64DB_NSH},
+	{"ishld", A64DB_ISHLD},
+	{"ishst", A64DB_ISHST},
+	{"ish", A64DB_ISH},
+	{"ld", A64DB_LD},
+	{"st", A64DB_ST},
+	{"sy", A64DB_SY}
+};
+
+A64NamedImmMapper A64DB_DBarrierMapper = {
+	DBarrierPairs,
+	ARR_SIZE(DBarrierPairs),
+	16,
+};
+
+static A64NamedImmMapper_Mapping DCPairs[] = {
+	{"zva", A64DC_ZVA},
+	{"ivac", A64DC_IVAC},
+	{"isw", A64DC_ISW},
+	{"cvac", A64DC_CVAC},
+	{"csw", A64DC_CSW},
+	{"cvau", A64DC_CVAU},
+	{"civac", A64DC_CIVAC},
+	{"cisw", A64DC_CISW}
+};
+
+A64NamedImmMapper A64DC_DCMapper = {
+	DCPairs,
+	ARR_SIZE(DCPairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping ICPairs[] = {
+	{"ialluis",  A64IC_IALLUIS},
+	{"iallu", A64IC_IALLU},
+	{"ivau", A64IC_IVAU}
+};
+
+A64NamedImmMapper A64IC_ICMapper = {
+	ICPairs,
+	ARR_SIZE(ICPairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping ISBPairs[] = {
+	{"sy",  A64DB_SY},
+};
+
+A64NamedImmMapper A64ISB_ISBMapper = {
+	ISBPairs,
+	ARR_SIZE(ISBPairs),
+	16,
+};
+
+static A64NamedImmMapper_Mapping PRFMPairs[] = {
+	{"pldl1keep", A64PRFM_PLDL1KEEP},
+	{"pldl1strm", A64PRFM_PLDL1STRM},
+	{"pldl2keep", A64PRFM_PLDL2KEEP},
+	{"pldl2strm", A64PRFM_PLDL2STRM},
+	{"pldl3keep", A64PRFM_PLDL3KEEP},
+	{"pldl3strm", A64PRFM_PLDL3STRM},
+	{"plil1keep", A64PRFM_PLIL1KEEP},
+	{"plil1strm", A64PRFM_PLIL1STRM},
+	{"plil2keep", A64PRFM_PLIL2KEEP},
+	{"plil2strm", A64PRFM_PLIL2STRM},
+	{"plil3keep", A64PRFM_PLIL3KEEP},
+	{"plil3strm", A64PRFM_PLIL3STRM},
+	{"pstl1keep", A64PRFM_PSTL1KEEP},
+	{"pstl1strm", A64PRFM_PSTL1STRM},
+	{"pstl2keep", A64PRFM_PSTL2KEEP},
+	{"pstl2strm", A64PRFM_PSTL2STRM},
+	{"pstl3keep", A64PRFM_PSTL3KEEP},
+	{"pstl3strm", A64PRFM_PSTL3STRM}
+};
+
+A64NamedImmMapper A64PRFM_PRFMMapper = {
+	PRFMPairs,
+	ARR_SIZE(PRFMPairs),
+	32,
+};
+
+static A64NamedImmMapper_Mapping PStatePairs[] = {
+	{"spsel", A64PState_SPSel},
+	{"daifset", A64PState_DAIFSet},
+	{"daifclr", A64PState_DAIFClr}
+};
+
+A64NamedImmMapper A64PState_PStateMapper = {
+	PStatePairs,
+	ARR_SIZE(PStatePairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping MRSPairs[] = {
+	{"mdccsr_el0", A64SysReg_MDCCSR_EL0},
+	{"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
+	{"mdrar_el1", A64SysReg_MDRAR_EL1},
+	{"oslsr_el1", A64SysReg_OSLSR_EL1},
+	{"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1},
+	{"pmceid0_el0", A64SysReg_PMCEID0_EL0},
+	{"pmceid1_el0", A64SysReg_PMCEID1_EL0},
+	{"midr_el1", A64SysReg_MIDR_EL1},
+	{"ccsidr_el1", A64SysReg_CCSIDR_EL1},
+	{"clidr_el1", A64SysReg_CLIDR_EL1},
+	{"ctr_el0", A64SysReg_CTR_EL0},
+	{"mpidr_el1", A64SysReg_MPIDR_EL1},
+	{"revidr_el1", A64SysReg_REVIDR_EL1},
+	{"aidr_el1", A64SysReg_AIDR_EL1},
+	{"dczid_el0", A64SysReg_DCZID_EL0},
+	{"id_pfr0_el1", A64SysReg_ID_PFR0_EL1},
+	{"id_pfr1_el1", A64SysReg_ID_PFR1_EL1},
+	{"id_dfr0_el1", A64SysReg_ID_DFR0_EL1},
+	{"id_afr0_el1", A64SysReg_ID_AFR0_EL1},
+	{"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1},
+	{"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
+	{"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
+	{"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
+	{"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
+	{"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
+	{"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
+	{"id_isar3_el1", A64SysReg_ID_ISAR3_EL1},
+	{"id_isar4_el1", A64SysReg_ID_ISAR4_EL1},
+	{"id_isar5_el1", A64SysReg_ID_ISAR5_EL1},
+	{"id_aa64pfr0_el1", A64SysReg_ID_A64PFR0_EL1},
+	{"id_aa64pfr1_el1", A64SysReg_ID_A64PFR1_EL1},
+	{"id_aa64dfr0_el1", A64SysReg_ID_A64DFR0_EL1},
+	{"id_aa64dfr1_el1", A64SysReg_ID_A64DFR1_EL1},
+	{"id_aa64afr0_el1", A64SysReg_ID_A64AFR0_EL1},
+	{"id_aa64afr1_el1", A64SysReg_ID_A64AFR1_EL1},
+	{"id_aa64isar0_el1", A64SysReg_ID_A64ISAR0_EL1},
+	{"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1},
+	{"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1},
+	{"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1},
+	{"mvfr0_el1", A64SysReg_MVFR0_EL1},
+	{"mvfr1_el1", A64SysReg_MVFR1_EL1},
+	{"mvfr2_el1", A64SysReg_MVFR2_EL1},
+	{"rvbar_el1", A64SysReg_RVBAR_EL1},
+	{"rvbar_el2", A64SysReg_RVBAR_EL2},
+	{"rvbar_el3", A64SysReg_RVBAR_EL3},
+	{"isr_el1", A64SysReg_ISR_EL1},
+	{"cntpct_el0", A64SysReg_CNTPCT_EL0},
+	{"cntvct_el0", A64SysReg_CNTVCT_EL0},
+
+	// Trace registers
+	{"trcstatr", A64SysReg_TRCSTATR},
+	{"trcidr8", A64SysReg_TRCIDR8},
+	{"trcidr9", A64SysReg_TRCIDR9},
+	{"trcidr10", A64SysReg_TRCIDR10},
+	{"trcidr11", A64SysReg_TRCIDR11},
+	{"trcidr12", A64SysReg_TRCIDR12},
+	{"trcidr13", A64SysReg_TRCIDR13},
+	{"trcidr0", A64SysReg_TRCIDR0},
+	{"trcidr1", A64SysReg_TRCIDR1},
+	{"trcidr2", A64SysReg_TRCIDR2},
+	{"trcidr3", A64SysReg_TRCIDR3},
+	{"trcidr4", A64SysReg_TRCIDR4},
+	{"trcidr5", A64SysReg_TRCIDR5},
+	{"trcidr6", A64SysReg_TRCIDR6},
+	{"trcidr7", A64SysReg_TRCIDR7},
+	{"trcoslsr", A64SysReg_TRCOSLSR},
+	{"trcpdsr", A64SysReg_TRCPDSR},
+	{"trcdevaff0", A64SysReg_TRCDEVAFF0},
+	{"trcdevaff1", A64SysReg_TRCDEVAFF1},
+	{"trclsr", A64SysReg_TRCLSR},
+	{"trcauthstatus", A64SysReg_TRCAUTHSTATUS},
+	{"trcdevarch", A64SysReg_TRCDEVARCH},
+	{"trcdevid", A64SysReg_TRCDEVID},
+	{"trcdevtype", A64SysReg_TRCDEVTYPE},
+	{"trcpidr4", A64SysReg_TRCPIDR4},
+	{"trcpidr5", A64SysReg_TRCPIDR5},
+	{"trcpidr6", A64SysReg_TRCPIDR6},
+	{"trcpidr7", A64SysReg_TRCPIDR7},
+	{"trcpidr0", A64SysReg_TRCPIDR0},
+	{"trcpidr1", A64SysReg_TRCPIDR1},
+	{"trcpidr2", A64SysReg_TRCPIDR2},
+	{"trcpidr3", A64SysReg_TRCPIDR3},
+	{"trccidr0", A64SysReg_TRCCIDR0},
+	{"trccidr1", A64SysReg_TRCCIDR1},
+	{"trccidr2", A64SysReg_TRCCIDR2},
+	{"trccidr3", A64SysReg_TRCCIDR3},
+
+	// GICv3 registers
+	{"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1},
+	{"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1},
+	{"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1},
+	{"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1},
+	{"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
+	{"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
+	{"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
+	{"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2}
+};
+
+A64SysRegMapper AArch64_MRSMapper = {
+	NULL,
+	MRSPairs,
+	ARR_SIZE(MRSPairs),
+};
+
+static A64NamedImmMapper_Mapping MSRPairs[] = {
+	{"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
+	{"oslar_el1", A64SysReg_OSLAR_EL1},
+	{"pmswinc_el0", A64SysReg_PMSWINC_EL0},
+
+	// Trace registers
+	{"trcoslar", A64SysReg_TRCOSLAR},
+	{"trclar", A64SysReg_TRCLAR},
+
+	// GICv3 registers
+	{"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1},
+	{"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1},
+	{"icc_dir_el1", A64SysReg_ICC_DIR_EL1},
+	{"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1},
+	{"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1},
+	{"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
+};
+
+A64SysRegMapper AArch64_MSRMapper = {
+	NULL,
+	MSRPairs,
+	ARR_SIZE(MSRPairs),
+};
+
+#endif

src/3rd-party/capstone/capstone/arch/AArch64/AArch64BaseInfo.h

@@ -0,0 +1,959 @@
+//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the AArch64 target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_AARCH64_BASEINFO_H
+#define CS_LLVM_AARCH64_BASEINFO_H
+
+#include <ctype.h>
+#include <stdint.h>
+#include <string.h>
+
+#ifndef __cplusplus
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#define inline /* inline */
+#endif
+#endif
+
+inline static unsigned getWRegFromXReg(unsigned Reg)
+{
+	switch (Reg) {
+		case ARM64_REG_X0: return ARM64_REG_W0;
+		case ARM64_REG_X1: return ARM64_REG_W1;
+		case ARM64_REG_X2: return ARM64_REG_W2;
+		case ARM64_REG_X3: return ARM64_REG_W3;
+		case ARM64_REG_X4: return ARM64_REG_W4;
+		case ARM64_REG_X5: return ARM64_REG_W5;
+		case ARM64_REG_X6: return ARM64_REG_W6;
+		case ARM64_REG_X7: return ARM64_REG_W7;
+		case ARM64_REG_X8: return ARM64_REG_W8;
+		case ARM64_REG_X9: return ARM64_REG_W9;
+		case ARM64_REG_X10: return ARM64_REG_W10;
+		case ARM64_REG_X11: return ARM64_REG_W11;
+		case ARM64_REG_X12: return ARM64_REG_W12;
+		case ARM64_REG_X13: return ARM64_REG_W13;
+		case ARM64_REG_X14: return ARM64_REG_W14;
+		case ARM64_REG_X15: return ARM64_REG_W15;
+		case ARM64_REG_X16: return ARM64_REG_W16;
+		case ARM64_REG_X17: return ARM64_REG_W17;
+		case ARM64_REG_X18: return ARM64_REG_W18;
+		case ARM64_REG_X19: return ARM64_REG_W19;
+		case ARM64_REG_X20: return ARM64_REG_W20;
+		case ARM64_REG_X21: return ARM64_REG_W21;
+		case ARM64_REG_X22: return ARM64_REG_W22;
+		case ARM64_REG_X23: return ARM64_REG_W23;
+		case ARM64_REG_X24: return ARM64_REG_W24;
+		case ARM64_REG_X25: return ARM64_REG_W25;
+		case ARM64_REG_X26: return ARM64_REG_W26;
+		case ARM64_REG_X27: return ARM64_REG_W27;
+		case ARM64_REG_X28: return ARM64_REG_W28;
+		case ARM64_REG_FP: return ARM64_REG_W29;
+		case ARM64_REG_LR: return ARM64_REG_W30;
+		case ARM64_REG_SP: return ARM64_REG_WSP;
+		case ARM64_REG_XZR: return ARM64_REG_WZR;
+	}
+
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+// // Enums corresponding to AArch64 condition codes
+// The CondCodes constants map directly to the 4-bit encoding of the
+// condition field for predicated instructions.
+typedef enum A64CC_CondCode { // Meaning (integer)     Meaning (floating-point)
+	A64CC_EQ = 0,        // Equal                      Equal
+	A64CC_NE,            // Not equal                  Not equal, or unordered
+	A64CC_HS,            // Unsigned higher or same    >, ==, or unordered
+	A64CC_LO,            // Unsigned lower or same     Less than
+	A64CC_MI,            // Minus, negative            Less than
+	A64CC_PL,            // Plus, positive or zero     >, ==, or unordered
+	A64CC_VS,            // Overflow                   Unordered
+	A64CC_VC,            // No overflow                Ordered
+	A64CC_HI,            // Unsigned higher            Greater than, or unordered
+	A64CC_LS,            // Unsigned lower or same     Less than or equal
+	A64CC_GE,            // Greater than or equal      Greater than or equal
+	A64CC_LT,            // Less than                  Less than, or unordered
+	A64CC_GT,            // Signed greater than        Greater than
+	A64CC_LE,            // Signed less than or equal  <, ==, or unordered
+	A64CC_AL,            // Always (unconditional)     Always (unconditional)
+	A64CC_NV,             // Always (unconditional)     Always (unconditional)
+	// Note the NV exists purely to disassemble 0b1111. Execution is "always".
+	A64CC_Invalid
+} A64CC_CondCode;
+
+inline static char *getCondCodeName(A64CC_CondCode CC)
+{
+	switch (CC) {
+		default: return NULL;	// never reach
+		case A64CC_EQ:  return "eq";
+		case A64CC_NE:  return "ne";
+		case A64CC_HS:  return "hs";
+		case A64CC_LO:  return "lo";
+		case A64CC_MI:  return "mi";
+		case A64CC_PL:  return "pl";
+		case A64CC_VS:  return "vs";
+		case A64CC_VC:  return "vc";
+		case A64CC_HI:  return "hi";
+		case A64CC_LS:  return "ls";
+		case A64CC_GE:  return "ge";
+		case A64CC_LT:  return "lt";
+		case A64CC_GT:  return "gt";
+		case A64CC_LE:  return "le";
+		case A64CC_AL:  return "al";
+		case A64CC_NV:  return "nv";
+	}
+}
+
+inline static A64CC_CondCode getInvertedCondCode(A64CC_CondCode Code)
+{
+	// To reverse a condition it's necessary to only invert the low bit:
+	return (A64CC_CondCode)((unsigned)Code ^ 0x1);
+}
+
+/// Instances of this class can perform bidirectional mapping from random
+/// identifier strings to operand encodings. For example "MSR" takes a named
+/// system-register which must be encoded somehow and decoded for printing. This
+/// central location means that the information for those transformations is not
+/// duplicated and remains in sync.
+///
+/// FIXME: currently the algorithm is a completely unoptimised linear
+/// search. Obviously this could be improved, but we would probably want to work
+/// out just how often these instructions are emitted before working on it. It
+/// might even be optimal to just reorder the tables for the common instructions
+/// rather than changing the algorithm.
+typedef struct A64NamedImmMapper_Mapping {
+	char *Name;
+	uint32_t Value;
+} A64NamedImmMapper_Mapping;
+
+typedef struct A64NamedImmMapper {
+	A64NamedImmMapper_Mapping *Pairs;
+	size_t NumPairs;
+	uint32_t TooBigImm;
+} A64NamedImmMapper;
+
+typedef struct A64SysRegMapper {
+	A64NamedImmMapper_Mapping *SysRegPairs;
+	A64NamedImmMapper_Mapping *InstPairs;
+	size_t NumInstPairs;
+} A64SysRegMapper;
+
+extern A64SysRegMapper AArch64_MSRMapper;
+extern A64SysRegMapper AArch64_MRSMapper;
+
+extern A64NamedImmMapper A64DB_DBarrierMapper;
+extern A64NamedImmMapper A64AT_ATMapper;
+extern A64NamedImmMapper A64DC_DCMapper;
+extern A64NamedImmMapper A64IC_ICMapper;
+extern A64NamedImmMapper A64ISB_ISBMapper;
+extern A64NamedImmMapper A64PRFM_PRFMMapper;
+extern A64NamedImmMapper A64PState_PStateMapper;
+extern A64NamedImmMapper A64TLBI_TLBIMapper;
+
+enum {
+	A64AT_Invalid = -1,    // Op0 Op1  CRn   CRm   Op2
+	A64AT_S1E1R = 0x43c0,  // 01  000  0111  1000  000
+	A64AT_S1E2R = 0x63c0,  // 01  100  0111  1000  000
+	A64AT_S1E3R = 0x73c0,  // 01  110  0111  1000  000
+	A64AT_S1E1W = 0x43c1,  // 01  000  0111  1000  001
+	A64AT_S1E2W = 0x63c1,  // 01  100  0111  1000  001
+	A64AT_S1E3W = 0x73c1,  // 01  110  0111  1000  001
+	A64AT_S1E0R = 0x43c2,  // 01  000  0111  1000  010
+	A64AT_S1E0W = 0x43c3,  // 01  000  0111  1000  011
+	A64AT_S12E1R = 0x63c4, // 01  100  0111  1000  100
+	A64AT_S12E1W = 0x63c5, // 01  100  0111  1000  101
+	A64AT_S12E0R = 0x63c6, // 01  100  0111  1000  110
+	A64AT_S12E0W = 0x63c7  // 01  100  0111  1000  111
+};
+
+enum A64DBValues {
+	A64DB_Invalid = -1,
+	A64DB_OSHLD = 0x1,
+	A64DB_OSHST = 0x2,
+	A64DB_OSH =   0x3,
+	A64DB_NSHLD = 0x5,
+	A64DB_NSHST = 0x6,
+	A64DB_NSH =   0x7,
+	A64DB_ISHLD = 0x9,
+	A64DB_ISHST = 0xa,
+	A64DB_ISH =   0xb,
+	A64DB_LD =    0xd,
+	A64DB_ST =    0xe,
+	A64DB_SY =    0xf
+};
+
+enum A64DCValues {
+	A64DC_Invalid = -1,   // Op1  CRn   CRm   Op2
+	A64DC_ZVA   = 0x5ba1, // 01  011  0111  0100  001
+	A64DC_IVAC  = 0x43b1, // 01  000  0111  0110  001
+	A64DC_ISW   = 0x43b2, // 01  000  0111  0110  010
+	A64DC_CVAC  = 0x5bd1, // 01  011  0111  1010  001
+	A64DC_CSW   = 0x43d2, // 01  000  0111  1010  010
+	A64DC_CVAU  = 0x5bd9, // 01  011  0111  1011  001
+	A64DC_CIVAC = 0x5bf1, // 01  011  0111  1110  001
+	A64DC_CISW  = 0x43f2  // 01  000  0111  1110  010
+};
+
+enum A64ICValues {
+	A64IC_Invalid = -1,     // Op1  CRn   CRm   Op2
+	A64IC_IALLUIS = 0x0388, // 000  0111  0001  000
+	A64IC_IALLU = 0x03a8,   // 000  0111  0101  000
+	A64IC_IVAU = 0x1ba9     // 011  0111  0101  001
+};
+
+enum A64ISBValues {
+	A64ISB_Invalid = -1,
+	A64ISB_SY = 0xf
+};
+
+enum A64PRFMValues {
+	A64PRFM_Invalid = -1,
+	A64PRFM_PLDL1KEEP = 0x00,
+	A64PRFM_PLDL1STRM = 0x01,
+	A64PRFM_PLDL2KEEP = 0x02,
+	A64PRFM_PLDL2STRM = 0x03,
+	A64PRFM_PLDL3KEEP = 0x04,
+	A64PRFM_PLDL3STRM = 0x05,
+	A64PRFM_PLIL1KEEP = 0x08,
+	A64PRFM_PLIL1STRM = 0x09,
+	A64PRFM_PLIL2KEEP = 0x0a,
+	A64PRFM_PLIL2STRM = 0x0b,
+	A64PRFM_PLIL3KEEP = 0x0c,
+	A64PRFM_PLIL3STRM = 0x0d,
+	A64PRFM_PSTL1KEEP = 0x10,
+	A64PRFM_PSTL1STRM = 0x11,
+	A64PRFM_PSTL2KEEP = 0x12,
+	A64PRFM_PSTL2STRM = 0x13,
+	A64PRFM_PSTL3KEEP = 0x14,
+	A64PRFM_PSTL3STRM = 0x15
+};
+
+enum A64PStateValues {
+	A64PState_Invalid = -1,
+	A64PState_SPSel = 0x05,
+	A64PState_DAIFSet = 0x1e,
+	A64PState_DAIFClr = 0x1f
+};
+
+typedef enum A64SE_ShiftExtSpecifiers {
+	A64SE_Invalid = -1,
+	A64SE_LSL,
+	A64SE_MSL,
+	A64SE_LSR,
+	A64SE_ASR,
+	A64SE_ROR,
+
+	A64SE_UXTB,
+	A64SE_UXTH,
+	A64SE_UXTW,
+	A64SE_UXTX,
+
+	A64SE_SXTB,
+	A64SE_SXTH,
+	A64SE_SXTW,
+	A64SE_SXTX
+} A64SE_ShiftExtSpecifiers;
+
+typedef enum A64Layout_VectorLayout {
+	A64Layout_Invalid = -1,
+	A64Layout_VL_8B,
+	A64Layout_VL_4H,
+	A64Layout_VL_2S,
+	A64Layout_VL_1D,
+
+	A64Layout_VL_16B,
+	A64Layout_VL_8H,
+	A64Layout_VL_4S,
+	A64Layout_VL_2D,
+
+	// Bare layout for the 128-bit vector
+	// (only show ".b", ".h", ".s", ".d" without vector number)
+	A64Layout_VL_B,
+	A64Layout_VL_H,
+	A64Layout_VL_S,
+	A64Layout_VL_D
+} A64Layout_VectorLayout;
+
+inline static char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
+{
+	switch (Layout) {
+		case A64Layout_VL_8B:  return ".8b";
+		case A64Layout_VL_4H:  return ".4h";
+		case A64Layout_VL_2S:  return ".2s";
+		case A64Layout_VL_1D:  return ".1d";
+		case A64Layout_VL_16B:  return ".16b";
+		case A64Layout_VL_8H:  return ".8h";
+		case A64Layout_VL_4S:  return ".4s";
+		case A64Layout_VL_2D:  return ".2d";
+		case A64Layout_VL_B:  return ".b";
+		case A64Layout_VL_H:  return ".h";
+		case A64Layout_VL_S:  return ".s";
+		case A64Layout_VL_D:  return ".d";
+		default: return NULL;	// never reach
+	}
+}
+
+enum A64SysRegROValues {
+	A64SysReg_MDCCSR_EL0        = 0x9808, // 10  011  0000  0001  000
+	A64SysReg_DBGDTRRX_EL0      = 0x9828, // 10  011  0000  0101  000
+	A64SysReg_MDRAR_EL1         = 0x8080, // 10  000  0001  0000  000
+	A64SysReg_OSLSR_EL1         = 0x808c, // 10  000  0001  0001  100
+	A64SysReg_DBGAUTHSTATUS_EL1 = 0x83f6, // 10  000  0111  1110  110
+	A64SysReg_PMCEID0_EL0       = 0xdce6, // 11  011  1001  1100  110
+	A64SysReg_PMCEID1_EL0       = 0xdce7, // 11  011  1001  1100  111
+	A64SysReg_MIDR_EL1          = 0xc000, // 11  000  0000  0000  000
+	A64SysReg_CCSIDR_EL1        = 0xc800, // 11  001  0000  0000  000
+	A64SysReg_CLIDR_EL1         = 0xc801, // 11  001  0000  0000  001
+	A64SysReg_CTR_EL0           = 0xd801, // 11  011  0000  0000  001
+	A64SysReg_MPIDR_EL1         = 0xc005, // 11  000  0000  0000  101
+	A64SysReg_REVIDR_EL1        = 0xc006, // 11  000  0000  0000  110
+	A64SysReg_AIDR_EL1          = 0xc807, // 11  001  0000  0000  111
+	A64SysReg_DCZID_EL0         = 0xd807, // 11  011  0000  0000  111
+	A64SysReg_ID_PFR0_EL1       = 0xc008, // 11  000  0000  0001  000
+	A64SysReg_ID_PFR1_EL1       = 0xc009, // 11  000  0000  0001  001
+	A64SysReg_ID_DFR0_EL1       = 0xc00a, // 11  000  0000  0001  010
+	A64SysReg_ID_AFR0_EL1       = 0xc00b, // 11  000  0000  0001  011
+	A64SysReg_ID_MMFR0_EL1      = 0xc00c, // 11  000  0000  0001  100
+	A64SysReg_ID_MMFR1_EL1      = 0xc00d, // 11  000  0000  0001  101
+	A64SysReg_ID_MMFR2_EL1      = 0xc00e, // 11  000  0000  0001  110
+	A64SysReg_ID_MMFR3_EL1      = 0xc00f, // 11  000  0000  0001  111
+	A64SysReg_ID_ISAR0_EL1      = 0xc010, // 11  000  0000  0010  000
+	A64SysReg_ID_ISAR1_EL1      = 0xc011, // 11  000  0000  0010  001
+	A64SysReg_ID_ISAR2_EL1      = 0xc012, // 11  000  0000  0010  010
+	A64SysReg_ID_ISAR3_EL1      = 0xc013, // 11  000  0000  0010  011
+	A64SysReg_ID_ISAR4_EL1      = 0xc014, // 11  000  0000  0010  100
+	A64SysReg_ID_ISAR5_EL1      = 0xc015, // 11  000  0000  0010  101
+	A64SysReg_ID_A64PFR0_EL1   = 0xc020, // 11  000  0000  0100  000
+	A64SysReg_ID_A64PFR1_EL1   = 0xc021, // 11  000  0000  0100  001
+	A64SysReg_ID_A64DFR0_EL1   = 0xc028, // 11  000  0000  0101  000
+	A64SysReg_ID_A64DFR1_EL1   = 0xc029, // 11  000  0000  0101  001
+	A64SysReg_ID_A64AFR0_EL1   = 0xc02c, // 11  000  0000  0101  100
+	A64SysReg_ID_A64AFR1_EL1   = 0xc02d, // 11  000  0000  0101  101
+	A64SysReg_ID_A64ISAR0_EL1  = 0xc030, // 11  000  0000  0110  000
+	A64SysReg_ID_A64ISAR1_EL1  = 0xc031, // 11  000  0000  0110  001
+	A64SysReg_ID_A64MMFR0_EL1  = 0xc038, // 11  000  0000  0111  000
+	A64SysReg_ID_A64MMFR1_EL1  = 0xc039, // 11  000  0000  0111  001
+	A64SysReg_MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
+	A64SysReg_MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
+	A64SysReg_MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
+	A64SysReg_RVBAR_EL1         = 0xc601, // 11  000  1100  0000  001
+	A64SysReg_RVBAR_EL2         = 0xe601, // 11  100  1100  0000  001
+	A64SysReg_RVBAR_EL3         = 0xf601, // 11  110  1100  0000  001
+	A64SysReg_ISR_EL1           = 0xc608, // 11  000  1100  0001  000
+	A64SysReg_CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
+	A64SysReg_CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010
+
+	// Trace registers
+	A64SysReg_TRCSTATR          = 0x8818, // 10  001  0000  0011  000
+	A64SysReg_TRCIDR8           = 0x8806, // 10  001  0000  0000  110
+	A64SysReg_TRCIDR9           = 0x880e, // 10  001  0000  0001  110
+	A64SysReg_TRCIDR10          = 0x8816, // 10  001  0000  0010  110
+	A64SysReg_TRCIDR11          = 0x881e, // 10  001  0000  0011  110
+	A64SysReg_TRCIDR12          = 0x8826, // 10  001  0000  0100  110
+	A64SysReg_TRCIDR13          = 0x882e, // 10  001  0000  0101  110
+	A64SysReg_TRCIDR0           = 0x8847, // 10  001  0000  1000  111
+	A64SysReg_TRCIDR1           = 0x884f, // 10  001  0000  1001  111
+	A64SysReg_TRCIDR2           = 0x8857, // 10  001  0000  1010  111
+	A64SysReg_TRCIDR3           = 0x885f, // 10  001  0000  1011  111
+	A64SysReg_TRCIDR4           = 0x8867, // 10  001  0000  1100  111
+	A64SysReg_TRCIDR5           = 0x886f, // 10  001  0000  1101  111
+	A64SysReg_TRCIDR6           = 0x8877, // 10  001  0000  1110  111
+	A64SysReg_TRCIDR7           = 0x887f, // 10  001  0000  1111  111
+	A64SysReg_TRCOSLSR          = 0x888c, // 10  001  0001  0001  100
+	A64SysReg_TRCPDSR           = 0x88ac, // 10  001  0001  0101  100
+	A64SysReg_TRCDEVAFF0        = 0x8bd6, // 10  001  0111  1010  110
+	A64SysReg_TRCDEVAFF1        = 0x8bde, // 10  001  0111  1011  110
+	A64SysReg_TRCLSR            = 0x8bee, // 10  001  0111  1101  110
+	A64SysReg_TRCAUTHSTATUS     = 0x8bf6, // 10  001  0111  1110  110
+	A64SysReg_TRCDEVARCH        = 0x8bfe, // 10  001  0111  1111  110
+	A64SysReg_TRCDEVID          = 0x8b97, // 10  001  0111  0010  111
+	A64SysReg_TRCDEVTYPE        = 0x8b9f, // 10  001  0111  0011  111
+	A64SysReg_TRCPIDR4          = 0x8ba7, // 10  001  0111  0100  111
+	A64SysReg_TRCPIDR5          = 0x8baf, // 10  001  0111  0101  111
+	A64SysReg_TRCPIDR6          = 0x8bb7, // 10  001  0111  0110  111
+	A64SysReg_TRCPIDR7          = 0x8bbf, // 10  001  0111  0111  111
+	A64SysReg_TRCPIDR0          = 0x8bc7, // 10  001  0111  1000  111
+	A64SysReg_TRCPIDR1          = 0x8bcf, // 10  001  0111  1001  111
+	A64SysReg_TRCPIDR2          = 0x8bd7, // 10  001  0111  1010  111
+	A64SysReg_TRCPIDR3          = 0x8bdf, // 10  001  0111  1011  111
+	A64SysReg_TRCCIDR0          = 0x8be7, // 10  001  0111  1100  111
+	A64SysReg_TRCCIDR1          = 0x8bef, // 10  001  0111  1101  111
+	A64SysReg_TRCCIDR2          = 0x8bf7, // 10  001  0111  1110  111
+	A64SysReg_TRCCIDR3          = 0x8bff, // 10  001  0111  1111  111
+
+	// GICv3 registers
+	A64SysReg_ICC_IAR1_EL1      = 0xc660, // 11  000  1100  1100  000
+	A64SysReg_ICC_IAR0_EL1      = 0xc640, // 11  000  1100  1000  000
+	A64SysReg_ICC_HPPIR1_EL1    = 0xc662, // 11  000  1100  1100  010
+	A64SysReg_ICC_HPPIR0_EL1    = 0xc642, // 11  000  1100  1000  010
+	A64SysReg_ICC_RPR_EL1       = 0xc65b, // 11  000  1100  1011  011
+	A64SysReg_ICH_VTR_EL2       = 0xe659, // 11  100  1100  1011  001
+	A64SysReg_ICH_EISR_EL2      = 0xe65b, // 11  100  1100  1011  011
+	A64SysReg_ICH_ELSR_EL2      = 0xe65d  // 11  100  1100  1011  101
+};
+
+enum A64SysRegWOValues {
+	A64SysReg_DBGDTRTX_EL0      = 0x9828, // 10  011  0000  0101  000
+	A64SysReg_OSLAR_EL1         = 0x8084, // 10  000  0001  0000  100
+	A64SysReg_PMSWINC_EL0       = 0xdce4,  // 11  011  1001  1100  100
+
+	// Trace Registers
+	A64SysReg_TRCOSLAR          = 0x8884, // 10  001  0001  0000  100
+	A64SysReg_TRCLAR            = 0x8be6, // 10  001  0111  1100  110
+
+	// GICv3 registers
+	A64SysReg_ICC_EOIR1_EL1     = 0xc661, // 11  000  1100  1100  001
+	A64SysReg_ICC_EOIR0_EL1     = 0xc641, // 11  000  1100  1000  001
+	A64SysReg_ICC_DIR_EL1       = 0xc659, // 11  000  1100  1011  001
+	A64SysReg_ICC_SGI1R_EL1     = 0xc65d, // 11  000  1100  1011  101
+	A64SysReg_ICC_ASGI1R_EL1    = 0xc65e, // 11  000  1100  1011  110
+	A64SysReg_ICC_SGI0R_EL1     = 0xc65f  // 11  000  1100  1011  111
+};
+
+enum A64SysRegValues {
+	A64SysReg_Invalid = -1,               // Op0 Op1  CRn   CRm   Op2
+	A64SysReg_OSDTRRX_EL1       = 0x8002, // 10  000  0000  0000  010
+	A64SysReg_OSDTRTX_EL1       = 0x801a, // 10  000  0000  0011  010
+	A64SysReg_TEECR32_EL1       = 0x9000, // 10  010  0000  0000  000
+	A64SysReg_MDCCINT_EL1       = 0x8010, // 10  000  0000  0010  000
+	A64SysReg_MDSCR_EL1         = 0x8012, // 10  000  0000  0010  010
+	A64SysReg_DBGDTR_EL0        = 0x9820, // 10  011  0000  0100  000
+	A64SysReg_OSECCR_EL1        = 0x8032, // 10  000  0000  0110  010
+	A64SysReg_DBGVCR32_EL2      = 0xa038, // 10  100  0000  0111  000
+	A64SysReg_DBGBVR0_EL1       = 0x8004, // 10  000  0000  0000  100
+	A64SysReg_DBGBVR1_EL1       = 0x800c, // 10  000  0000  0001  100
+	A64SysReg_DBGBVR2_EL1       = 0x8014, // 10  000  0000  0010  100
+	A64SysReg_DBGBVR3_EL1       = 0x801c, // 10  000  0000  0011  100
+	A64SysReg_DBGBVR4_EL1       = 0x8024, // 10  000  0000  0100  100
+	A64SysReg_DBGBVR5_EL1       = 0x802c, // 10  000  0000  0101  100
+	A64SysReg_DBGBVR6_EL1       = 0x8034, // 10  000  0000  0110  100
+	A64SysReg_DBGBVR7_EL1       = 0x803c, // 10  000  0000  0111  100
+	A64SysReg_DBGBVR8_EL1       = 0x8044, // 10  000  0000  1000  100
+	A64SysReg_DBGBVR9_EL1       = 0x804c, // 10  000  0000  1001  100
+	A64SysReg_DBGBVR10_EL1      = 0x8054, // 10  000  0000  1010  100
+	A64SysReg_DBGBVR11_EL1      = 0x805c, // 10  000  0000  1011  100
+	A64SysReg_DBGBVR12_EL1      = 0x8064, // 10  000  0000  1100  100
+	A64SysReg_DBGBVR13_EL1      = 0x806c, // 10  000  0000  1101  100
+	A64SysReg_DBGBVR14_EL1      = 0x8074, // 10  000  0000  1110  100
+	A64SysReg_DBGBVR15_EL1      = 0x807c, // 10  000  0000  1111  100
+	A64SysReg_DBGBCR0_EL1       = 0x8005, // 10  000  0000  0000  101
+	A64SysReg_DBGBCR1_EL1       = 0x800d, // 10  000  0000  0001  101
+	A64SysReg_DBGBCR2_EL1       = 0x8015, // 10  000  0000  0010  101
+	A64SysReg_DBGBCR3_EL1       = 0x801d, // 10  000  0000  0011  101
+	A64SysReg_DBGBCR4_EL1       = 0x8025, // 10  000  0000  0100  101
+	A64SysReg_DBGBCR5_EL1       = 0x802d, // 10  000  0000  0101  101
+	A64SysReg_DBGBCR6_EL1       = 0x8035, // 10  000  0000  0110  101
+	A64SysReg_DBGBCR7_EL1       = 0x803d, // 10  000  0000  0111  101
+	A64SysReg_DBGBCR8_EL1       = 0x8045, // 10  000  0000  1000  101
+	A64SysReg_DBGBCR9_EL1       = 0x804d, // 10  000  0000  1001  101
+	A64SysReg_DBGBCR10_EL1      = 0x8055, // 10  000  0000  1010  101
+	A64SysReg_DBGBCR11_EL1      = 0x805d, // 10  000  0000  1011  101
+	A64SysReg_DBGBCR12_EL1      = 0x8065, // 10  000  0000  1100  101
+	A64SysReg_DBGBCR13_EL1      = 0x806d, // 10  000  0000  1101  101
+	A64SysReg_DBGBCR14_EL1      = 0x8075, // 10  000  0000  1110  101
+	A64SysReg_DBGBCR15_EL1      = 0x807d, // 10  000  0000  1111  101
+	A64SysReg_DBGWVR0_EL1       = 0x8006, // 10  000  0000  0000  110
+	A64SysReg_DBGWVR1_EL1       = 0x800e, // 10  000  0000  0001  110
+	A64SysReg_DBGWVR2_EL1       = 0x8016, // 10  000  0000  0010  110
+	A64SysReg_DBGWVR3_EL1       = 0x801e, // 10  000  0000  0011  110
+	A64SysReg_DBGWVR4_EL1       = 0x8026, // 10  000  0000  0100  110
+	A64SysReg_DBGWVR5_EL1       = 0x802e, // 10  000  0000  0101  110
+	A64SysReg_DBGWVR6_EL1       = 0x8036, // 10  000  0000  0110  110
+	A64SysReg_DBGWVR7_EL1       = 0x803e, // 10  000  0000  0111  110
+	A64SysReg_DBGWVR8_EL1       = 0x8046, // 10  000  0000  1000  110
+	A64SysReg_DBGWVR9_EL1       = 0x804e, // 10  000  0000  1001  110
+	A64SysReg_DBGWVR10_EL1      = 0x8056, // 10  000  0000  1010  110
+	A64SysReg_DBGWVR11_EL1      = 0x805e, // 10  000  0000  1011  110
+	A64SysReg_DBGWVR12_EL1      = 0x8066, // 10  000  0000  1100  110
+	A64SysReg_DBGWVR13_EL1      = 0x806e, // 10  000  0000  1101  110
+	A64SysReg_DBGWVR14_EL1      = 0x8076, // 10  000  0000  1110  110
+	A64SysReg_DBGWVR15_EL1      = 0x807e, // 10  000  0000  1111  110
+	A64SysReg_DBGWCR0_EL1       = 0x8007, // 10  000  0000  0000  111
+	A64SysReg_DBGWCR1_EL1       = 0x800f, // 10  000  0000  0001  111
+	A64SysReg_DBGWCR2_EL1       = 0x8017, // 10  000  0000  0010  111
+	A64SysReg_DBGWCR3_EL1       = 0x801f, // 10  000  0000  0011  111
+	A64SysReg_DBGWCR4_EL1       = 0x8027, // 10  000  0000  0100  111
+	A64SysReg_DBGWCR5_EL1       = 0x802f, // 10  000  0000  0101  111
+	A64SysReg_DBGWCR6_EL1       = 0x8037, // 10  000  0000  0110  111
+	A64SysReg_DBGWCR7_EL1       = 0x803f, // 10  000  0000  0111  111
+	A64SysReg_DBGWCR8_EL1       = 0x8047, // 10  000  0000  1000  111
+	A64SysReg_DBGWCR9_EL1       = 0x804f, // 10  000  0000  1001  111
+	A64SysReg_DBGWCR10_EL1      = 0x8057, // 10  000  0000  1010  111
+	A64SysReg_DBGWCR11_EL1      = 0x805f, // 10  000  0000  1011  111
+	A64SysReg_DBGWCR12_EL1      = 0x8067, // 10  000  0000  1100  111
+	A64SysReg_DBGWCR13_EL1      = 0x806f, // 10  000  0000  1101  111
+	A64SysReg_DBGWCR14_EL1      = 0x8077, // 10  000  0000  1110  111
+	A64SysReg_DBGWCR15_EL1      = 0x807f, // 10  000  0000  1111  111
+	A64SysReg_TEEHBR32_EL1      = 0x9080, // 10  010  0001  0000  000
+	A64SysReg_OSDLR_EL1         = 0x809c, // 10  000  0001  0011  100
+	A64SysReg_DBGPRCR_EL1       = 0x80a4, // 10  000  0001  0100  100
+	A64SysReg_DBGCLAIMSET_EL1   = 0x83c6, // 10  000  0111  1000  110
+	A64SysReg_DBGCLAIMCLR_EL1   = 0x83ce, // 10  000  0111  1001  110
+	A64SysReg_CSSELR_EL1        = 0xd000, // 11  010  0000  0000  000
+	A64SysReg_VPIDR_EL2         = 0xe000, // 11  100  0000  0000  000
+	A64SysReg_VMPIDR_EL2        = 0xe005, // 11  100  0000  0000  101
+	A64SysReg_CPACR_EL1         = 0xc082, // 11  000  0001  0000  010
+	A64SysReg_SCTLR_EL1         = 0xc080, // 11  000  0001  0000  000
+	A64SysReg_SCTLR_EL2         = 0xe080, // 11  100  0001  0000  000
+	A64SysReg_SCTLR_EL3         = 0xf080, // 11  110  0001  0000  000
+	A64SysReg_ACTLR_EL1         = 0xc081, // 11  000  0001  0000  001
+	A64SysReg_ACTLR_EL2         = 0xe081, // 11  100  0001  0000  001
+	A64SysReg_ACTLR_EL3         = 0xf081, // 11  110  0001  0000  001
+	A64SysReg_HCR_EL2           = 0xe088, // 11  100  0001  0001  000
+	A64SysReg_SCR_EL3           = 0xf088, // 11  110  0001  0001  000
+	A64SysReg_MDCR_EL2          = 0xe089, // 11  100  0001  0001  001
+	A64SysReg_SDER32_EL3        = 0xf089, // 11  110  0001  0001  001
+	A64SysReg_CPTR_EL2          = 0xe08a, // 11  100  0001  0001  010
+	A64SysReg_CPTR_EL3          = 0xf08a, // 11  110  0001  0001  010
+	A64SysReg_HSTR_EL2          = 0xe08b, // 11  100  0001  0001  011
+	A64SysReg_HACR_EL2          = 0xe08f, // 11  100  0001  0001  111
+	A64SysReg_MDCR_EL3          = 0xf099, // 11  110  0001  0011  001
+	A64SysReg_TTBR0_EL1         = 0xc100, // 11  000  0010  0000  000
+	A64SysReg_TTBR0_EL2         = 0xe100, // 11  100  0010  0000  000
+	A64SysReg_TTBR0_EL3         = 0xf100, // 11  110  0010  0000  000
+	A64SysReg_TTBR1_EL1         = 0xc101, // 11  000  0010  0000  001
+	A64SysReg_TCR_EL1           = 0xc102, // 11  000  0010  0000  010
+	A64SysReg_TCR_EL2           = 0xe102, // 11  100  0010  0000  010
+	A64SysReg_TCR_EL3           = 0xf102, // 11  110  0010  0000  010
+	A64SysReg_VTTBR_EL2         = 0xe108, // 11  100  0010  0001  000
+	A64SysReg_VTCR_EL2          = 0xe10a, // 11  100  0010  0001  010
+	A64SysReg_DACR32_EL2        = 0xe180, // 11  100  0011  0000  000
+	A64SysReg_SPSR_EL1          = 0xc200, // 11  000  0100  0000  000
+	A64SysReg_SPSR_EL2          = 0xe200, // 11  100  0100  0000  000
+	A64SysReg_SPSR_EL3          = 0xf200, // 11  110  0100  0000  000
+	A64SysReg_ELR_EL1           = 0xc201, // 11  000  0100  0000  001
+	A64SysReg_ELR_EL2           = 0xe201, // 11  100  0100  0000  001
+	A64SysReg_ELR_EL3           = 0xf201, // 11  110  0100  0000  001
+	A64SysReg_SP_EL0            = 0xc208, // 11  000  0100  0001  000
+	A64SysReg_SP_EL1            = 0xe208, // 11  100  0100  0001  000
+	A64SysReg_SP_EL2            = 0xf208, // 11  110  0100  0001  000
+	A64SysReg_SPSel             = 0xc210, // 11  000  0100  0010  000
+	A64SysReg_NZCV              = 0xda10, // 11  011  0100  0010  000
+	A64SysReg_DAIF              = 0xda11, // 11  011  0100  0010  001
+	A64SysReg_CurrentEL         = 0xc212, // 11  000  0100  0010  010
+	A64SysReg_SPSR_irq          = 0xe218, // 11  100  0100  0011  000
+	A64SysReg_SPSR_abt          = 0xe219, // 11  100  0100  0011  001
+	A64SysReg_SPSR_und          = 0xe21a, // 11  100  0100  0011  010
+	A64SysReg_SPSR_fiq          = 0xe21b, // 11  100  0100  0011  011
+	A64SysReg_FPCR              = 0xda20, // 11  011  0100  0100  000
+	A64SysReg_FPSR              = 0xda21, // 11  011  0100  0100  001
+	A64SysReg_DSPSR_EL0         = 0xda28, // 11  011  0100  0101  000
+	A64SysReg_DLR_EL0           = 0xda29, // 11  011  0100  0101  001
+	A64SysReg_IFSR32_EL2        = 0xe281, // 11  100  0101  0000  001
+	A64SysReg_AFSR0_EL1         = 0xc288, // 11  000  0101  0001  000
+	A64SysReg_AFSR0_EL2         = 0xe288, // 11  100  0101  0001  000
+	A64SysReg_AFSR0_EL3         = 0xf288, // 11  110  0101  0001  000
+	A64SysReg_AFSR1_EL1         = 0xc289, // 11  000  0101  0001  001
+	A64SysReg_AFSR1_EL2         = 0xe289, // 11  100  0101  0001  001
+	A64SysReg_AFSR1_EL3         = 0xf289, // 11  110  0101  0001  001
+	A64SysReg_ESR_EL1           = 0xc290, // 11  000  0101  0010  000
+	A64SysReg_ESR_EL2           = 0xe290, // 11  100  0101  0010  000
+	A64SysReg_ESR_EL3           = 0xf290, // 11  110  0101  0010  000
+	A64SysReg_FPEXC32_EL2       = 0xe298, // 11  100  0101  0011  000
+	A64SysReg_FAR_EL1           = 0xc300, // 11  000  0110  0000  000
+	A64SysReg_FAR_EL2           = 0xe300, // 11  100  0110  0000  000
+	A64SysReg_FAR_EL3           = 0xf300, // 11  110  0110  0000  000
+	A64SysReg_HPFAR_EL2         = 0xe304, // 11  100  0110  0000  100
+	A64SysReg_PAR_EL1           = 0xc3a0, // 11  000  0111  0100  000
+	A64SysReg_PMCR_EL0          = 0xdce0, // 11  011  1001  1100  000
+	A64SysReg_PMCNTENSET_EL0    = 0xdce1, // 11  011  1001  1100  001
+	A64SysReg_PMCNTENCLR_EL0    = 0xdce2, // 11  011  1001  1100  010
+	A64SysReg_PMOVSCLR_EL0      = 0xdce3, // 11  011  1001  1100  011
+	A64SysReg_PMSELR_EL0        = 0xdce5, // 11  011  1001  1100  101
+	A64SysReg_PMCCNTR_EL0       = 0xdce8, // 11  011  1001  1101  000
+	A64SysReg_PMXEVTYPER_EL0    = 0xdce9, // 11  011  1001  1101  001
+	A64SysReg_PMXEVCNTR_EL0     = 0xdcea, // 11  011  1001  1101  010
+	A64SysReg_PMUSERENR_EL0     = 0xdcf0, // 11  011  1001  1110  000
+	A64SysReg_PMINTENSET_EL1    = 0xc4f1, // 11  000  1001  1110  001
+	A64SysReg_PMINTENCLR_EL1    = 0xc4f2, // 11  000  1001  1110  010
+	A64SysReg_PMOVSSET_EL0      = 0xdcf3, // 11  011  1001  1110  011
+	A64SysReg_MAIR_EL1          = 0xc510, // 11  000  1010  0010  000
+	A64SysReg_MAIR_EL2          = 0xe510, // 11  100  1010  0010  000
+	A64SysReg_MAIR_EL3          = 0xf510, // 11  110  1010  0010  000
+	A64SysReg_AMAIR_EL1         = 0xc518, // 11  000  1010  0011  000
+	A64SysReg_AMAIR_EL2         = 0xe518, // 11  100  1010  0011  000
+	A64SysReg_AMAIR_EL3         = 0xf518, // 11  110  1010  0011  000
+	A64SysReg_VBAR_EL1          = 0xc600, // 11  000  1100  0000  000
+	A64SysReg_VBAR_EL2          = 0xe600, // 11  100  1100  0000  000
+	A64SysReg_VBAR_EL3          = 0xf600, // 11  110  1100  0000  000
+	A64SysReg_RMR_EL1           = 0xc602, // 11  000  1100  0000  010
+	A64SysReg_RMR_EL2           = 0xe602, // 11  100  1100  0000  010
+	A64SysReg_RMR_EL3           = 0xf602, // 11  110  1100  0000  010
+	A64SysReg_CONTEXTIDR_EL1    = 0xc681, // 11  000  1101  0000  001
+	A64SysReg_TPIDR_EL0         = 0xde82, // 11  011  1101  0000  010
+	A64SysReg_TPIDR_EL2         = 0xe682, // 11  100  1101  0000  010
+	A64SysReg_TPIDR_EL3         = 0xf682, // 11  110  1101  0000  010
+	A64SysReg_TPIDRRO_EL0       = 0xde83, // 11  011  1101  0000  011
+	A64SysReg_TPIDR_EL1         = 0xc684, // 11  000  1101  0000  100
+	A64SysReg_CNTFRQ_EL0        = 0xdf00, // 11  011  1110  0000  000
+	A64SysReg_CNTVOFF_EL2       = 0xe703, // 11  100  1110  0000  011
+	A64SysReg_CNTKCTL_EL1       = 0xc708, // 11  000  1110  0001  000
+	A64SysReg_CNTHCTL_EL2       = 0xe708, // 11  100  1110  0001  000
+	A64SysReg_CNTP_TVAL_EL0     = 0xdf10, // 11  011  1110  0010  000
+	A64SysReg_CNTHP_TVAL_EL2    = 0xe710, // 11  100  1110  0010  000
+	A64SysReg_CNTPS_TVAL_EL1    = 0xff10, // 11  111  1110  0010  000
+	A64SysReg_CNTP_CTL_EL0      = 0xdf11, // 11  011  1110  0010  001
+	A64SysReg_CNTHP_CTL_EL2     = 0xe711, // 11  100  1110  0010  001
+	A64SysReg_CNTPS_CTL_EL1     = 0xff11, // 11  111  1110  0010  001
+	A64SysReg_CNTP_CVAL_EL0     = 0xdf12, // 11  011  1110  0010  010
+	A64SysReg_CNTHP_CVAL_EL2    = 0xe712, // 11  100  1110  0010  010
+	A64SysReg_CNTPS_CVAL_EL1    = 0xff12, // 11  111  1110  0010  010
+	A64SysReg_CNTV_TVAL_EL0     = 0xdf18, // 11  011  1110  0011  000
+	A64SysReg_CNTV_CTL_EL0      = 0xdf19, // 11  011  1110  0011  001
+	A64SysReg_CNTV_CVAL_EL0     = 0xdf1a, // 11  011  1110  0011  010
+	A64SysReg_PMEVCNTR0_EL0     = 0xdf40, // 11  011  1110  1000  000
+	A64SysReg_PMEVCNTR1_EL0     = 0xdf41, // 11  011  1110  1000  001
+	A64SysReg_PMEVCNTR2_EL0     = 0xdf42, // 11  011  1110  1000  010
+	A64SysReg_PMEVCNTR3_EL0     = 0xdf43, // 11  011  1110  1000  011
+	A64SysReg_PMEVCNTR4_EL0     = 0xdf44, // 11  011  1110  1000  100
+	A64SysReg_PMEVCNTR5_EL0     = 0xdf45, // 11  011  1110  1000  101
+	A64SysReg_PMEVCNTR6_EL0     = 0xdf46, // 11  011  1110  1000  110
+	A64SysReg_PMEVCNTR7_EL0     = 0xdf47, // 11  011  1110  1000  111
+	A64SysReg_PMEVCNTR8_EL0     = 0xdf48, // 11  011  1110  1001  000
+	A64SysReg_PMEVCNTR9_EL0     = 0xdf49, // 11  011  1110  1001  001
+	A64SysReg_PMEVCNTR10_EL0    = 0xdf4a, // 11  011  1110  1001  010
+	A64SysReg_PMEVCNTR11_EL0    = 0xdf4b, // 11  011  1110  1001  011
+	A64SysReg_PMEVCNTR12_EL0    = 0xdf4c, // 11  011  1110  1001  100
+	A64SysReg_PMEVCNTR13_EL0    = 0xdf4d, // 11  011  1110  1001  101
+	A64SysReg_PMEVCNTR14_EL0    = 0xdf4e, // 11  011  1110  1001  110
+	A64SysReg_PMEVCNTR15_EL0    = 0xdf4f, // 11  011  1110  1001  111
+	A64SysReg_PMEVCNTR16_EL0    = 0xdf50, // 11  011  1110  1010  000
+	A64SysReg_PMEVCNTR17_EL0    = 0xdf51, // 11  011  1110  1010  001
+	A64SysReg_PMEVCNTR18_EL0    = 0xdf52, // 11  011  1110  1010  010
+	A64SysReg_PMEVCNTR19_EL0    = 0xdf53, // 11  011  1110  1010  011
+	A64SysReg_PMEVCNTR20_EL0    = 0xdf54, // 11  011  1110  1010  100
+	A64SysReg_PMEVCNTR21_EL0    = 0xdf55, // 11  011  1110  1010  101
+	A64SysReg_PMEVCNTR22_EL0    = 0xdf56, // 11  011  1110  1010  110
+	A64SysReg_PMEVCNTR23_EL0    = 0xdf57, // 11  011  1110  1010  111
+	A64SysReg_PMEVCNTR24_EL0    = 0xdf58, // 11  011  1110  1011  000
+	A64SysReg_PMEVCNTR25_EL0    = 0xdf59, // 11  011  1110  1011  001
+	A64SysReg_PMEVCNTR26_EL0    = 0xdf5a, // 11  011  1110  1011  010
+	A64SysReg_PMEVCNTR27_EL0    = 0xdf5b, // 11  011  1110  1011  011
+	A64SysReg_PMEVCNTR28_EL0    = 0xdf5c, // 11  011  1110  1011  100
+	A64SysReg_PMEVCNTR29_EL0    = 0xdf5d, // 11  011  1110  1011  101
+	A64SysReg_PMEVCNTR30_EL0    = 0xdf5e, // 11  011  1110  1011  110
+	A64SysReg_PMCCFILTR_EL0     = 0xdf7f, // 11  011  1110  1111  111
+	A64SysReg_PMEVTYPER0_EL0    = 0xdf60, // 11  011  1110  1100  000
+	A64SysReg_PMEVTYPER1_EL0    = 0xdf61, // 11  011  1110  1100  001
+	A64SysReg_PMEVTYPER2_EL0    = 0xdf62, // 11  011  1110  1100  010
+	A64SysReg_PMEVTYPER3_EL0    = 0xdf63, // 11  011  1110  1100  011
+	A64SysReg_PMEVTYPER4_EL0    = 0xdf64, // 11  011  1110  1100  100
+	A64SysReg_PMEVTYPER5_EL0    = 0xdf65, // 11  011  1110  1100  101
+	A64SysReg_PMEVTYPER6_EL0    = 0xdf66, // 11  011  1110  1100  110
+	A64SysReg_PMEVTYPER7_EL0    = 0xdf67, // 11  011  1110  1100  111
+	A64SysReg_PMEVTYPER8_EL0    = 0xdf68, // 11  011  1110  1101  000
+	A64SysReg_PMEVTYPER9_EL0    = 0xdf69, // 11  011  1110  1101  001
+	A64SysReg_PMEVTYPER10_EL0   = 0xdf6a, // 11  011  1110  1101  010
+	A64SysReg_PMEVTYPER11_EL0   = 0xdf6b, // 11  011  1110  1101  011
+	A64SysReg_PMEVTYPER12_EL0   = 0xdf6c, // 11  011  1110  1101  100
+	A64SysReg_PMEVTYPER13_EL0   = 0xdf6d, // 11  011  1110  1101  101
+	A64SysReg_PMEVTYPER14_EL0   = 0xdf6e, // 11  011  1110  1101  110
+	A64SysReg_PMEVTYPER15_EL0   = 0xdf6f, // 11  011  1110  1101  111
+	A64SysReg_PMEVTYPER16_EL0   = 0xdf70, // 11  011  1110  1110  000
+	A64SysReg_PMEVTYPER17_EL0   = 0xdf71, // 11  011  1110  1110  001
+	A64SysReg_PMEVTYPER18_EL0   = 0xdf72, // 11  011  1110  1110  010
+	A64SysReg_PMEVTYPER19_EL0   = 0xdf73, // 11  011  1110  1110  011
+	A64SysReg_PMEVTYPER20_EL0   = 0xdf74, // 11  011  1110  1110  100
+	A64SysReg_PMEVTYPER21_EL0   = 0xdf75, // 11  011  1110  1110  101
+	A64SysReg_PMEVTYPER22_EL0   = 0xdf76, // 11  011  1110  1110  110
+	A64SysReg_PMEVTYPER23_EL0   = 0xdf77, // 11  011  1110  1110  111
+	A64SysReg_PMEVTYPER24_EL0   = 0xdf78, // 11  011  1110  1111  000
+	A64SysReg_PMEVTYPER25_EL0   = 0xdf79, // 11  011  1110  1111  001
+	A64SysReg_PMEVTYPER26_EL0   = 0xdf7a, // 11  011  1110  1111  010
+	A64SysReg_PMEVTYPER27_EL0   = 0xdf7b, // 11  011  1110  1111  011
+	A64SysReg_PMEVTYPER28_EL0   = 0xdf7c, // 11  011  1110  1111  100
+	A64SysReg_PMEVTYPER29_EL0   = 0xdf7d, // 11  011  1110  1111  101
+	A64SysReg_PMEVTYPER30_EL0   = 0xdf7e, // 11  011  1110  1111  110
+
+	// Trace registers
+	A64SysReg_TRCPRGCTLR        = 0x8808, // 10  001  0000  0001  000
+	A64SysReg_TRCPROCSELR       = 0x8810, // 10  001  0000  0010  000
+	A64SysReg_TRCCONFIGR        = 0x8820, // 10  001  0000  0100  000
+	A64SysReg_TRCAUXCTLR        = 0x8830, // 10  001  0000  0110  000
+	A64SysReg_TRCEVENTCTL0R     = 0x8840, // 10  001  0000  1000  000
+	A64SysReg_TRCEVENTCTL1R     = 0x8848, // 10  001  0000  1001  000
+	A64SysReg_TRCSTALLCTLR      = 0x8858, // 10  001  0000  1011  000
+	A64SysReg_TRCTSCTLR         = 0x8860, // 10  001  0000  1100  000
+	A64SysReg_TRCSYNCPR         = 0x8868, // 10  001  0000  1101  000
+	A64SysReg_TRCCCCTLR         = 0x8870, // 10  001  0000  1110  000
+	A64SysReg_TRCBBCTLR         = 0x8878, // 10  001  0000  1111  000
+	A64SysReg_TRCTRACEIDR       = 0x8801, // 10  001  0000  0000  001
+	A64SysReg_TRCQCTLR          = 0x8809, // 10  001  0000  0001  001
+	A64SysReg_TRCVICTLR         = 0x8802, // 10  001  0000  0000  010
+	A64SysReg_TRCVIIECTLR       = 0x880a, // 10  001  0000  0001  010
+	A64SysReg_TRCVISSCTLR       = 0x8812, // 10  001  0000  0010  010
+	A64SysReg_TRCVIPCSSCTLR     = 0x881a, // 10  001  0000  0011  010
+	A64SysReg_TRCVDCTLR         = 0x8842, // 10  001  0000  1000  010
+	A64SysReg_TRCVDSACCTLR      = 0x884a, // 10  001  0000  1001  010
+	A64SysReg_TRCVDARCCTLR      = 0x8852, // 10  001  0000  1010  010
+	A64SysReg_TRCSEQEVR0        = 0x8804, // 10  001  0000  0000  100
+	A64SysReg_TRCSEQEVR1        = 0x880c, // 10  001  0000  0001  100
+	A64SysReg_TRCSEQEVR2        = 0x8814, // 10  001  0000  0010  100
+	A64SysReg_TRCSEQRSTEVR      = 0x8834, // 10  001  0000  0110  100
+	A64SysReg_TRCSEQSTR         = 0x883c, // 10  001  0000  0111  100
+	A64SysReg_TRCEXTINSELR      = 0x8844, // 10  001  0000  1000  100
+	A64SysReg_TRCCNTRLDVR0      = 0x8805, // 10  001  0000  0000  101
+	A64SysReg_TRCCNTRLDVR1      = 0x880d, // 10  001  0000  0001  101
+	A64SysReg_TRCCNTRLDVR2      = 0x8815, // 10  001  0000  0010  101
+	A64SysReg_TRCCNTRLDVR3      = 0x881d, // 10  001  0000  0011  101
+	A64SysReg_TRCCNTCTLR0       = 0x8825, // 10  001  0000  0100  101
+	A64SysReg_TRCCNTCTLR1       = 0x882d, // 10  001  0000  0101  101
+	A64SysReg_TRCCNTCTLR2       = 0x8835, // 10  001  0000  0110  101
+	A64SysReg_TRCCNTCTLR3       = 0x883d, // 10  001  0000  0111  101
+	A64SysReg_TRCCNTVR0         = 0x8845, // 10  001  0000  1000  101
+	A64SysReg_TRCCNTVR1         = 0x884d, // 10  001  0000  1001  101
+	A64SysReg_TRCCNTVR2         = 0x8855, // 10  001  0000  1010  101
+	A64SysReg_TRCCNTVR3         = 0x885d, // 10  001  0000  1011  101
+	A64SysReg_TRCIMSPEC0        = 0x8807, // 10  001  0000  0000  111
+	A64SysReg_TRCIMSPEC1        = 0x880f, // 10  001  0000  0001  111
+	A64SysReg_TRCIMSPEC2        = 0x8817, // 10  001  0000  0010  111
+	A64SysReg_TRCIMSPEC3        = 0x881f, // 10  001  0000  0011  111
+	A64SysReg_TRCIMSPEC4        = 0x8827, // 10  001  0000  0100  111
+	A64SysReg_TRCIMSPEC5        = 0x882f, // 10  001  0000  0101  111
+	A64SysReg_TRCIMSPEC6        = 0x8837, // 10  001  0000  0110  111
+	A64SysReg_TRCIMSPEC7        = 0x883f, // 10  001  0000  0111  111
+	A64SysReg_TRCRSCTLR2        = 0x8890, // 10  001  0001  0010  000
+	A64SysReg_TRCRSCTLR3        = 0x8898, // 10  001  0001  0011  000
+	A64SysReg_TRCRSCTLR4        = 0x88a0, // 10  001  0001  0100  000
+	A64SysReg_TRCRSCTLR5        = 0x88a8, // 10  001  0001  0101  000
+	A64SysReg_TRCRSCTLR6        = 0x88b0, // 10  001  0001  0110  000
+	A64SysReg_TRCRSCTLR7        = 0x88b8, // 10  001  0001  0111  000
+	A64SysReg_TRCRSCTLR8        = 0x88c0, // 10  001  0001  1000  000
+	A64SysReg_TRCRSCTLR9        = 0x88c8, // 10  001  0001  1001  000
+	A64SysReg_TRCRSCTLR10       = 0x88d0, // 10  001  0001  1010  000
+	A64SysReg_TRCRSCTLR11       = 0x88d8, // 10  001  0001  1011  000
+	A64SysReg_TRCRSCTLR12       = 0x88e0, // 10  001  0001  1100  000
+	A64SysReg_TRCRSCTLR13       = 0x88e8, // 10  001  0001  1101  000
+	A64SysReg_TRCRSCTLR14       = 0x88f0, // 10  001  0001  1110  000
+	A64SysReg_TRCRSCTLR15       = 0x88f8, // 10  001  0001  1111  000
+	A64SysReg_TRCRSCTLR16       = 0x8881, // 10  001  0001  0000  001
+	A64SysReg_TRCRSCTLR17       = 0x8889, // 10  001  0001  0001  001
+	A64SysReg_TRCRSCTLR18       = 0x8891, // 10  001  0001  0010  001
+	A64SysReg_TRCRSCTLR19       = 0x8899, // 10  001  0001  0011  001
+	A64SysReg_TRCRSCTLR20       = 0x88a1, // 10  001  0001  0100  001
+	A64SysReg_TRCRSCTLR21       = 0x88a9, // 10  001  0001  0101  001
+	A64SysReg_TRCRSCTLR22       = 0x88b1, // 10  001  0001  0110  001
+	A64SysReg_TRCRSCTLR23       = 0x88b9, // 10  001  0001  0111  001
+	A64SysReg_TRCRSCTLR24       = 0x88c1, // 10  001  0001  1000  001
+	A64SysReg_TRCRSCTLR25       = 0x88c9, // 10  001  0001  1001  001
+	A64SysReg_TRCRSCTLR26       = 0x88d1, // 10  001  0001  1010  001
+	A64SysReg_TRCRSCTLR27       = 0x88d9, // 10  001  0001  1011  001
+	A64SysReg_TRCRSCTLR28       = 0x88e1, // 10  001  0001  1100  001
+	A64SysReg_TRCRSCTLR29       = 0x88e9, // 10  001  0001  1101  001
+	A64SysReg_TRCRSCTLR30       = 0x88f1, // 10  001  0001  1110  001
+	A64SysReg_TRCRSCTLR31       = 0x88f9, // 10  001  0001  1111  001
+	A64SysReg_TRCSSCCR0         = 0x8882, // 10  001  0001  0000  010
+	A64SysReg_TRCSSCCR1         = 0x888a, // 10  001  0001  0001  010
+	A64SysReg_TRCSSCCR2         = 0x8892, // 10  001  0001  0010  010
+	A64SysReg_TRCSSCCR3         = 0x889a, // 10  001  0001  0011  010
+	A64SysReg_TRCSSCCR4         = 0x88a2, // 10  001  0001  0100  010
+	A64SysReg_TRCSSCCR5         = 0x88aa, // 10  001  0001  0101  010
+	A64SysReg_TRCSSCCR6         = 0x88b2, // 10  001  0001  0110  010
+	A64SysReg_TRCSSCCR7         = 0x88ba, // 10  001  0001  0111  010
+	A64SysReg_TRCSSCSR0         = 0x88c2, // 10  001  0001  1000  010
+	A64SysReg_TRCSSCSR1         = 0x88ca, // 10  001  0001  1001  010
+	A64SysReg_TRCSSCSR2         = 0x88d2, // 10  001  0001  1010  010
+	A64SysReg_TRCSSCSR3         = 0x88da, // 10  001  0001  1011  010
+	A64SysReg_TRCSSCSR4         = 0x88e2, // 10  001  0001  1100  010
+	A64SysReg_TRCSSCSR5         = 0x88ea, // 10  001  0001  1101  010
+	A64SysReg_TRCSSCSR6         = 0x88f2, // 10  001  0001  1110  010
+	A64SysReg_TRCSSCSR7         = 0x88fa, // 10  001  0001  1111  010
+	A64SysReg_TRCSSPCICR0       = 0x8883, // 10  001  0001  0000  011
+	A64SysReg_TRCSSPCICR1       = 0x888b, // 10  001  0001  0001  011
+	A64SysReg_TRCSSPCICR2       = 0x8893, // 10  001  0001  0010  011
+	A64SysReg_TRCSSPCICR3       = 0x889b, // 10  001  0001  0011  011
+	A64SysReg_TRCSSPCICR4       = 0x88a3, // 10  001  0001  0100  011
+	A64SysReg_TRCSSPCICR5       = 0x88ab, // 10  001  0001  0101  011
+	A64SysReg_TRCSSPCICR6       = 0x88b3, // 10  001  0001  0110  011
+	A64SysReg_TRCSSPCICR7       = 0x88bb, // 10  001  0001  0111  011
+	A64SysReg_TRCPDCR           = 0x88a4, // 10  001  0001  0100  100
+	A64SysReg_TRCACVR0          = 0x8900, // 10  001  0010  0000  000
+	A64SysReg_TRCACVR1          = 0x8910, // 10  001  0010  0010  000
+	A64SysReg_TRCACVR2          = 0x8920, // 10  001  0010  0100  000
+	A64SysReg_TRCACVR3          = 0x8930, // 10  001  0010  0110  000
+	A64SysReg_TRCACVR4          = 0x8940, // 10  001  0010  1000  000
+	A64SysReg_TRCACVR5          = 0x8950, // 10  001  0010  1010  000
+	A64SysReg_TRCACVR6          = 0x8960, // 10  001  0010  1100  000
+	A64SysReg_TRCACVR7          = 0x8970, // 10  001  0010  1110  000
+	A64SysReg_TRCACVR8          = 0x8901, // 10  001  0010  0000  001
+	A64SysReg_TRCACVR9          = 0x8911, // 10  001  0010  0010  001
+	A64SysReg_TRCACVR10         = 0x8921, // 10  001  0010  0100  001
+	A64SysReg_TRCACVR11         = 0x8931, // 10  001  0010  0110  001
+	A64SysReg_TRCACVR12         = 0x8941, // 10  001  0010  1000  001
+	A64SysReg_TRCACVR13         = 0x8951, // 10  001  0010  1010  001
+	A64SysReg_TRCACVR14         = 0x8961, // 10  001  0010  1100  001
+	A64SysReg_TRCACVR15         = 0x8971, // 10  001  0010  1110  001
+	A64SysReg_TRCACATR0         = 0x8902, // 10  001  0010  0000  010
+	A64SysReg_TRCACATR1         = 0x8912, // 10  001  0010  0010  010
+	A64SysReg_TRCACATR2         = 0x8922, // 10  001  0010  0100  010
+	A64SysReg_TRCACATR3         = 0x8932, // 10  001  0010  0110  010
+	A64SysReg_TRCACATR4         = 0x8942, // 10  001  0010  1000  010
+	A64SysReg_TRCACATR5         = 0x8952, // 10  001  0010  1010  010
+	A64SysReg_TRCACATR6         = 0x8962, // 10  001  0010  1100  010
+	A64SysReg_TRCACATR7         = 0x8972, // 10  001  0010  1110  010
+	A64SysReg_TRCACATR8         = 0x8903, // 10  001  0010  0000  011
+	A64SysReg_TRCACATR9         = 0x8913, // 10  001  0010  0010  011
+	A64SysReg_TRCACATR10        = 0x8923, // 10  001  0010  0100  011
+	A64SysReg_TRCACATR11        = 0x8933, // 10  001  0010  0110  011
+	A64SysReg_TRCACATR12        = 0x8943, // 10  001  0010  1000  011
+	A64SysReg_TRCACATR13        = 0x8953, // 10  001  0010  1010  011
+	A64SysReg_TRCACATR14        = 0x8963, // 10  001  0010  1100  011
+	A64SysReg_TRCACATR15        = 0x8973, // 10  001  0010  1110  011
+	A64SysReg_TRCDVCVR0         = 0x8904, // 10  001  0010  0000  100
+	A64SysReg_TRCDVCVR1         = 0x8924, // 10  001  0010  0100  100
+	A64SysReg_TRCDVCVR2         = 0x8944, // 10  001  0010  1000  100
+	A64SysReg_TRCDVCVR3         = 0x8964, // 10  001  0010  1100  100
+	A64SysReg_TRCDVCVR4         = 0x8905, // 10  001  0010  0000  101
+	A64SysReg_TRCDVCVR5         = 0x8925, // 10  001  0010  0100  101
+	A64SysReg_TRCDVCVR6         = 0x8945, // 10  001  0010  1000  101
+	A64SysReg_TRCDVCVR7         = 0x8965, // 10  001  0010  1100  101
+	A64SysReg_TRCDVCMR0         = 0x8906, // 10  001  0010  0000  110
+	A64SysReg_TRCDVCMR1         = 0x8926, // 10  001  0010  0100  110
+	A64SysReg_TRCDVCMR2         = 0x8946, // 10  001  0010  1000  110
+	A64SysReg_TRCDVCMR3         = 0x8966, // 10  001  0010  1100  110
+	A64SysReg_TRCDVCMR4         = 0x8907, // 10  001  0010  0000  111
+	A64SysReg_TRCDVCMR5         = 0x8927, // 10  001  0010  0100  111
+	A64SysReg_TRCDVCMR6         = 0x8947, // 10  001  0010  1000  111
+	A64SysReg_TRCDVCMR7         = 0x8967, // 10  001  0010  1100  111
+	A64SysReg_TRCCIDCVR0        = 0x8980, // 10  001  0011  0000  000
+	A64SysReg_TRCCIDCVR1        = 0x8990, // 10  001  0011  0010  000
+	A64SysReg_TRCCIDCVR2        = 0x89a0, // 10  001  0011  0100  000
+	A64SysReg_TRCCIDCVR3        = 0x89b0, // 10  001  0011  0110  000
+	A64SysReg_TRCCIDCVR4        = 0x89c0, // 10  001  0011  1000  000
+	A64SysReg_TRCCIDCVR5        = 0x89d0, // 10  001  0011  1010  000
+	A64SysReg_TRCCIDCVR6        = 0x89e0, // 10  001  0011  1100  000
+	A64SysReg_TRCCIDCVR7        = 0x89f0, // 10  001  0011  1110  000
+	A64SysReg_TRCVMIDCVR0       = 0x8981, // 10  001  0011  0000  001
+	A64SysReg_TRCVMIDCVR1       = 0x8991, // 10  001  0011  0010  001
+	A64SysReg_TRCVMIDCVR2       = 0x89a1, // 10  001  0011  0100  001
+	A64SysReg_TRCVMIDCVR3       = 0x89b1, // 10  001  0011  0110  001
+	A64SysReg_TRCVMIDCVR4       = 0x89c1, // 10  001  0011  1000  001
+	A64SysReg_TRCVMIDCVR5       = 0x89d1, // 10  001  0011  1010  001
+	A64SysReg_TRCVMIDCVR6       = 0x89e1, // 10  001  0011  1100  001
+	A64SysReg_TRCVMIDCVR7       = 0x89f1, // 10  001  0011  1110  001
+	A64SysReg_TRCCIDCCTLR0      = 0x8982, // 10  001  0011  0000  010
+	A64SysReg_TRCCIDCCTLR1      = 0x898a, // 10  001  0011  0001  010
+	A64SysReg_TRCVMIDCCTLR0     = 0x8992, // 10  001  0011  0010  010
+	A64SysReg_TRCVMIDCCTLR1     = 0x899a, // 10  001  0011  0011  010
+	A64SysReg_TRCITCTRL         = 0x8b84, // 10  001  0111  0000  100
+	A64SysReg_TRCCLAIMSET       = 0x8bc6, // 10  001  0111  1000  110
+	A64SysReg_TRCCLAIMCLR       = 0x8bce, // 10  001  0111  1001  110
+
+	// GICv3 registers
+	A64SysReg_ICC_BPR1_EL1      = 0xc663, // 11  000  1100  1100  011
+	A64SysReg_ICC_BPR0_EL1      = 0xc643, // 11  000  1100  1000  011
+	A64SysReg_ICC_PMR_EL1       = 0xc230, // 11  000  0100  0110  000
+	A64SysReg_ICC_CTLR_EL1      = 0xc664, // 11  000  1100  1100  100
+	A64SysReg_ICC_CTLR_EL3      = 0xf664, // 11  110  1100  1100  100
+	A64SysReg_ICC_SRE_EL1       = 0xc665, // 11  000  1100  1100  101
+	A64SysReg_ICC_SRE_EL2       = 0xe64d, // 11  100  1100  1001  101
+	A64SysReg_ICC_SRE_EL3       = 0xf665, // 11  110  1100  1100  101
+	A64SysReg_ICC_IGRPEN0_EL1   = 0xc666, // 11  000  1100  1100  110
+	A64SysReg_ICC_IGRPEN1_EL1   = 0xc667, // 11  000  1100  1100  111
+	A64SysReg_ICC_IGRPEN1_EL3   = 0xf667, // 11  110  1100  1100  111
+	A64SysReg_ICC_SEIEN_EL1     = 0xc668, // 11  000  1100  1101  000
+	A64SysReg_ICC_AP0R0_EL1     = 0xc644, // 11  000  1100  1000  100
+	A64SysReg_ICC_AP0R1_EL1     = 0xc645, // 11  000  1100  1000  101
+	A64SysReg_ICC_AP0R2_EL1     = 0xc646, // 11  000  1100  1000  110
+	A64SysReg_ICC_AP0R3_EL1     = 0xc647, // 11  000  1100  1000  111
+	A64SysReg_ICC_AP1R0_EL1     = 0xc648, // 11  000  1100  1001  000
+	A64SysReg_ICC_AP1R1_EL1     = 0xc649, // 11  000  1100  1001  001
+	A64SysReg_ICC_AP1R2_EL1     = 0xc64a, // 11  000  1100  1001  010
+	A64SysReg_ICC_AP1R3_EL1     = 0xc64b, // 11  000  1100  1001  011
+	A64SysReg_ICH_AP0R0_EL2     = 0xe640, // 11  100  1100  1000  000
+	A64SysReg_ICH_AP0R1_EL2     = 0xe641, // 11  100  1100  1000  001
+	A64SysReg_ICH_AP0R2_EL2     = 0xe642, // 11  100  1100  1000  010
+	A64SysReg_ICH_AP0R3_EL2     = 0xe643, // 11  100  1100  1000  011
+	A64SysReg_ICH_AP1R0_EL2     = 0xe648, // 11  100  1100  1001  000
+	A64SysReg_ICH_AP1R1_EL2     = 0xe649, // 11  100  1100  1001  001
+	A64SysReg_ICH_AP1R2_EL2     = 0xe64a, // 11  100  1100  1001  010
+	A64SysReg_ICH_AP1R3_EL2     = 0xe64b, // 11  100  1100  1001  011
+	A64SysReg_ICH_HCR_EL2       = 0xe658, // 11  100  1100  1011  000
+	A64SysReg_ICH_MISR_EL2      = 0xe65a, // 11  100  1100  1011  010
+	A64SysReg_ICH_VMCR_EL2      = 0xe65f, // 11  100  1100  1011  111
+	A64SysReg_ICH_VSEIR_EL2     = 0xe64c, // 11  100  1100  1001  100
+	A64SysReg_ICH_LR0_EL2       = 0xe660, // 11  100  1100  1100  000
+	A64SysReg_ICH_LR1_EL2       = 0xe661, // 11  100  1100  1100  001
+	A64SysReg_ICH_LR2_EL2       = 0xe662, // 11  100  1100  1100  010
+	A64SysReg_ICH_LR3_EL2       = 0xe663, // 11  100  1100  1100  011
+	A64SysReg_ICH_LR4_EL2       = 0xe664, // 11  100  1100  1100  100
+	A64SysReg_ICH_LR5_EL2       = 0xe665, // 11  100  1100  1100  101
+	A64SysReg_ICH_LR6_EL2       = 0xe666, // 11  100  1100  1100  110
+	A64SysReg_ICH_LR7_EL2       = 0xe667, // 11  100  1100  1100  111
+	A64SysReg_ICH_LR8_EL2       = 0xe668, // 11  100  1100  1101  000
+	A64SysReg_ICH_LR9_EL2       = 0xe669, // 11  100  1100  1101  001
+	A64SysReg_ICH_LR10_EL2      = 0xe66a, // 11  100  1100  1101  010
+	A64SysReg_ICH_LR11_EL2      = 0xe66b, // 11  100  1100  1101  011
+	A64SysReg_ICH_LR12_EL2      = 0xe66c, // 11  100  1100  1101  100
+	A64SysReg_ICH_LR13_EL2      = 0xe66d, // 11  100  1100  1101  101
+	A64SysReg_ICH_LR14_EL2      = 0xe66e, // 11  100  1100  1101  110
+	A64SysReg_ICH_LR15_EL2      = 0xe66f  // 11  100  1100  1101  111
+};
+
+// Cyclone specific system registers
+enum A64CycloneSysRegValues {
+	A64SysReg_CPM_IOACC_CTL_EL3 = 0xff90
+};
+
+enum A64TLBIValues {
+	A64TLBI_Invalid = -1,          // Op0 Op1  CRn   CRm   Op2
+	A64TLBI_IPAS2E1IS    = 0x6401, // 01  100  1000  0000  001
+	A64TLBI_IPAS2LE1IS   = 0x6405, // 01  100  1000  0000  101
+	A64TLBI_VMALLE1IS    = 0x4418, // 01  000  1000  0011  000
+	A64TLBI_ALLE2IS      = 0x6418, // 01  100  1000  0011  000
+	A64TLBI_ALLE3IS      = 0x7418, // 01  110  1000  0011  000
+	A64TLBI_VAE1IS       = 0x4419, // 01  000  1000  0011  001
+	A64TLBI_VAE2IS       = 0x6419, // 01  100  1000  0011  001
+	A64TLBI_VAE3IS       = 0x7419, // 01  110  1000  0011  001
+	A64TLBI_ASIDE1IS     = 0x441a, // 01  000  1000  0011  010
+	A64TLBI_VAAE1IS      = 0x441b, // 01  000  1000  0011  011
+	A64TLBI_ALLE1IS      = 0x641c, // 01  100  1000  0011  100
+	A64TLBI_VALE1IS      = 0x441d, // 01  000  1000  0011  101
+	A64TLBI_VALE2IS      = 0x641d, // 01  100  1000  0011  101
+	A64TLBI_VALE3IS      = 0x741d, // 01  110  1000  0011  101
+	A64TLBI_VMALLS12E1IS = 0x641e, // 01  100  1000  0011  110
+	A64TLBI_VAALE1IS     = 0x441f, // 01  000  1000  0011  111
+	A64TLBI_IPAS2E1      = 0x6421, // 01  100  1000  0100  001
+	A64TLBI_IPAS2LE1     = 0x6425, // 01  100  1000  0100  101
+	A64TLBI_VMALLE1      = 0x4438, // 01  000  1000  0111  000
+	A64TLBI_ALLE2        = 0x6438, // 01  100  1000  0111  000
+	A64TLBI_ALLE3        = 0x7438, // 01  110  1000  0111  000
+	A64TLBI_VAE1         = 0x4439, // 01  000  1000  0111  001
+	A64TLBI_VAE2         = 0x6439, // 01  100  1000  0111  001
+	A64TLBI_VAE3         = 0x7439, // 01  110  1000  0111  001
+	A64TLBI_ASIDE1       = 0x443a, // 01  000  1000  0111  010
+	A64TLBI_VAAE1        = 0x443b, // 01  000  1000  0111  011
+	A64TLBI_ALLE1        = 0x643c, // 01  100  1000  0111  100
+	A64TLBI_VALE1        = 0x443d, // 01  000  1000  0111  101
+	A64TLBI_VALE2        = 0x643d, // 01  100  1000  0111  101
+	A64TLBI_VALE3        = 0x743d, // 01  110  1000  0111  101
+	A64TLBI_VMALLS12E1   = 0x643e, // 01  100  1000  0111  110
+	A64TLBI_VAALE1       = 0x443f  // 01  000  1000  0111  111
+};
+
+bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm);
+
+char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid);
+
+uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid);
+
+bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value);
+
+void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result);
+
+#endif

src/3rd-party/capstone/capstone/arch/AArch64/AArch64Disassembler.h

@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_AARCH64_DISASSEMBLER_H
+#define CS_AARCH64_DISASSEMBLER_H
+
+#include <stdint.h>
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void AArch64_init(MCRegisterInfo *MRI);
+
+bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif

src/3rd-party/capstone/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc

@@ -0,0 +1,29 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Subtarget Enumeration Source Fragment                                       *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  AArch64_FeatureCRC =  1ULL << 0,
+  AArch64_FeatureCrypto =  1ULL << 1,
+  AArch64_FeatureFPARMv8 =  1ULL << 2,
+  AArch64_FeatureNEON =  1ULL << 3,
+  AArch64_FeatureZCRegMove =  1ULL << 4,
+  AArch64_FeatureZCZeroing =  1ULL << 5,
+  AArch64_ProcA53 =  1ULL << 6,
+  AArch64_ProcA57 =  1ULL << 7,
+  AArch64_ProcCyclone =  1ULL << 8
+};
+
+#endif // GET_SUBTARGETINFO_ENUM
+

src/3rd-party/capstone/capstone/arch/AArch64/AArch64InstPrinter.h

@@ -0,0 +1,28 @@
+//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an AArch64 MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_AARCH64INSTPRINTER_H
+#define CS_LLVM_AARCH64INSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void AArch64_printInst(MCInst *MI, SStream *O, void *);
+
+void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci);
+
+#endif

src/3rd-party/capstone/capstone/arch/AArch64/AArch64Mapping.h

@@ -0,0 +1,35 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_ARM64_MAP_H
+#define CS_ARM64_MAP_H
+
+#include "../../include/capstone.h"
+
+// return name of regiser in friendly string
+const char *AArch64_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *AArch64_insn_name(csh handle, unsigned int id);
+
+const char *AArch64_group_name(csh handle, unsigned int id);
+
+// map instruction name to public instruction ID
+arm64_reg AArch64_map_insn(const char *name);
+
+// map internal vregister to public register
+arm64_reg AArch64_map_vregister(unsigned int r);
+
+void arm64_op_addReg(MCInst *MI, int reg);
+
+void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp);
+
+void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp);
+
+void arm64_op_addFP(MCInst *MI, float fp);
+
+void arm64_op_addImm(MCInst *MI, int64_t imm);
+
+#endif

src/3rd-party/capstone/capstone/arch/AArch64/AArch64Module.c

@@ -0,0 +1,55 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#ifdef CAPSTONE_HAS_ARM64
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "AArch64Disassembler.h"
+#include "AArch64InstPrinter.h"
+#include "AArch64Mapping.h"
+
+static cs_err init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	// verify if requested mode is valid
+	if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN))
+		return CS_ERR_MODE;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	AArch64_init(mri);
+	ud->printer = AArch64_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = AArch64_getInstruction;
+	ud->reg_name = AArch64_reg_name;
+	ud->insn_id = AArch64_get_insn_id;
+	ud->insn_name = AArch64_insn_name;
+	ud->group_name = AArch64_group_name;
+	ud->post_printer = AArch64_post_printer;
+
+	return CS_ERR_OK;
+}
+
+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	return CS_ERR_OK;
+}
+
+static void destroy(cs_struct *handle)
+{
+}
+
+void AArch64_enable(void)
+{
+	arch_init[CS_ARCH_ARM64] = init;
+	arch_option[CS_ARCH_ARM64] = option;
+	arch_destroy[CS_ARCH_ARM64] = destroy;
+
+	// support this arch
+	all_arch |= (1 << CS_ARCH_ARM64);
+}
+
+#endif

src/3rd-party/capstone/capstone/arch/ARM/ARMAddressingModes.h

@@ -0,0 +1,670 @@
+//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the ARM addressing mode implementation stuff.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
+#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
+
+#include "../../include/platform.h"
+#include "../../MathExtras.h"
+
+/// ARM_AM - ARM Addressing Mode Stuff
+typedef enum ARM_AM_ShiftOpc {
+	ARM_AM_no_shift = 0,
+	ARM_AM_asr,
+	ARM_AM_lsl,
+	ARM_AM_lsr,
+	ARM_AM_ror,
+	ARM_AM_rrx
+} ARM_AM_ShiftOpc;
+
+typedef enum ARM_AM_AddrOpc {
+	ARM_AM_sub = 0,
+	ARM_AM_add
+} ARM_AM_AddrOpc;
+
+static inline char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
+{
+	return Op == ARM_AM_sub ? "-" : "";
+}
+
+static inline char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
+{
+	switch (Op) {
+		default: return "";	//llvm_unreachable("Unknown shift opc!");
+		case ARM_AM_asr: return "asr";
+		case ARM_AM_lsl: return "lsl";
+		case ARM_AM_lsr: return "lsr";
+		case ARM_AM_ror: return "ror";
+		case ARM_AM_rrx: return "rrx";
+	}
+}
+
+static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
+{
+	switch (Op) {
+		default: return (unsigned int)-1;	//llvm_unreachable("Unknown shift opc!");
+		case ARM_AM_asr: return 2;
+		case ARM_AM_lsl: return 0;
+		case ARM_AM_lsr: return 1;
+		case ARM_AM_ror: return 3;
+	}
+}
+
+typedef enum ARM_AM_AMSubMode {
+	ARM_AM_bad_am_submode = 0,
+	ARM_AM_ia,
+	ARM_AM_ib,
+	ARM_AM_da,
+	ARM_AM_db
+} ARM_AM_AMSubMode;
+
+static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode)
+{
+	switch (Mode) {
+		default: return "";
+		case ARM_AM_ia: return "ia";
+		case ARM_AM_ib: return "ib";
+		case ARM_AM_da: return "da";
+		case ARM_AM_db: return "db";
+	}
+}
+
+/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
+///
+static inline unsigned rotr32(unsigned Val, unsigned Amt)
+{
+	//assert(Amt < 32 && "Invalid rotate amount");
+	return (Val >> Amt) | (Val << ((32-Amt)&31));
+}
+
+/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
+///
+static inline unsigned rotl32(unsigned Val, unsigned Amt)
+{
+	//assert(Amt < 32 && "Invalid rotate amount");
+	return (Val << Amt) | (Val >> ((32-Amt)&31));
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #1: shift_operand with registers
+//===--------------------------------------------------------------------===//
+//
+// This 'addressing mode' is used for arithmetic instructions.  It can
+// represent things like:
+//   reg
+//   reg [asr|lsl|lsr|ror|rrx] reg
+//   reg [asr|lsl|lsr|ror|rrx] imm
+//
+// This is stored three operands [rega, regb, opc].  The first is the base
+// reg, the second is the shift amount (or reg0 if not present or imm).  The
+// third operand encodes the shift opcode and the imm if a reg isn't present.
+//
+static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
+{
+	return ShOp | (Imm << 3);
+}
+
+static inline unsigned getSORegOffset(unsigned Op)
+{
+	return Op >> 3;
+}
+
+static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
+{
+	return (ARM_AM_ShiftOpc)(Op & 7);
+}
+
+/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
+/// the 8-bit imm value.
+static inline unsigned getSOImmValImm(unsigned Imm)
+{
+	return Imm & 0xFF;
+}
+
+/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
+/// the rotate amount.
+static inline unsigned getSOImmValRot(unsigned Imm)
+{
+	return (Imm >> 8) * 2;
+}
+
+/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
+/// computing the rotate amount to use.  If this immediate value cannot be
+/// handled with a single shifter-op, determine a good rotate amount that will
+/// take a maximal chunk of bits out of the immediate.
+static inline unsigned getSOImmValRotate(unsigned Imm)
+{
+	unsigned TZ, RotAmt;
+	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
+	// of zero.
+	if ((Imm & ~255U) == 0) return 0;
+
+	// Use CTZ to compute the rotate amount.
+	TZ = CountTrailingZeros_32(Imm);
+
+	// Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
+	// not 9.
+	RotAmt = TZ & ~1;
+
+	// If we can handle this spread, return it.
+	if ((rotr32(Imm, RotAmt) & ~255U) == 0)
+		return (32-RotAmt)&31;  // HW rotates right, not left.
+
+	// For values like 0xF000000F, we should ignore the low 6 bits, then
+	// retry the hunt.
+	if (Imm & 63U) {
+		unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
+		unsigned RotAmt2 = TZ2 & ~1;
+		if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
+			return (32-RotAmt2)&31;  // HW rotates right, not left.
+	}
+
+	// Otherwise, we have no way to cover this span of bits with a single
+	// shifter_op immediate.  Return a chunk of bits that will be useful to
+	// handle.
+	return (32-RotAmt)&31;  // HW rotates right, not left.
+}
+
+/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
+/// into an shifter_operand immediate operand, return the 12-bit encoding for
+/// it.  If not, return -1.
+static inline int getSOImmVal(unsigned Arg)
+{
+	unsigned RotAmt;
+	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
+	// of zero.
+	if ((Arg & ~255U) == 0) return Arg;
+
+	RotAmt = getSOImmValRotate(Arg);
+
+	// If this cannot be handled with a single shifter_op, bail out.
+	if (rotr32(~255U, RotAmt) & Arg)
+		return -1;
+
+	// Encode this correctly.
+	return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
+}
+
+/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
+/// or'ing together two SOImmVal's.
+static inline bool isSOImmTwoPartVal(unsigned V)
+{
+	// If this can be handled with a single shifter_op, bail out.
+	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	if (V == 0)
+		return false;
+
+	// If this can be handled with two shifter_op's, accept.
+	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	return V == 0;
+}
+
+/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
+/// return the first chunk of it.
+static inline unsigned getSOImmTwoPartFirst(unsigned V)
+{
+	return rotr32(255U, getSOImmValRotate(V)) & V;
+}
+
+/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
+/// return the second chunk of it.
+static inline unsigned getSOImmTwoPartSecond(unsigned V)
+{
+	// Mask out the first hunk.
+	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+
+	// Take what's left.
+	//assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
+	return V;
+}
+
+/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
+/// by a left shift. Returns the shift amount to use.
+static inline unsigned getThumbImmValShift(unsigned Imm)
+{
+	// 8-bit (or less) immediates are trivially immediate operand with a shift
+	// of zero.
+	if ((Imm & ~255U) == 0) return 0;
+
+	// Use CTZ to compute the shift amount.
+	return CountTrailingZeros_32(Imm);
+}
+
+/// isThumbImmShiftedVal - Return true if the specified value can be obtained
+/// by left shifting a 8-bit immediate.
+static inline bool isThumbImmShiftedVal(unsigned V)
+{
+	// If this can be handled with
+	V = (~255U << getThumbImmValShift(V)) & V;
+	return V == 0;
+}
+
+/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
+/// by a left shift. Returns the shift amount to use.
+static inline unsigned getThumbImm16ValShift(unsigned Imm)
+{
+	// 16-bit (or less) immediates are trivially immediate operand with a shift
+	// of zero.
+	if ((Imm & ~65535U) == 0) return 0;
+
+	// Use CTZ to compute the shift amount.
+	return CountTrailingZeros_32(Imm);
+}
+
+/// isThumbImm16ShiftedVal - Return true if the specified value can be
+/// obtained by left shifting a 16-bit immediate.
+static inline bool isThumbImm16ShiftedVal(unsigned V)
+{
+	// If this can be handled with
+	V = (~65535U << getThumbImm16ValShift(V)) & V;
+	return V == 0;
+}
+
+/// getThumbImmNonShiftedVal - If V is a value that satisfies
+/// isThumbImmShiftedVal, return the non-shiftd value.
+static inline unsigned getThumbImmNonShiftedVal(unsigned V)
+{
+	return V >> getThumbImmValShift(V);
+}
+
+
+/// getT2SOImmValSplat - Return the 12-bit encoded representation
+/// if the specified value can be obtained by splatting the low 8 bits
+/// into every other byte or every byte of a 32-bit value. i.e.,
+///     00000000 00000000 00000000 abcdefgh    control = 0
+///     00000000 abcdefgh 00000000 abcdefgh    control = 1
+///     abcdefgh 00000000 abcdefgh 00000000    control = 2
+///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
+/// Return -1 if none of the above apply.
+/// See ARM Reference Manual A6.3.2.
+static inline int getT2SOImmValSplatVal(unsigned V)
+{
+	unsigned u, Vs, Imm;
+	// control = 0
+	if ((V & 0xffffff00) == 0)
+		return V;
+
+	// If the value is zeroes in the first byte, just shift those off
+	Vs = ((V & 0xff) == 0) ? V >> 8 : V;
+	// Any passing value only has 8 bits of payload, splatted across the word
+	Imm = Vs & 0xff;
+	// Likewise, any passing values have the payload splatted into the 3rd byte
+	u = Imm | (Imm << 16);
+
+	// control = 1 or 2
+	if (Vs == u)
+		return (((Vs == V) ? 1 : 2) << 8) | Imm;
+
+	// control = 3
+	if (Vs == (u | (u << 8)))
+		return (3 << 8) | Imm;
+
+	return -1;
+}
+
+/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
+/// specified value is a rotated 8-bit value. Return -1 if no rotation
+/// encoding is possible.
+/// See ARM Reference Manual A6.3.2.
+static inline int getT2SOImmValRotateVal(unsigned V)
+{
+	unsigned RotAmt = CountLeadingZeros_32(V);
+	if (RotAmt >= 24)
+		return -1;
+
+	// If 'Arg' can be handled with a single shifter_op return the value.
+	if ((rotr32(0xff000000U, RotAmt) & V) == V)
+		return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
+
+	return -1;
+}
+
+/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
+/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
+/// encoding for it.  If not, return -1.
+/// See ARM Reference Manual A6.3.2.
+static inline int getT2SOImmVal(unsigned Arg)
+{
+	int Rot;
+	// If 'Arg' is an 8-bit splat, then get the encoded value.
+	int Splat = getT2SOImmValSplatVal(Arg);
+	if (Splat != -1)
+		return Splat;
+
+	// If 'Arg' can be handled with a single shifter_op return the value.
+	Rot = getT2SOImmValRotateVal(Arg);
+	if (Rot != -1)
+		return Rot;
+
+	return -1;
+}
+
+static inline unsigned getT2SOImmValRotate(unsigned V)
+{
+	unsigned RotAmt;
+
+	if ((V & ~255U) == 0)
+		return 0;
+
+	// Use CTZ to compute the rotate amount.
+	RotAmt = CountTrailingZeros_32(V);
+	return (32 - RotAmt) & 31;
+}
+
+static inline bool isT2SOImmTwoPartVal (unsigned Imm)
+{
+	unsigned V = Imm;
+	// Passing values can be any combination of splat values and shifter
+	// values. If this can be handled with a single shifter or splat, bail
+	// out. Those should be handled directly, not with a two-part val.
+	if (getT2SOImmValSplatVal(V) != -1)
+		return false;
+	V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
+	if (V == 0)
+		return false;
+
+	// If this can be handled as an immediate, accept.
+	if (getT2SOImmVal(V) != -1) return true;
+
+	// Likewise, try masking out a splat value first.
+	V = Imm;
+	if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
+		V &= ~0xff00ff00U;
+	else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
+		V &= ~0x00ff00ffU;
+	// If what's left can be handled as an immediate, accept.
+	if (getT2SOImmVal(V) != -1) return true;
+
+	// Otherwise, do not accept.
+	return false;
+}
+
+static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm)
+{
+	//assert (isT2SOImmTwoPartVal(Imm) &&
+	//        "Immedate cannot be encoded as two part immediate!");
+	// Try a shifter operand as one part
+	unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
+	// If the rest is encodable as an immediate, then return it.
+	if (getT2SOImmVal(V) != -1) return V;
+
+	// Try masking out a splat value first.
+	if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
+		return Imm & 0xff00ff00U;
+
+	// The other splat is all that's left as an option.
+	//assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
+	return Imm & 0x00ff00ffU;
+}
+
+static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
+{
+	// Mask out the first hunk
+	Imm ^= getT2SOImmTwoPartFirst(Imm);
+	// Return what's left
+	//assert (getT2SOImmVal(Imm) != -1 &&
+	//        "Unable to encode second part of T2 two part SO immediate");
+	return Imm;
+}
+
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #2
+//===--------------------------------------------------------------------===//
+//
+// This is used for most simple load/store instructions.
+//
+// addrmode2 := reg +/- reg shop imm
+// addrmode2 := reg +/- imm12
+//
+// The first operand is always a Reg.  The second operand is a reg if in
+// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
+// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
+// fourth operand 16-17 encodes the index mode.
+//
+// If this addressing mode is a frame index (before prolog/epilog insertion
+// and code rewriting), this operand will have the form:  FI#, reg0, <offs>
+// with no shift amount for the frame offset.
+//
+static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO,
+		unsigned IdxMode)
+{
+	//assert(Imm12 < (1 << 12) && "Imm too large!");
+	bool isSub = Opc == ARM_AM_sub;
+	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
+}
+
+static inline unsigned getAM2Offset(unsigned AM2Opc)
+{
+	return AM2Opc & ((1 << 12)-1);
+}
+
+static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc)
+{
+	return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
+{
+	return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
+}
+
+static inline unsigned getAM2IdxMode(unsigned AM2Opc)
+{
+	return (AM2Opc >> 16);
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #3
+//===--------------------------------------------------------------------===//
+//
+// This is used for sign-extending loads, and load/store-pair instructions.
+//
+// addrmode3 := reg +/- reg
+// addrmode3 := reg +/- imm8
+//
+// The first operand is always a Reg.  The second operand is a reg if in
+// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
+// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
+// index mode.
+
+/// getAM3Opc - This function encodes the addrmode3 opc field.
+static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset,
+		unsigned IdxMode)
+{
+	bool isSub = Opc == ARM_AM_sub;
+	return ((int)isSub << 8) | Offset | (IdxMode << 9);
+}
+
+static inline unsigned char getAM3Offset(unsigned AM3Opc)
+{
+	return AM3Opc & 0xFF;
+}
+
+static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc)
+{
+	return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+static inline unsigned getAM3IdxMode(unsigned AM3Opc)
+{
+	return (AM3Opc >> 9);
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #4
+//===--------------------------------------------------------------------===//
+//
+// This is used for load / store multiple instructions.
+//
+// addrmode4 := reg, <mode>
+//
+// The four modes are:
+//    IA - Increment after
+//    IB - Increment before
+//    DA - Decrement after
+//    DB - Decrement before
+// For VFP instructions, only the IA and DB modes are valid.
+
+static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode)
+{
+	return (ARM_AM_AMSubMode)(Mode & 0x7);
+}
+
+static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
+{
+	return (int)SubMode;
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #5
+//===--------------------------------------------------------------------===//
+//
+// This is used for coprocessor instructions, such as FP load/stores.
+//
+// addrmode5 := reg +/- imm8*4
+//
+// The first operand is always a Reg.  The second operand encodes the
+// operation in bit 8 and the immediate in bits 0-7.
+
+/// getAM5Opc - This function encodes the addrmode5 opc field.
+static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
+{
+	bool isSub = Opc == ARM_AM_sub;
+	return ((int)isSub << 8) | Offset;
+}
+static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
+{
+	return AM5Opc & 0xFF;
+}
+static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
+{
+	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #6
+//===--------------------------------------------------------------------===//
+//
+// This is used for NEON load / store instructions.
+//
+// addrmode6 := reg with optional alignment
+//
+// This is stored in two operands [regaddr, align].  The first is the
+// address register.  The second operand is the value of the alignment
+// specifier in bytes or zero if no explicit alignment.
+// Valid alignments depend on the specific instruction.
+
+//===--------------------------------------------------------------------===//
+// NEON Modified Immediates
+//===--------------------------------------------------------------------===//
+//
+// Several NEON instructions (e.g., VMOV) take a "modified immediate"
+// vector operand, where a small immediate encoded in the instruction
+// specifies a full NEON vector value.  These modified immediates are
+// represented here as encoded integers.  The low 8 bits hold the immediate
+// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
+// the "Cmode" field of the instruction.  The interfaces below treat the
+// Op and Cmode values as a single 5-bit value.
+
+static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val)
+{
+	return (OpCmode << 8) | Val;
+}
+static inline unsigned getNEONModImmOpCmode(unsigned ModImm)
+{
+	return (ModImm >> 8) & 0x1f;
+}
+static inline unsigned getNEONModImmVal(unsigned ModImm)
+{
+	return ModImm & 0xff;
+}
+
+/// decodeNEONModImm - Decode a NEON modified immediate value into the
+/// element value and the element size in bits.  (If the element size is
+/// smaller than the vector, it is splatted into all the elements.)
+static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits)
+{
+	unsigned OpCmode = getNEONModImmOpCmode(ModImm);
+	unsigned Imm8 = getNEONModImmVal(ModImm);
+	uint64_t Val = 0;
+	unsigned ByteNum;
+
+	if (OpCmode == 0xe) {
+		// 8-bit vector elements
+		Val = Imm8;
+		*EltBits = 8;
+	} else if ((OpCmode & 0xc) == 0x8) {
+		// 16-bit vector elements
+		ByteNum = (OpCmode & 0x6) >> 1;
+		Val = (uint64_t)Imm8 << (8 * ByteNum);
+		*EltBits = 16;
+	} else if ((OpCmode & 0x8) == 0) {
+		// 32-bit vector elements, zero with one byte set
+		ByteNum = (OpCmode & 0x6) >> 1;
+		Val = (uint64_t)Imm8 << (8 * ByteNum);
+		*EltBits = 32;
+	} else if ((OpCmode & 0xe) == 0xc) {
+		// 32-bit vector elements, one byte with low bits set
+		ByteNum = 1 + (OpCmode & 0x1);
+		Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
+		*EltBits = 32;
+	} else if (OpCmode == 0x1e) {
+		// 64-bit vector elements
+		for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
+			if ((ModImm >> ByteNum) & 1)
+				Val |= (uint64_t)0xff << (8 * ByteNum);
+		}
+		*EltBits = 64;
+	} else {
+		//llvm_unreachable("Unsupported NEON immediate");
+	}
+	return Val;
+}
+
+ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode);
+
+//===--------------------------------------------------------------------===//
+// Floating-point Immediates
+//
+static inline float getFPImmFloat(unsigned Imm)
+{
+	// We expect an 8-bit binary encoding of a floating-point number here.
+	union {
+		uint32_t I;
+		float F;
+	} FPUnion;
+
+	uint8_t Sign = (Imm >> 7) & 0x1;
+	uint8_t Exp = (Imm >> 4) & 0x7;
+	uint8_t Mantissa = Imm & 0xf;
+
+	//   8-bit FP    iEEEE Float Encoding
+	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
+	//
+	// where B = NOT(b);
+
+	FPUnion.I = 0;
+	FPUnion.I |= Sign << 31;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	FPUnion.I |= (Exp & 0x3) << 23;
+	FPUnion.I |= Mantissa << 19;
+	return FPUnion.F;
+}
+
+#endif
+

src/3rd-party/capstone/capstone/arch/ARM/ARMBaseInfo.h

@@ -0,0 +1,432 @@
+//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the ARM target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_ARMBASEINFO_H
+#define CS_ARMBASEINFO_H
+
+#include "../../include/arm.h"
+
+// Defines symbolic names for ARM registers.  This defines a mapping from
+// register name to register number.
+//
+#define GET_REGINFO_ENUM
+#include "ARMGenRegisterInfo.inc"
+
+// Enums corresponding to ARM condition codes
+// The CondCodes constants map directly to the 4-bit encoding of the
+// condition field for predicated instructions.
+typedef enum ARMCC_CondCodes { // Meaning (integer)          Meaning (floating-point)
+	ARMCC_EQ,            // Equal                      Equal
+	ARMCC_NE,            // Not equal                  Not equal, or unordered
+	ARMCC_HS,            // Carry set                  >, ==, or unordered
+	ARMCC_LO,            // Carry clear                Less than
+	ARMCC_MI,            // Minus, negative            Less than
+	ARMCC_PL,            // Plus, positive or zero     >, ==, or unordered
+	ARMCC_VS,            // Overflow                   Unordered
+	ARMCC_VC,            // No overflow                Not unordered
+	ARMCC_HI,            // Unsigned higher            Greater than, or unordered
+	ARMCC_LS,            // Unsigned lower or same     Less than or equal
+	ARMCC_GE,            // Greater than or equal      Greater than or equal
+	ARMCC_LT,            // Less than                  Less than, or unordered
+	ARMCC_GT,            // Greater than               Greater than
+	ARMCC_LE,            // Less than or equal         <, ==, or unordered
+	ARMCC_AL             // Always (unconditional)     Always (unconditional)
+} ARMCC_CondCodes;
+
+inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
+{
+	switch (CC) {
+		case ARMCC_EQ: return ARMCC_NE;
+		case ARMCC_NE: return ARMCC_EQ;
+		case ARMCC_HS: return ARMCC_LO;
+		case ARMCC_LO: return ARMCC_HS;
+		case ARMCC_MI: return ARMCC_PL;
+		case ARMCC_PL: return ARMCC_MI;
+		case ARMCC_VS: return ARMCC_VC;
+		case ARMCC_VC: return ARMCC_VS;
+		case ARMCC_HI: return ARMCC_LS;
+		case ARMCC_LS: return ARMCC_HI;
+		case ARMCC_GE: return ARMCC_LT;
+		case ARMCC_LT: return ARMCC_GE;
+		case ARMCC_GT: return ARMCC_LE;
+		case ARMCC_LE: return ARMCC_GT;
+		default: return ARMCC_AL;
+	}
+}
+
+inline static char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
+{
+	switch (CC) {
+		case ARMCC_EQ:  return "eq";
+		case ARMCC_NE:  return "ne";
+		case ARMCC_HS:  return "hs";
+		case ARMCC_LO:  return "lo";
+		case ARMCC_MI:  return "mi";
+		case ARMCC_PL:  return "pl";
+		case ARMCC_VS:  return "vs";
+		case ARMCC_VC:  return "vc";
+		case ARMCC_HI:  return "hi";
+		case ARMCC_LS:  return "ls";
+		case ARMCC_GE:  return "ge";
+		case ARMCC_LT:  return "lt";
+		case ARMCC_GT:  return "gt";
+		case ARMCC_LE:  return "le";
+		case ARMCC_AL:  return "al";
+		default: return "";
+	}
+}
+
+inline static char *ARM_PROC_IFlagsToString(unsigned val)
+{
+	switch (val) {
+		case ARM_CPSFLAG_F: return "f";
+		case ARM_CPSFLAG_I: return "i";
+		case ARM_CPSFLAG_A: return "a";
+		default: return "";
+	}
+}
+
+inline static char *ARM_PROC_IModToString(unsigned val)
+{
+	switch (val) {
+		case ARM_CPSMODE_IE: return "ie";
+		case ARM_CPSMODE_ID: return "id";
+		default: return "";
+	}
+}
+
+inline static char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
+{
+	switch (val) {
+		default: return "BUGBUG";
+		case ARM_MB_SY:    return "sy";
+		case ARM_MB_ST:    return "st";
+		case ARM_MB_LD: return HasV8 ? "ld" : "#0xd";
+		case ARM_MB_RESERVED_12: return "#0xc";
+		case ARM_MB_ISH:   return "ish";
+		case ARM_MB_ISHST: return "ishst";
+		case ARM_MB_ISHLD: return HasV8 ?  "ishld" : "#0x9";
+		case ARM_MB_RESERVED_8: return "#0x8";
+		case ARM_MB_NSH:   return "nsh";
+		case ARM_MB_NSHST: return "nshst";
+		case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#0x5";
+		case ARM_MB_RESERVED_4: return "#0x4";
+		case ARM_MB_OSH:   return "osh";
+		case ARM_MB_OSHST: return "oshst";
+		case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#0x1";
+		case ARM_MB_RESERVED_0: return "#0x0";
+	}
+}
+
+enum ARM_ISB_InstSyncBOpt {
+    ARM_ISB_RESERVED_0 = 0,
+    ARM_ISB_RESERVED_1 = 1,
+    ARM_ISB_RESERVED_2 = 2,
+    ARM_ISB_RESERVED_3 = 3,
+    ARM_ISB_RESERVED_4 = 4,
+    ARM_ISB_RESERVED_5 = 5,
+    ARM_ISB_RESERVED_6 = 6,
+    ARM_ISB_RESERVED_7 = 7,
+    ARM_ISB_RESERVED_8 = 8,
+    ARM_ISB_RESERVED_9 = 9,
+    ARM_ISB_RESERVED_10 = 10,
+    ARM_ISB_RESERVED_11 = 11,
+    ARM_ISB_RESERVED_12 = 12,
+    ARM_ISB_RESERVED_13 = 13,
+    ARM_ISB_RESERVED_14 = 14,
+    ARM_ISB_SY = 15
+};
+
+inline static char *ARM_ISB_InstSyncBOptToString(unsigned val)
+{
+	switch (val) {
+		default: // never reach
+		case ARM_ISB_RESERVED_0:  return "#0x0";
+		case ARM_ISB_RESERVED_1:  return "#0x1";
+		case ARM_ISB_RESERVED_2:  return "#0x2";
+		case ARM_ISB_RESERVED_3:  return "#0x3";
+		case ARM_ISB_RESERVED_4:  return "#0x4";
+		case ARM_ISB_RESERVED_5:  return "#0x5";
+		case ARM_ISB_RESERVED_6:  return "#0x6";
+		case ARM_ISB_RESERVED_7:  return "#0x7";
+		case ARM_ISB_RESERVED_8:  return "#0x8";
+		case ARM_ISB_RESERVED_9:  return "#0x9";
+		case ARM_ISB_RESERVED_10: return "#0xa";
+		case ARM_ISB_RESERVED_11: return "#0xb";
+		case ARM_ISB_RESERVED_12: return "#0xc";
+		case ARM_ISB_RESERVED_13: return "#0xd";
+		case ARM_ISB_RESERVED_14: return "#0xe";
+		case ARM_ISB_SY:          return "sy";
+	}
+}
+
+/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
+///
+static inline bool isARMLowRegister(unsigned Reg)
+{
+	//using namespace ARM;
+	switch (Reg) {
+		case ARM_R0:  case ARM_R1:  case ARM_R2:  case ARM_R3:
+		case ARM_R4:  case ARM_R5:  case ARM_R6:  case ARM_R7:
+			return true;
+		default:
+			return false;
+	}
+}
+
+/// ARMII - This namespace holds all of the target specific flags that
+/// instruction info tracks.
+///
+/// ARM Index Modes
+enum ARMII_IndexMode {
+	ARMII_IndexModeNone  = 0,
+	ARMII_IndexModePre   = 1,
+	ARMII_IndexModePost  = 2,
+	ARMII_IndexModeUpd   = 3
+};
+
+/// ARM Addressing Modes
+typedef enum ARMII_AddrMode {
+	ARMII_AddrModeNone    = 0,
+	ARMII_AddrMode1       = 1,
+	ARMII_AddrMode2       = 2,
+	ARMII_AddrMode3       = 3,
+	ARMII_AddrMode4       = 4,
+	ARMII_AddrMode5       = 5,
+	ARMII_AddrMode6       = 6,
+	ARMII_AddrModeT1_1    = 7,
+	ARMII_AddrModeT1_2    = 8,
+	ARMII_AddrModeT1_4    = 9,
+	ARMII_AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
+	ARMII_AddrModeT2_i12  = 11,
+	ARMII_AddrModeT2_i8   = 12,
+	ARMII_AddrModeT2_so   = 13,
+	ARMII_AddrModeT2_pc   = 14, // +/- i12 for pc relative data
+	ARMII_AddrModeT2_i8s4 = 15, // i8 * 4
+	ARMII_AddrMode_i12    = 16
+} ARMII_AddrMode;
+
+inline static char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
+{
+	switch (addrmode) {
+		case ARMII_AddrModeNone:    return "AddrModeNone";
+		case ARMII_AddrMode1:       return "AddrMode1";
+		case ARMII_AddrMode2:       return "AddrMode2";
+		case ARMII_AddrMode3:       return "AddrMode3";
+		case ARMII_AddrMode4:       return "AddrMode4";
+		case ARMII_AddrMode5:       return "AddrMode5";
+		case ARMII_AddrMode6:       return "AddrMode6";
+		case ARMII_AddrModeT1_1:    return "AddrModeT1_1";
+		case ARMII_AddrModeT1_2:    return "AddrModeT1_2";
+		case ARMII_AddrModeT1_4:    return "AddrModeT1_4";
+		case ARMII_AddrModeT1_s:    return "AddrModeT1_s";
+		case ARMII_AddrModeT2_i12:  return "AddrModeT2_i12";
+		case ARMII_AddrModeT2_i8:   return "AddrModeT2_i8";
+		case ARMII_AddrModeT2_so:   return "AddrModeT2_so";
+		case ARMII_AddrModeT2_pc:   return "AddrModeT2_pc";
+		case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4";
+		case ARMII_AddrMode_i12:    return "AddrMode_i12";
+	}
+}
+
+/// Target Operand Flag enum.
+enum ARMII_TOF {
+	//===------------------------------------------------------------------===//
+	// ARM Specific MachineOperand flags.
+
+	ARMII_MO_NO_FLAG,
+
+	/// MO_LO16 - On a symbol operand, this represents a relocation containing
+	/// lower 16 bit of the address. Used only via movw instruction.
+	ARMII_MO_LO16,
+
+	/// MO_HI16 - On a symbol operand, this represents a relocation containing
+	/// higher 16 bit of the address. Used only via movt instruction.
+	ARMII_MO_HI16,
+
+	/// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
+	/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
+	/// i.e. "FOO$non_lazy_ptr".
+	/// Used only via movw instruction.
+	ARMII_MO_LO16_NONLAZY,
+
+	/// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
+	/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
+	/// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
+	ARMII_MO_HI16_NONLAZY,
+
+	/// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
+	/// relocation containing lower 16 bit of the PC relative address of the
+	/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
+	/// Used only via movw instruction.
+	ARMII_MO_LO16_NONLAZY_PIC,
+
+	/// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
+	/// relocation containing lower 16 bit of the PC relative address of the
+	/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
+	/// Used only via movt instruction.
+	ARMII_MO_HI16_NONLAZY_PIC,
+
+	/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
+	/// call operand.
+	ARMII_MO_PLT
+};
+
+enum {
+	//===------------------------------------------------------------------===//
+	// Instruction Flags.
+
+	//===------------------------------------------------------------------===//
+	// This four-bit field describes the addressing mode used.
+	ARMII_AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
+
+	// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
+	// and store ops only.  Generic "updating" flag is used for ld/st multiple.
+	// The index mode enums are declared in ARMBaseInfo.h
+	ARMII_IndexModeShift = 5,
+	ARMII_IndexModeMask  = 3 << ARMII_IndexModeShift,
+
+	//===------------------------------------------------------------------===//
+	// Instruction encoding formats.
+	//
+	ARMII_FormShift     = 7,
+	ARMII_FormMask      = 0x3f << ARMII_FormShift,
+
+	// Pseudo instructions
+	ARMII_Pseudo        = 0  << ARMII_FormShift,
+
+	// Multiply instructions
+	ARMII_MulFrm        = 1  << ARMII_FormShift,
+
+	// Branch instructions
+	ARMII_BrFrm         = 2  << ARMII_FormShift,
+	ARMII_BrMiscFrm     = 3  << ARMII_FormShift,
+
+	// Data Processing instructions
+	ARMII_DPFrm         = 4  << ARMII_FormShift,
+	ARMII_DPSoRegFrm    = 5  << ARMII_FormShift,
+
+	// Load and Store
+	ARMII_LdFrm         = 6  << ARMII_FormShift,
+	ARMII_StFrm         = 7  << ARMII_FormShift,
+	ARMII_LdMiscFrm     = 8  << ARMII_FormShift,
+	ARMII_StMiscFrm     = 9  << ARMII_FormShift,
+	ARMII_LdStMulFrm    = 10 << ARMII_FormShift,
+
+	ARMII_LdStExFrm     = 11 << ARMII_FormShift,
+
+	// Miscellaneous arithmetic instructions
+	ARMII_ArithMiscFrm  = 12 << ARMII_FormShift,
+	ARMII_SatFrm        = 13 << ARMII_FormShift,
+
+	// Extend instructions
+	ARMII_ExtFrm        = 14 << ARMII_FormShift,
+
+	// VFP formats
+	ARMII_VFPUnaryFrm   = 15 << ARMII_FormShift,
+	ARMII_VFPBinaryFrm  = 16 << ARMII_FormShift,
+	ARMII_VFPConv1Frm   = 17 << ARMII_FormShift,
+	ARMII_VFPConv2Frm   = 18 << ARMII_FormShift,
+	ARMII_VFPConv3Frm   = 19 << ARMII_FormShift,
+	ARMII_VFPConv4Frm   = 20 << ARMII_FormShift,
+	ARMII_VFPConv5Frm   = 21 << ARMII_FormShift,
+	ARMII_VFPLdStFrm    = 22 << ARMII_FormShift,
+	ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
+	ARMII_VFPMiscFrm    = 24 << ARMII_FormShift,
+
+	// Thumb format
+	ARMII_ThumbFrm      = 25 << ARMII_FormShift,
+
+	// Miscelleaneous format
+	ARMII_MiscFrm       = 26 << ARMII_FormShift,
+
+	// NEON formats
+	ARMII_NGetLnFrm     = 27 << ARMII_FormShift,
+	ARMII_NSetLnFrm     = 28 << ARMII_FormShift,
+	ARMII_NDupFrm       = 29 << ARMII_FormShift,
+	ARMII_NLdStFrm      = 30 << ARMII_FormShift,
+	ARMII_N1RegModImmFrm= 31 << ARMII_FormShift,
+	ARMII_N2RegFrm      = 32 << ARMII_FormShift,
+	ARMII_NVCVTFrm      = 33 << ARMII_FormShift,
+	ARMII_NVDupLnFrm    = 34 << ARMII_FormShift,
+	ARMII_N2RegVShLFrm  = 35 << ARMII_FormShift,
+	ARMII_N2RegVShRFrm  = 36 << ARMII_FormShift,
+	ARMII_N3RegFrm      = 37 << ARMII_FormShift,
+	ARMII_N3RegVShFrm   = 38 << ARMII_FormShift,
+	ARMII_NVExtFrm      = 39 << ARMII_FormShift,
+	ARMII_NVMulSLFrm    = 40 << ARMII_FormShift,
+	ARMII_NVTBLFrm      = 41 << ARMII_FormShift,
+
+	//===------------------------------------------------------------------===//
+	// Misc flags.
+
+	// UnaryDP - Indicates this is a unary data processing instruction, i.e.
+	// it doesn't have a Rn operand.
+	ARMII_UnaryDP       = 1 << 13,
+
+	// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
+	// a 16-bit Thumb instruction if certain conditions are met.
+	ARMII_Xform16Bit    = 1 << 14,
+
+	// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
+	// instruction. Used by the parser to determine whether to require the 'S'
+	// suffix on the mnemonic (when not in an IT block) or preclude it (when
+	// in an IT block).
+	ARMII_ThumbArithFlagSetting = 1 << 18,
+
+	//===------------------------------------------------------------------===//
+	// Code domain.
+	ARMII_DomainShift   = 15,
+	ARMII_DomainMask    = 7 << ARMII_DomainShift,
+	ARMII_DomainGeneral = 0 << ARMII_DomainShift,
+	ARMII_DomainVFP     = 1 << ARMII_DomainShift,
+	ARMII_DomainNEON    = 2 << ARMII_DomainShift,
+	ARMII_DomainNEONA8  = 4 << ARMII_DomainShift,
+
+	//===------------------------------------------------------------------===//
+	// Field shifts - such shifts are used to set field while generating
+	// machine instructions.
+	//
+	// FIXME: This list will need adjusting/fixing as the MC code emitter
+	// takes shape and the ARMCodeEmitter.cpp bits go away.
+	ARMII_ShiftTypeShift = 4,
+
+	ARMII_M_BitShift     = 5,
+	ARMII_ShiftImmShift  = 5,
+	ARMII_ShiftShift     = 7,
+	ARMII_N_BitShift     = 7,
+	ARMII_ImmHiShift     = 8,
+	ARMII_SoRotImmShift  = 8,
+	ARMII_RegRsShift     = 8,
+	ARMII_ExtRotImmShift = 10,
+	ARMII_RegRdLoShift   = 12,
+	ARMII_RegRdShift     = 12,
+	ARMII_RegRdHiShift   = 16,
+	ARMII_RegRnShift     = 16,
+	ARMII_S_BitShift     = 20,
+	ARMII_W_BitShift     = 21,
+	ARMII_AM3_I_BitShift = 22,
+	ARMII_D_BitShift     = 22,
+	ARMII_U_BitShift     = 23,
+	ARMII_P_BitShift     = 24,
+	ARMII_I_BitShift     = 25,
+	ARMII_CondShift      = 28
+};
+
+#endif

src/3rd-party/capstone/capstone/arch/ARM/ARMDisassembler.h

@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_ARMDISASSEMBLER_H
+#define CS_ARMDISASSEMBLER_H
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+
+void ARM_init(MCRegisterInfo *MRI);
+
+bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+uint64_t ARM_getFeatureBits(unsigned int mode);
+
+#endif

src/3rd-party/capstone/capstone/arch/ARM/ARMGenSubtargetInfo.inc

@@ -0,0 +1,74 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Subtarget Enumeration Source Fragment                                       *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+#define ARM_FeatureAAPCS (1ULL << 0)
+#define ARM_FeatureAClass (1ULL << 1)
+#define ARM_FeatureAPCS (1ULL << 2)
+#define ARM_FeatureAvoidMOVsShOp (1ULL << 3)
+#define ARM_FeatureAvoidPartialCPSR (1ULL << 4)
+#define ARM_FeatureCRC (1ULL << 5)
+#define ARM_FeatureCrypto (1ULL << 6)
+#define ARM_FeatureD16 (1ULL << 7)
+#define ARM_FeatureDB (1ULL << 8)
+#define ARM_FeatureDSPThumb2 (1ULL << 9)
+#define ARM_FeatureFP16 (1ULL << 10)
+#define ARM_FeatureFPARMv8 (1ULL << 11)
+#define ARM_FeatureHWDiv (1ULL << 12)
+#define ARM_FeatureHWDivARM (1ULL << 13)
+#define ARM_FeatureHasRAS (1ULL << 14)
+#define ARM_FeatureHasSlowFPVMLx (1ULL << 15)
+#define ARM_FeatureMClass (1ULL << 16)
+#define ARM_FeatureMP (1ULL << 17)
+#define ARM_FeatureNEON (1ULL << 18)
+#define ARM_FeatureNEONForFP (1ULL << 19)
+#define ARM_FeatureNaClTrap (1ULL << 20)
+#define ARM_FeatureNoARM (1ULL << 21)
+#define ARM_FeaturePerfMon (1ULL << 22)
+#define ARM_FeaturePref32BitThumb (1ULL << 23)
+#define ARM_FeatureRClass (1ULL << 24)
+#define ARM_FeatureSlowFPBrcc (1ULL << 25)
+#define ARM_FeatureT2XtPk (1ULL << 26)
+#define ARM_FeatureThumb2 (1ULL << 27)
+#define ARM_FeatureTrustZone (1ULL << 28)
+#define ARM_FeatureVFP2 (1ULL << 29)
+#define ARM_FeatureVFP3 (1ULL << 30)
+#define ARM_FeatureVFP4 (1ULL << 31)
+#define ARM_FeatureVFPOnlySP (1ULL << 32)
+#define ARM_FeatureVMLxForwarding (1ULL << 33)
+#define ARM_FeatureVirtualization (1ULL << 34)
+#define ARM_FeatureZCZeroing (1ULL << 35)
+#define ARM_HasV4TOps (1ULL << 36)
+#define ARM_HasV5TEOps (1ULL << 37)
+#define ARM_HasV5TOps (1ULL << 38)
+#define ARM_HasV6MOps (1ULL << 39)
+#define ARM_HasV6Ops (1ULL << 40)
+#define ARM_HasV6T2Ops (1ULL << 41)
+#define ARM_HasV7Ops (1ULL << 42)
+#define ARM_HasV8Ops (1ULL << 43)
+#define ARM_ModeThumb (1ULL << 44)
+#define ARM_ProcA5 (1ULL << 45)
+#define ARM_ProcA7 (1ULL << 46)
+#define ARM_ProcA8 (1ULL << 47)
+#define ARM_ProcA9 (1ULL << 48)
+#define ARM_ProcA12 (1ULL << 49)
+#define ARM_ProcA15 (1ULL << 50)
+#define ARM_ProcA53 (1ULL << 51)
+#define ARM_ProcA57 (1ULL << 52)
+#define ARM_ProcKrait (1ULL << 53)
+#define ARM_ProcR5 (1ULL << 54)
+#define ARM_ProcSwift (1ULL << 55)
+
+#endif // GET_SUBTARGETINFO_ENUM
+

src/3rd-party/capstone/capstone/arch/ARM/ARMInstPrinter.h

@@ -0,0 +1,43 @@
+//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an ARM MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_ARMINSTPRINTER_H
+#define CS_ARMINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void ARM_printInst(MCInst *MI, SStream *O, void *Info);
+void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci);
+
+// setup handle->get_regname
+void ARM_getRegName(cs_struct *handle, int value);
+
+// specify vector data type for vector instructions
+void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd);
+
+void ARM_addVectorDataSize(MCInst *MI, int size);
+
+void ARM_addReg(MCInst *MI, int reg);
+
+// load usermode registers (LDM, STM)
+void ARM_addUserMode(MCInst *MI);
+
+// sysreg for MRS/MSR
+void ARM_addSysReg(MCInst *MI, arm_sysreg reg);
+
+#endif

src/3rd-party/capstone/capstone/arch/ARM/ARMMapping.h

@@ -0,0 +1,26 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_ARM_MAP_H
+#define CS_ARM_MAP_H
+
+#include "../../include/capstone.h"
+#include "../../utils.h"
+
+// return name of regiser in friendly string
+const char *ARM_reg_name(csh handle, unsigned int reg);
+const char *ARM_reg_name2(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction ID
+void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *ARM_insn_name(csh handle, unsigned int id);
+
+const char *ARM_group_name(csh handle, unsigned int id);
+
+// check if this insn is relative branch
+bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
+
+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
+
+#endif

src/3rd-party/capstone/capstone/arch/ARM/ARMModule.c

@@ -0,0 +1,78 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#ifdef CAPSTONE_HAS_ARM
+
+#include "../../cs_priv.h"
+#include "../../MCRegisterInfo.h"
+#include "ARMDisassembler.h"
+#include "ARMInstPrinter.h"
+#include "ARMMapping.h"
+
+static cs_err init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	// verify if requested mode is valid
+	if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_V8 |
+				CS_MODE_MCLASS | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN))
+		return CS_ERR_MODE;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	ARM_init(mri);
+	ARM_getRegName(ud, 0);	// use default get_regname
+
+	ud->printer = ARM_printInst;
+	ud->printer_info = mri;
+	ud->reg_name = ARM_reg_name;
+	ud->insn_id = ARM_get_insn_id;
+	ud->insn_name = ARM_insn_name;
+	ud->group_name = ARM_group_name;
+	ud->post_printer = ARM_post_printer;
+
+	if (ud->mode & CS_MODE_THUMB)
+		ud->disasm = Thumb_getInstruction;
+	else
+		ud->disasm = ARM_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	switch(type) {
+		case CS_OPT_MODE:
+			if (value & CS_MODE_THUMB)
+				handle->disasm = Thumb_getInstruction;
+			else
+				handle->disasm = ARM_getInstruction;
+
+			handle->mode = (cs_mode)value;
+			break;
+		case CS_OPT_SYNTAX:
+			ARM_getRegName(handle, (int)value);
+			handle->syntax = (int)value;
+			break;
+		default:
+			break;
+	}
+
+	return CS_ERR_OK;
+}
+
+static void destroy(cs_struct *handle)
+{
+}
+
+void ARM_enable(void)
+{
+	arch_init[CS_ARCH_ARM] = init;
+	arch_option[CS_ARCH_ARM] = option;
+	arch_destroy[CS_ARCH_ARM] = destroy;
+
+	// support this arch
+	all_arch |= (1 << CS_ARCH_ARM);
+}
+
+#endif

src/3rd-party/capstone/capstone/arch/Mips/MipsDisassembler.h

@@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_MIPSDISASSEMBLER_H
+#define CS_MIPSDISASSEMBLER_H
+
+#include "../../include/capstone.h"
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+
+void Mips_init(MCRegisterInfo *MRI);
+
+bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+bool Mips64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif

src/3rd-party/capstone/capstone/arch/Mips/MipsGenSubtargetInfo.inc

@@ -0,0 +1,52 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Subtarget Enumeration Source Fragment                                       *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+#define Mips_FeatureCnMips (1ULL << 0)
+#define Mips_FeatureDSP (1ULL << 1)
+#define Mips_FeatureDSPR2 (1ULL << 2)
+#define Mips_FeatureEABI (1ULL << 3)
+#define Mips_FeatureFP64Bit (1ULL << 4)
+#define Mips_FeatureFPXX (1ULL << 5)
+#define Mips_FeatureGP64Bit (1ULL << 6)
+#define Mips_FeatureMSA (1ULL << 7)
+#define Mips_FeatureMicroMips (1ULL << 8)
+#define Mips_FeatureMips1 (1ULL << 9)
+#define Mips_FeatureMips2 (1ULL << 10)
+#define Mips_FeatureMips3 (1ULL << 11)
+#define Mips_FeatureMips3_32 (1ULL << 12)
+#define Mips_FeatureMips3_32r2 (1ULL << 13)
+#define Mips_FeatureMips4 (1ULL << 14)
+#define Mips_FeatureMips4_32 (1ULL << 15)
+#define Mips_FeatureMips4_32r2 (1ULL << 16)
+#define Mips_FeatureMips5 (1ULL << 17)
+#define Mips_FeatureMips5_32r2 (1ULL << 18)
+#define Mips_FeatureMips16 (1ULL << 19)
+#define Mips_FeatureMips32 (1ULL << 20)
+#define Mips_FeatureMips32r2 (1ULL << 21)
+#define Mips_FeatureMips32r6 (1ULL << 22)
+#define Mips_FeatureMips64 (1ULL << 23)
+#define Mips_FeatureMips64r2 (1ULL << 24)
+#define Mips_FeatureMips64r6 (1ULL << 25)
+#define Mips_FeatureN32 (1ULL << 26)
+#define Mips_FeatureN64 (1ULL << 27)
+#define Mips_FeatureNaN2008 (1ULL << 28)
+#define Mips_FeatureNoABICalls (1ULL << 29)
+#define Mips_FeatureNoOddSPReg (1ULL << 30)
+#define Mips_FeatureO32 (1ULL << 31)
+#define Mips_FeatureSingleFloat (1ULL << 32)
+#define Mips_FeatureVFPU (1ULL << 33)
+
+#endif // GET_SUBTARGETINFO_ENUM
+

src/3rd-party/capstone/capstone/arch/Mips/MipsInstPrinter.c

@@ -0,0 +1,424 @@
+//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an Mips MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_MIPS
+
+#include "../../myinttypes.h"
+#include <stdlib.h>
+#include <stdio.h>	// debug
+#include <string.h>
+
+#include "MipsInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "MipsMapping.h"
+
+#include "MipsInstPrinter.h"
+
+static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
+static char *printAliasInstr(MCInst *MI, SStream *O, void *info);
+static char *printAlias(MCInst *MI, SStream *OS);
+
+// These enumeration declarations were originally in MipsInstrInfo.h but
+// had to be moved here to avoid circular dependencies between
+// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
+
+// Mips Condition Codes
+typedef enum Mips_CondCode {
+	// To be used with float branch True
+	Mips_FCOND_F,
+	Mips_FCOND_UN,
+	Mips_FCOND_OEQ,
+	Mips_FCOND_UEQ,
+	Mips_FCOND_OLT,
+	Mips_FCOND_ULT,
+	Mips_FCOND_OLE,
+	Mips_FCOND_ULE,
+	Mips_FCOND_SF,
+	Mips_FCOND_NGLE,
+	Mips_FCOND_SEQ,
+	Mips_FCOND_NGL,
+	Mips_FCOND_LT,
+	Mips_FCOND_NGE,
+	Mips_FCOND_LE,
+	Mips_FCOND_NGT,
+
+	// To be used with float branch False
+	// This conditions have the same mnemonic as the
+	// above ones, but are used with a branch False;
+	Mips_FCOND_T,
+	Mips_FCOND_OR,
+	Mips_FCOND_UNE,
+	Mips_FCOND_ONE,
+	Mips_FCOND_UGE,
+	Mips_FCOND_OGE,
+	Mips_FCOND_UGT,
+	Mips_FCOND_OGT,
+	Mips_FCOND_ST,
+	Mips_FCOND_GLE,
+	Mips_FCOND_SNE,
+	Mips_FCOND_GL,
+	Mips_FCOND_NLT,
+	Mips_FCOND_GE,
+	Mips_FCOND_NLE,
+	Mips_FCOND_GT
+} Mips_CondCode;
+
+#define GET_INSTRINFO_ENUM
+#include "MipsGenInstrInfo.inc"
+
+static char *getRegisterName(unsigned RegNo);
+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
+
+static void set_mem_access(MCInst *MI, bool status)
+{
+	MI->csh->doing_mem = status;
+
+	if (MI->csh->detail != CS_OPT_ON)
+		return;
+
+	if (status) {
+		MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
+		MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
+		MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
+	} else {
+		// done, create the next operand slot
+		MI->flat_insn->detail->mips.op_count++;
+	}
+}
+
+static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
+{
+	return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) &&
+			MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
+}
+
+static char* MipsFCCToString(Mips_CondCode CC)
+{
+	switch (CC) {
+		default: return 0;	// never reach
+		case Mips_FCOND_F:
+		case Mips_FCOND_T:   return "f";
+		case Mips_FCOND_UN:
+		case Mips_FCOND_OR:  return "un";
+		case Mips_FCOND_OEQ:
+		case Mips_FCOND_UNE: return "eq";
+		case Mips_FCOND_UEQ:
+		case Mips_FCOND_ONE: return "ueq";
+		case Mips_FCOND_OLT:
+		case Mips_FCOND_UGE: return "olt";
+		case Mips_FCOND_ULT:
+		case Mips_FCOND_OGE: return "ult";
+		case Mips_FCOND_OLE:
+		case Mips_FCOND_UGT: return "ole";
+		case Mips_FCOND_ULE:
+		case Mips_FCOND_OGT: return "ule";
+		case Mips_FCOND_SF:
+		case Mips_FCOND_ST:  return "sf";
+		case Mips_FCOND_NGLE:
+		case Mips_FCOND_GLE: return "ngle";
+		case Mips_FCOND_SEQ:
+		case Mips_FCOND_SNE: return "seq";
+		case Mips_FCOND_NGL:
+		case Mips_FCOND_GL:  return "ngl";
+		case Mips_FCOND_LT:
+		case Mips_FCOND_NLT: return "lt";
+		case Mips_FCOND_NGE:
+		case Mips_FCOND_GE:  return "nge";
+		case Mips_FCOND_LE:
+		case Mips_FCOND_NLE: return "le";
+		case Mips_FCOND_NGT:
+		case Mips_FCOND_GT:  return "ngt";
+	}
+}
+
+static void printRegName(SStream *OS, unsigned RegNo)
+{
+	SStream_concat(OS, "$%s", getRegisterName(RegNo));
+}
+
+void Mips_printInst(MCInst *MI, SStream *O, void *info)
+{
+	char *mnem;
+
+	switch (MCInst_getOpcode(MI)) {
+		default: break;
+		case Mips_Save16:
+		case Mips_SaveX16:
+		case Mips_Restore16:
+		case Mips_RestoreX16:
+			return;
+	}
+
+	// Try to print any aliases first.
+	mnem = printAliasInstr(MI, O, info);
+	if (!mnem) {
+		mnem = printAlias(MI, O);
+		if (!mnem) {
+			printInstruction(MI, O, NULL);
+		}
+	}
+
+	if (mnem) {
+		// fixup instruction id due to the change in alias instruction
+		MCInst_setOpcodePub(MI, Mips_map_insn(mnem));
+		cs_mem_free(mnem);
+	}
+}
+
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op;
+
+	if (OpNo >= MI->size)
+		return;
+
+	Op = MCInst_getOperand(MI, OpNo);
+	if (MCOperand_isReg(Op)) {
+		unsigned int reg = MCOperand_getReg(Op);
+		printRegName(O, reg);
+		reg = Mips_map_register(reg);
+		if (MI->csh->detail) {
+			if (MI->csh->doing_mem) {
+				MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
+			} else {
+				MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
+				MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
+				MI->flat_insn->detail->mips.op_count++;
+			}
+		}
+	} else if (MCOperand_isImm(Op)) {
+		int64_t imm = MCOperand_getImm(Op);
+		if (MI->csh->doing_mem) {
+			if (imm) {	// only print Imm offset if it is not 0
+				if (imm >= 0) {
+					if (imm > HEX_THRESHOLD)
+						SStream_concat(O, "0x%"PRIx64, imm);
+					else
+						SStream_concat(O, "%"PRIu64, imm);
+				} else {
+					if (imm < -HEX_THRESHOLD)
+						SStream_concat(O, "-0x%"PRIx64, -imm);
+					else
+						SStream_concat(O, "-%"PRIu64, -imm);
+				}
+			}
+			if (MI->csh->detail)
+				MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
+		} else {
+			if (imm >= 0) {
+				if (imm > HEX_THRESHOLD)
+					SStream_concat(O, "0x%"PRIx64, imm);
+				else
+					SStream_concat(O, "%"PRIu64, imm);
+			} else {
+				if (imm < -HEX_THRESHOLD)
+					SStream_concat(O, "-0x%"PRIx64, -imm);
+				else
+					SStream_concat(O, "-%"PRIu64, -imm);
+			}
+
+			if (MI->csh->detail) {
+				MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+				MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
+				MI->flat_insn->detail->mips.op_count++;
+			}
+		}
+	}
+}
+
+static void printUnsignedImm(MCInst *MI, int opNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, opNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t imm = MCOperand_getImm(MO);
+		if (imm >= 0) {
+			if (imm > HEX_THRESHOLD)
+				SStream_concat(O, "0x%x", (unsigned short int)imm);
+			else
+				SStream_concat(O, "%u", (unsigned short int)imm);
+		} else {
+			if (imm < -HEX_THRESHOLD)
+				SStream_concat(O, "-0x%x", (short int)-imm);
+			else
+				SStream_concat(O, "-%u", (short int)-imm);
+		}
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+			MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
+			MI->flat_insn->detail->mips.op_count++;
+		}
+	} else
+		printOperand(MI, opNum, O);
+}
+
+static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, opNum);
+	if (MCOperand_isImm(MO)) {
+		uint8_t imm = (uint8_t)MCOperand_getImm(MO);
+		if (imm > HEX_THRESHOLD)
+			SStream_concat(O, "0x%x", imm);
+		else
+			SStream_concat(O, "%u", imm);
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+			MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
+			MI->flat_insn->detail->mips.op_count++;
+		}
+	} else
+		printOperand(MI, opNum, O);
+}
+
+static void printMemOperand(MCInst *MI, int opNum, SStream *O)
+{
+	// Load/Store memory operands -- imm($reg)
+	// If PIC target the target is loaded as the
+	// pattern lw $25,%call16($28)
+	set_mem_access(MI, true);
+	printOperand(MI, opNum + 1, O);
+	SStream_concat0(O, "(");
+	printOperand(MI, opNum, O);
+	SStream_concat0(O, ")");
+	set_mem_access(MI, false);
+}
+
+// TODO???
+static void printMemOperandEA(MCInst *MI, int opNum, SStream *O)
+{
+	// when using stack locations for not load/store instructions
+	// print the same way as all normal 3 operand instructions.
+	printOperand(MI, opNum, O);
+	SStream_concat0(O, ", ");
+	printOperand(MI, opNum + 1, O);
+	return;
+}
+
+static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, opNum);
+	SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
+}
+
+static char *printAlias1(char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
+{
+	SStream_concat(OS, "%s\t", Str);
+	printOperand(MI, OpNo, OS);
+	return cs_strdup(Str);
+}
+
+static char *printAlias2(char *Str, MCInst *MI,
+		unsigned OpNo0, unsigned OpNo1, SStream *OS)
+{
+	char *tmp;
+
+	tmp = printAlias1(Str, MI, OpNo0, OS);
+	SStream_concat0(OS, ", ");
+	printOperand(MI, OpNo1, OS);
+
+	return tmp;
+}
+
+#define GET_REGINFO_ENUM
+#include "MipsGenRegisterInfo.inc"
+
+static char *printAlias(MCInst *MI, SStream *OS)
+{
+	switch (MCInst_getOpcode(MI)) {
+		case Mips_BEQ:
+			// beq $zero, $zero, $L2 => b $L2
+			// beq $r0, $zero, $L2 => beqz $r0, $L2
+			if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
+				return printAlias1("b", MI, 2, OS);
+			if (isReg(MI, 1, Mips_ZERO))
+				return printAlias2("beqz", MI, 0, 2, OS);
+			return NULL;
+		case Mips_BEQL:
+			// beql $r0, $zero, $L2 => beqzl $r0, $L2
+			if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
+				return printAlias2("beqzl", MI, 0, 2, OS);
+			return NULL;
+		case Mips_BEQ64:
+			// beq $r0, $zero, $L2 => beqz $r0, $L2
+			if (isReg(MI, 1, Mips_ZERO_64))
+				return printAlias2("beqz", MI, 0, 2, OS);
+			return NULL;
+		case Mips_BNE:
+			// bne $r0, $zero, $L2 => bnez $r0, $L2
+			if (isReg(MI, 1, Mips_ZERO))
+				return printAlias2("bnez", MI, 0, 2, OS);
+			return NULL;
+		case Mips_BNEL:
+			// bnel $r0, $zero, $L2 => bnezl $r0, $L2
+			if (isReg(MI, 1, Mips_ZERO))
+				return printAlias2("bnezl", MI, 0, 2, OS);
+			return NULL;
+		case Mips_BNE64:
+			// bne $r0, $zero, $L2 => bnez $r0, $L2
+			if (isReg(MI, 1, Mips_ZERO_64))
+				return printAlias2("bnez", MI, 0, 2, OS);
+			return NULL;
+		case Mips_BGEZAL:
+			// bgezal $zero, $L1 => bal $L1
+			if (isReg(MI, 0, Mips_ZERO))
+				return printAlias1("bal", MI, 1, OS);
+			return NULL;
+		case Mips_BC1T:
+			// bc1t $fcc0, $L1 => bc1t $L1
+			if (isReg(MI, 0, Mips_FCC0))
+				return printAlias1("bc1t", MI, 1, OS);
+			return NULL;
+		case Mips_BC1F:
+			// bc1f $fcc0, $L1 => bc1f $L1
+			if (isReg(MI, 0, Mips_FCC0))
+				return printAlias1("bc1f", MI, 1, OS);
+			return NULL;
+		case Mips_JALR:
+			// jalr $ra, $r1 => jalr $r1
+			if (isReg(MI, 0, Mips_RA))
+				return printAlias1("jalr", MI, 1, OS);
+			return NULL;
+		case Mips_JALR64:
+			// jalr $ra, $r1 => jalr $r1
+			if (isReg(MI, 0, Mips_RA_64))
+				return printAlias1("jalr", MI, 1, OS);
+			return NULL;
+		case Mips_NOR:
+		case Mips_NOR_MM:
+			// nor $r0, $r1, $zero => not $r0, $r1
+			if (isReg(MI, 2, Mips_ZERO))
+				return printAlias2("not", MI, 0, 1, OS);
+			return NULL;
+		case Mips_NOR64:
+			// nor $r0, $r1, $zero => not $r0, $r1
+			if (isReg(MI, 2, Mips_ZERO_64))
+				return printAlias2("not", MI, 0, 1, OS);
+			return NULL;
+		case Mips_OR:
+			// or $r0, $r1, $zero => move $r0, $r1
+			if (isReg(MI, 2, Mips_ZERO))
+				return printAlias2("move", MI, 0, 1, OS);
+			return NULL;
+		default: return NULL;
+	}
+}
+
+#define PRINT_ALIAS_INSTR
+#include "MipsGenAsmWriter.inc"
+
+#endif

src/3rd-party/capstone/capstone/arch/Mips/MipsInstPrinter.h

@@ -0,0 +1,25 @@
+//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints a Mips MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_MIPSINSTPRINTER_H
+#define CS_MIPSINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+void Mips_printInst(MCInst *MI, SStream *O, void *info);
+
+#endif

src/3rd-party/capstone/capstone/arch/Mips/MipsMapping.h

@@ -0,0 +1,25 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_MIPS_MAP_H
+#define CS_MIPS_MAP_H
+
+#include "../../include/capstone.h"
+
+// return name of regiser in friendly string
+const char *Mips_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *Mips_insn_name(csh handle, unsigned int id);
+
+const char *Mips_group_name(csh handle, unsigned int id);
+
+// map instruction name to instruction ID
+mips_reg Mips_map_insn(const char *name);
+
+// map internal raw register to 'public' register
+mips_reg Mips_map_register(unsigned int r);
+
+#endif

src/3rd-party/capstone/capstone/arch/Mips/MipsModule.c

@@ -0,0 +1,68 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#ifdef CAPSTONE_HAS_MIPS
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "MipsDisassembler.h"
+#include "MipsInstPrinter.h"
+#include "MipsMapping.h"
+
+static cs_err init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	// verify if requested mode is valid
+	if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
+				CS_MODE_MICRO | CS_MODE_MIPS32R6 |
+				CS_MODE_MIPSGP64 | CS_MODE_BIG_ENDIAN))
+		return CS_ERR_MODE;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	Mips_init(mri);
+	ud->printer = Mips_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->reg_name = Mips_reg_name;
+	ud->insn_id = Mips_get_insn_id;
+	ud->insn_name = Mips_insn_name;
+	ud->group_name = Mips_group_name;
+
+	if (ud->mode & CS_MODE_32 || ud->mode & CS_MODE_MIPS32R6)
+		ud->disasm = Mips_getInstruction;
+	else
+		ud->disasm = Mips64_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_MODE) {
+		if (value & CS_MODE_32)
+			handle->disasm = Mips_getInstruction;
+		else
+			handle->disasm = Mips64_getInstruction;
+
+		handle->mode = (cs_mode)value;
+	}
+	return CS_ERR_OK;
+}
+
+static void destroy(cs_struct *handle)
+{
+}
+
+void Mips_enable(void)
+{
+	arch_init[CS_ARCH_MIPS] = init;
+	arch_option[CS_ARCH_MIPS] = option;
+	arch_destroy[CS_ARCH_MIPS] = destroy;
+
+	// support this arch
+	all_arch |= (1 << CS_ARCH_MIPS);
+}
+
+#endif

src/3rd-party/capstone/capstone/arch/PowerPC/PPCDisassembler.c

@@ -0,0 +1,406 @@
+//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_POWERPC
+
+#include <stdio.h>	// DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+#define GET_REGINFO_ENUM
+#include "PPCGenRegisterInfo.inc"
+
+
+// FIXME: These can be generated by TableGen from the existing register
+// encoding values!
+
+static const unsigned CRRegs[] = {
+	PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3,
+	PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7
+};
+
+static const unsigned CRBITRegs[] = {
+	PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN,
+	PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN,
+	PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN,
+	PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN,
+	PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN,
+	PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN,
+	PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN,
+	PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN
+};
+
+static const unsigned FRegs[] = {
+	PPC_F0, PPC_F1, PPC_F2, PPC_F3,
+	PPC_F4, PPC_F5, PPC_F6, PPC_F7,
+	PPC_F8, PPC_F9, PPC_F10, PPC_F11,
+	PPC_F12, PPC_F13, PPC_F14, PPC_F15,
+	PPC_F16, PPC_F17, PPC_F18, PPC_F19,
+	PPC_F20, PPC_F21, PPC_F22, PPC_F23,
+	PPC_F24, PPC_F25, PPC_F26, PPC_F27,
+	PPC_F28, PPC_F29, PPC_F30, PPC_F31
+};
+
+static const unsigned VRegs[] = {
+	PPC_V0, PPC_V1, PPC_V2, PPC_V3,
+	PPC_V4, PPC_V5, PPC_V6, PPC_V7,
+	PPC_V8, PPC_V9, PPC_V10, PPC_V11,
+	PPC_V12, PPC_V13, PPC_V14, PPC_V15,
+	PPC_V16, PPC_V17, PPC_V18, PPC_V19,
+	PPC_V20, PPC_V21, PPC_V22, PPC_V23,
+	PPC_V24, PPC_V25, PPC_V26, PPC_V27,
+	PPC_V28, PPC_V29, PPC_V30, PPC_V31
+};
+
+static const unsigned VSRegs[] = {
+	PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3,
+	PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7,
+	PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11,
+	PPC_VSL12, PPC_VSL13, PPC_VSL14, PPC_VSL15,
+	PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19,
+	PPC_VSL20, PPC_VSL21, PPC_VSL22, PPC_VSL23,
+	PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27,
+	PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31,
+
+	PPC_VSH0, PPC_VSH1, PPC_VSH2, PPC_VSH3,
+	PPC_VSH4, PPC_VSH5, PPC_VSH6, PPC_VSH7,
+	PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11,
+	PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15,
+	PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19,
+	PPC_VSH20, PPC_VSH21, PPC_VSH22, PPC_VSH23,
+	PPC_VSH24, PPC_VSH25, PPC_VSH26, PPC_VSH27,
+	PPC_VSH28, PPC_VSH29, PPC_VSH30, PPC_VSH31
+};
+
+static const unsigned VSFRegs[] = {
+	PPC_F0, PPC_F1, PPC_F2, PPC_F3,
+	PPC_F4, PPC_F5, PPC_F6, PPC_F7,
+	PPC_F8, PPC_F9, PPC_F10, PPC_F11,
+	PPC_F12, PPC_F13, PPC_F14, PPC_F15,
+	PPC_F16, PPC_F17, PPC_F18, PPC_F19,
+	PPC_F20, PPC_F21, PPC_F22, PPC_F23,
+	PPC_F24, PPC_F25, PPC_F26, PPC_F27,
+	PPC_F28, PPC_F29, PPC_F30, PPC_F31,
+
+	PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3,
+	PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7,
+	PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11,
+	PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15,
+	PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
+	PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23,
+	PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27,
+	PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31
+};
+
+static const unsigned GPRegs[] = {
+	PPC_R0, PPC_R1, PPC_R2, PPC_R3,
+	PPC_R4, PPC_R5, PPC_R6, PPC_R7,
+	PPC_R8, PPC_R9, PPC_R10, PPC_R11,
+	PPC_R12, PPC_R13, PPC_R14, PPC_R15,
+	PPC_R16, PPC_R17, PPC_R18, PPC_R19,
+	PPC_R20, PPC_R21, PPC_R22, PPC_R23,
+	PPC_R24, PPC_R25, PPC_R26, PPC_R27,
+	PPC_R28, PPC_R29, PPC_R30, PPC_R31
+};
+
+static const unsigned GP0Regs[] = {
+	PPC_ZERO, PPC_R1, PPC_R2, PPC_R3,
+	PPC_R4, PPC_R5, PPC_R6, PPC_R7,
+	PPC_R8, PPC_R9, PPC_R10, PPC_R11,
+	PPC_R12, PPC_R13, PPC_R14, PPC_R15,
+	PPC_R16, PPC_R17, PPC_R18, PPC_R19,
+	PPC_R20, PPC_R21, PPC_R22, PPC_R23,
+	PPC_R24, PPC_R25, PPC_R26, PPC_R27,
+	PPC_R28, PPC_R29, PPC_R30, PPC_R31
+};
+
+static const unsigned G8Regs[] = {
+	PPC_X0, PPC_X1, PPC_X2, PPC_X3,
+	PPC_X4, PPC_X5, PPC_X6, PPC_X7,
+	PPC_X8, PPC_X9, PPC_X10, PPC_X11,
+	PPC_X12, PPC_X13, PPC_X14, PPC_X15,
+	PPC_X16, PPC_X17, PPC_X18, PPC_X19,
+	PPC_X20, PPC_X21, PPC_X22, PPC_X23,
+	PPC_X24, PPC_X25, PPC_X26, PPC_X27,
+	PPC_X28, PPC_X29, PPC_X30, PPC_X31
+};
+
+static uint64_t getFeatureBits(int feature)
+{
+	// enable all features
+	return (uint64_t)-1;
+}
+
+static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,
+		const unsigned *Regs)
+{
+	// assert(RegNo < N && "Invalid register number");
+	MCOperand_CreateReg0(Inst, Regs[RegNo]);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, CRRegs);
+}
+
+static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, CRBITRegs);
+}
+
+static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, FRegs);
+}
+
+static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, FRegs);
+}
+
+static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VRegs);
+}
+
+static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VSRegs);
+}
+
+static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VSFRegs);
+}
+
+static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, GPRegs);
+}
+
+static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, GP0Regs);
+}
+
+static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, G8Regs);
+}
+
+#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
+#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
+
+static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm,
+		int64_t Address, const void *Decoder, unsigned N)
+{
+	//assert(isUInt<N>(Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, Imm);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm,
+		int64_t Address, const void *Decoder, unsigned N)
+{
+	// assert(isUInt<N>(Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
+	return MCDisassembler_Success;
+}
+
+
+#define GET_INSTRINFO_ENUM
+#include "PPCGenInstrInfo.inc"
+
+static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
+		int64_t Address, const void *Decoder)
+{
+	// Decode the memri field (imm, reg), which has the low 16-bits as the
+	// displacement and the next 5 bits as the register #.
+
+	uint64_t Base = Imm >> 16;
+	uint64_t Disp = Imm & 0xFFFF;
+
+	// assert(Base < 32 && "Invalid base register");
+	if (Base >= 32)
+		return MCDisassembler_Fail;
+
+	switch (MCInst_getOpcode(Inst)) {
+		default: break;
+		case PPC_LBZU:
+		case PPC_LHAU:
+		case PPC_LHZU:
+		case PPC_LWZU:
+		case PPC_LFSU:
+		case PPC_LFDU:
+				 // Add the tied output operand.
+				 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
+				 break;
+		case PPC_STBU:
+		case PPC_STHU:
+		case PPC_STWU:
+		case PPC_STFSU:
+		case PPC_STFDU:
+				 MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
+				 break;
+	}
+
+	MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16));
+	MCOperand_CreateReg0(Inst, GP0Regs[Base]);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm,
+		int64_t Address, const void *Decoder)
+{
+	// Decode the memrix field (imm, reg), which has the low 14-bits as the
+	// displacement and the next 5 bits as the register #.
+
+	uint64_t Base = Imm >> 14;
+	uint64_t Disp = Imm & 0x3FFF;
+
+	// assert(Base < 32 && "Invalid base register");
+
+	if (MCInst_getOpcode(Inst) == PPC_LDU)
+		// Add the tied output operand.
+		MCOperand_CreateReg0(Inst, GP0Regs[Base]);
+	else if (MCInst_getOpcode(Inst) == PPC_STDU)
+		MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
+
+	MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16));
+	MCOperand_CreateReg0(Inst, GP0Regs[Base]);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm,
+		int64_t Address, const void *Decoder)
+{
+	// The cr bit encoding is 0x80 >> cr_reg_num.
+
+	unsigned Zeros = CountTrailingZeros_64(Imm);
+	// assert(Zeros < 8 && "Invalid CR bit value");
+	if (Zeros >=8)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]);
+	return MCDisassembler_Success;
+}
+
+#include "PPCGenDisassemblerTables.inc"
+
+static DecodeStatus getInstruction(MCInst *MI,
+		const uint8_t *code, size_t code_len,
+		uint16_t *Size,
+		uint64_t Address, MCRegisterInfo *MRI)
+{
+	uint32_t insn;
+	DecodeStatus result;
+	// Get the four bytes of the instruction.
+	if (code_len < 4) {
+		// not enough data
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	// The instruction is big-endian encoded.
+	if (MI->csh->mode & CS_MODE_BIG_ENDIAN)
+		insn = (code[0] << 24) | (code[1] << 16) |
+			(code[2] <<  8) | (code[3] <<  0);
+	else
+		insn = (code[3] << 24) | (code[2] << 16) |
+			(code[1] <<  8) | (code[0] <<  0);
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
+	}
+
+	result = decodeInstruction_4(DecoderTable32, MI, insn, Address, 4);
+	if (result != MCDisassembler_Fail) {
+		*Size = 4;
+		return result;
+	}
+
+	// report error
+	MCInst_clear(MI);
+	*Size = 0;
+	return MCDisassembler_Fail;
+}
+
+bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info)
+{
+	DecodeStatus status = getInstruction(instr,
+			code, code_len,
+			size,
+			address, (MCRegisterInfo *)info);
+
+	return status == MCDisassembler_Success;
+}
+
+#define GET_REGINFO_MC_DESC
+#include "PPCGenRegisterInfo.inc"
+void PPC_init(MCRegisterInfo *MRI)
+{
+	/*
+	InitMCRegisterInfo(PPCRegDesc, 279, RA, PC,
+			PPCMCRegisterClasses, 21,
+			PPCRegUnitRoots,
+			146,
+			PPCRegDiffLists,
+			PPCRegStrings,
+			PPCSubRegIdxLists,
+			8,
+			PPCSubRegIdxRanges,
+			PPCRegEncodingTable);
+	*/
+
+	MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 279,
+			0, 0,
+			PPCMCRegisterClasses, 21,
+			0, 0,
+			PPCRegDiffLists,
+			0,
+			PPCSubRegIdxLists, 8,
+			0);
+}
+
+#endif

src/3rd-party/capstone/capstone/arch/PowerPC/PPCDisassembler.h

@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_PPCDISASSEMBLER_H
+#define CS_PPCDISASSEMBLER_H
+
+#include <stdint.h>
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void PPC_init(MCRegisterInfo *MRI);
+
+bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+

src/3rd-party/capstone/capstone/arch/PowerPC/PPCGenRegisterInfo.inc

@@ -0,0 +1,917 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Register Enum Values                                                 *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  PPC_NoRegister,
+  PPC_BP = 1,
+  PPC_CARRY = 2,
+  PPC_CC = 3,
+  PPC_CTR = 4,
+  PPC_FP = 5,
+  PPC_LR = 6,
+  PPC_RM = 7,
+  PPC_VRSAVE = 8,
+  PPC_ZERO = 9,
+  PPC_BP8 = 10,
+  PPC_CR0 = 11,
+  PPC_CR1 = 12,
+  PPC_CR2 = 13,
+  PPC_CR3 = 14,
+  PPC_CR4 = 15,
+  PPC_CR5 = 16,
+  PPC_CR6 = 17,
+  PPC_CR7 = 18,
+  PPC_CTR8 = 19,
+  PPC_F0 = 20,
+  PPC_F1 = 21,
+  PPC_F2 = 22,
+  PPC_F3 = 23,
+  PPC_F4 = 24,
+  PPC_F5 = 25,
+  PPC_F6 = 26,
+  PPC_F7 = 27,
+  PPC_F8 = 28,
+  PPC_F9 = 29,
+  PPC_F10 = 30,
+  PPC_F11 = 31,
+  PPC_F12 = 32,
+  PPC_F13 = 33,
+  PPC_F14 = 34,
+  PPC_F15 = 35,
+  PPC_F16 = 36,
+  PPC_F17 = 37,
+  PPC_F18 = 38,
+  PPC_F19 = 39,
+  PPC_F20 = 40,
+  PPC_F21 = 41,
+  PPC_F22 = 42,
+  PPC_F23 = 43,
+  PPC_F24 = 44,
+  PPC_F25 = 45,
+  PPC_F26 = 46,
+  PPC_F27 = 47,
+  PPC_F28 = 48,
+  PPC_F29 = 49,
+  PPC_F30 = 50,
+  PPC_F31 = 51,
+  PPC_FP8 = 52,
+  PPC_LR8 = 53,
+  PPC_R0 = 54,
+  PPC_R1 = 55,
+  PPC_R2 = 56,
+  PPC_R3 = 57,
+  PPC_R4 = 58,
+  PPC_R5 = 59,
+  PPC_R6 = 60,
+  PPC_R7 = 61,
+  PPC_R8 = 62,
+  PPC_R9 = 63,
+  PPC_R10 = 64,
+  PPC_R11 = 65,
+  PPC_R12 = 66,
+  PPC_R13 = 67,
+  PPC_R14 = 68,
+  PPC_R15 = 69,
+  PPC_R16 = 70,
+  PPC_R17 = 71,
+  PPC_R18 = 72,
+  PPC_R19 = 73,
+  PPC_R20 = 74,
+  PPC_R21 = 75,
+  PPC_R22 = 76,
+  PPC_R23 = 77,
+  PPC_R24 = 78,
+  PPC_R25 = 79,
+  PPC_R26 = 80,
+  PPC_R27 = 81,
+  PPC_R28 = 82,
+  PPC_R29 = 83,
+  PPC_R30 = 84,
+  PPC_R31 = 85,
+  PPC_V0 = 86,
+  PPC_V1 = 87,
+  PPC_V2 = 88,
+  PPC_V3 = 89,
+  PPC_V4 = 90,
+  PPC_V5 = 91,
+  PPC_V6 = 92,
+  PPC_V7 = 93,
+  PPC_V8 = 94,
+  PPC_V9 = 95,
+  PPC_V10 = 96,
+  PPC_V11 = 97,
+  PPC_V12 = 98,
+  PPC_V13 = 99,
+  PPC_V14 = 100,
+  PPC_V15 = 101,
+  PPC_V16 = 102,
+  PPC_V17 = 103,
+  PPC_V18 = 104,
+  PPC_V19 = 105,
+  PPC_V20 = 106,
+  PPC_V21 = 107,
+  PPC_V22 = 108,
+  PPC_V23 = 109,
+  PPC_V24 = 110,
+  PPC_V25 = 111,
+  PPC_V26 = 112,
+  PPC_V27 = 113,
+  PPC_V28 = 114,
+  PPC_V29 = 115,
+  PPC_V30 = 116,
+  PPC_V31 = 117,
+  PPC_VF0 = 118,
+  PPC_VF1 = 119,
+  PPC_VF2 = 120,
+  PPC_VF3 = 121,
+  PPC_VF4 = 122,
+  PPC_VF5 = 123,
+  PPC_VF6 = 124,
+  PPC_VF7 = 125,
+  PPC_VF8 = 126,
+  PPC_VF9 = 127,
+  PPC_VF10 = 128,
+  PPC_VF11 = 129,
+  PPC_VF12 = 130,
+  PPC_VF13 = 131,
+  PPC_VF14 = 132,
+  PPC_VF15 = 133,
+  PPC_VF16 = 134,
+  PPC_VF17 = 135,
+  PPC_VF18 = 136,
+  PPC_VF19 = 137,
+  PPC_VF20 = 138,
+  PPC_VF21 = 139,
+  PPC_VF22 = 140,
+  PPC_VF23 = 141,
+  PPC_VF24 = 142,
+  PPC_VF25 = 143,
+  PPC_VF26 = 144,
+  PPC_VF27 = 145,
+  PPC_VF28 = 146,
+  PPC_VF29 = 147,
+  PPC_VF30 = 148,
+  PPC_VF31 = 149,
+  PPC_VSH0 = 150,
+  PPC_VSH1 = 151,
+  PPC_VSH2 = 152,
+  PPC_VSH3 = 153,
+  PPC_VSH4 = 154,
+  PPC_VSH5 = 155,
+  PPC_VSH6 = 156,
+  PPC_VSH7 = 157,
+  PPC_VSH8 = 158,
+  PPC_VSH9 = 159,
+  PPC_VSH10 = 160,
+  PPC_VSH11 = 161,
+  PPC_VSH12 = 162,
+  PPC_VSH13 = 163,
+  PPC_VSH14 = 164,
+  PPC_VSH15 = 165,
+  PPC_VSH16 = 166,
+  PPC_VSH17 = 167,
+  PPC_VSH18 = 168,
+  PPC_VSH19 = 169,
+  PPC_VSH20 = 170,
+  PPC_VSH21 = 171,
+  PPC_VSH22 = 172,
+  PPC_VSH23 = 173,
+  PPC_VSH24 = 174,
+  PPC_VSH25 = 175,
+  PPC_VSH26 = 176,
+  PPC_VSH27 = 177,
+  PPC_VSH28 = 178,
+  PPC_VSH29 = 179,
+  PPC_VSH30 = 180,
+  PPC_VSH31 = 181,
+  PPC_VSL0 = 182,
+  PPC_VSL1 = 183,
+  PPC_VSL2 = 184,
+  PPC_VSL3 = 185,
+  PPC_VSL4 = 186,
+  PPC_VSL5 = 187,
+  PPC_VSL6 = 188,
+  PPC_VSL7 = 189,
+  PPC_VSL8 = 190,
+  PPC_VSL9 = 191,
+  PPC_VSL10 = 192,
+  PPC_VSL11 = 193,
+  PPC_VSL12 = 194,
+  PPC_VSL13 = 195,
+  PPC_VSL14 = 196,
+  PPC_VSL15 = 197,
+  PPC_VSL16 = 198,
+  PPC_VSL17 = 199,
+  PPC_VSL18 = 200,
+  PPC_VSL19 = 201,
+  PPC_VSL20 = 202,
+  PPC_VSL21 = 203,
+  PPC_VSL22 = 204,
+  PPC_VSL23 = 205,
+  PPC_VSL24 = 206,
+  PPC_VSL25 = 207,
+  PPC_VSL26 = 208,
+  PPC_VSL27 = 209,
+  PPC_VSL28 = 210,
+  PPC_VSL29 = 211,
+  PPC_VSL30 = 212,
+  PPC_VSL31 = 213,
+  PPC_X0 = 214,
+  PPC_X1 = 215,
+  PPC_X2 = 216,
+  PPC_X3 = 217,
+  PPC_X4 = 218,
+  PPC_X5 = 219,
+  PPC_X6 = 220,
+  PPC_X7 = 221,
+  PPC_X8 = 222,
+  PPC_X9 = 223,
+  PPC_X10 = 224,
+  PPC_X11 = 225,
+  PPC_X12 = 226,
+  PPC_X13 = 227,
+  PPC_X14 = 228,
+  PPC_X15 = 229,
+  PPC_X16 = 230,
+  PPC_X17 = 231,
+  PPC_X18 = 232,
+  PPC_X19 = 233,
+  PPC_X20 = 234,
+  PPC_X21 = 235,
+  PPC_X22 = 236,
+  PPC_X23 = 237,
+  PPC_X24 = 238,
+  PPC_X25 = 239,
+  PPC_X26 = 240,
+  PPC_X27 = 241,
+  PPC_X28 = 242,
+  PPC_X29 = 243,
+  PPC_X30 = 244,
+  PPC_X31 = 245,
+  PPC_ZERO8 = 246,
+  PPC_CR0EQ = 247,
+  PPC_CR1EQ = 248,
+  PPC_CR2EQ = 249,
+  PPC_CR3EQ = 250,
+  PPC_CR4EQ = 251,
+  PPC_CR5EQ = 252,
+  PPC_CR6EQ = 253,
+  PPC_CR7EQ = 254,
+  PPC_CR0GT = 255,
+  PPC_CR1GT = 256,
+  PPC_CR2GT = 257,
+  PPC_CR3GT = 258,
+  PPC_CR4GT = 259,
+  PPC_CR5GT = 260,
+  PPC_CR6GT = 261,
+  PPC_CR7GT = 262,
+  PPC_CR0LT = 263,
+  PPC_CR1LT = 264,
+  PPC_CR2LT = 265,
+  PPC_CR3LT = 266,
+  PPC_CR4LT = 267,
+  PPC_CR5LT = 268,
+  PPC_CR6LT = 269,
+  PPC_CR7LT = 270,
+  PPC_CR0UN = 271,
+  PPC_CR1UN = 272,
+  PPC_CR2UN = 273,
+  PPC_CR3UN = 274,
+  PPC_CR4UN = 275,
+  PPC_CR5UN = 276,
+  PPC_CR6UN = 277,
+  PPC_CR7UN = 278,
+  PPC_NUM_TARGET_REGS 	// 279
+};
+
+// Register classes
+enum {
+  PPC_GPRCRegClassID = 0,
+  PPC_GPRC_NOR0RegClassID = 1,
+  PPC_GPRC_and_GPRC_NOR0RegClassID = 2,
+  PPC_CRBITRCRegClassID = 3,
+  PPC_F4RCRegClassID = 4,
+  PPC_CRRCRegClassID = 5,
+  PPC_CARRYRCRegClassID = 6,
+  PPC_CCRCRegClassID = 7,
+  PPC_CTRRCRegClassID = 8,
+  PPC_VRSAVERCRegClassID = 9,
+  PPC_VSFRCRegClassID = 10,
+  PPC_G8RCRegClassID = 11,
+  PPC_G8RC_NOX0RegClassID = 12,
+  PPC_G8RC_and_G8RC_NOX0RegClassID = 13,
+  PPC_F8RCRegClassID = 14,
+  PPC_VFRCRegClassID = 15,
+  PPC_CTRRC8RegClassID = 16,
+  PPC_VSRCRegClassID = 17,
+  PPC_VRRCRegClassID = 18,
+  PPC_VSHRCRegClassID = 19,
+  PPC_VSLRCRegClassID = 20
+};
+
+// Subregister indices
+enum {
+  PPC_NoSubRegister,
+  PPC_sub_32,	// 1
+  PPC_sub_64,	// 2
+  PPC_sub_128,	// 3
+  PPC_sub_eq,	// 4
+  PPC_sub_gt,	// 5
+  PPC_sub_lt,	// 6
+  PPC_sub_un,	// 7
+  PPC_NUM_TARGET_SUBREGS
+};
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*MC Register Information                                                     *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static MCPhysReg PPCRegDiffLists[] = {
+  /* 0 */ 0, 0,
+  /* 2 */ 2, 1, 1, 1, 1, 1, 1, 1, 0,
+  /* 11 */ 65527, 14, 1, 1, 1, 0,
+  /* 17 */ 65527, 17, 1, 1, 1, 0,
+  /* 23 */ 65527, 20, 1, 1, 1, 0,
+  /* 29 */ 65527, 23, 1, 1, 1, 0,
+  /* 35 */ 65527, 26, 1, 1, 1, 0,
+  /* 41 */ 65527, 29, 1, 1, 1, 0,
+  /* 47 */ 65527, 32, 1, 1, 1, 0,
+  /* 53 */ 65527, 35, 1, 1, 1, 0,
+  /* 59 */ 6, 0,
+  /* 61 */ 9, 0,
+  /* 63 */ 11, 0,
+  /* 65 */ 252, 65528, 65528, 24, 0,
+  /* 70 */ 28, 0,
+  /* 72 */ 29, 0,
+  /* 74 */ 65472, 32, 0,
+  /* 77 */ 47, 0,
+  /* 79 */ 65504, 64, 0,
+  /* 82 */ 160, 0,
+  /* 84 */ 162, 0,
+  /* 86 */ 237, 0,
+  /* 88 */ 64471, 0,
+  /* 90 */ 64500, 0,
+  /* 92 */ 64533, 0,
+  /* 94 */ 64566, 0,
+  /* 96 */ 64813, 0,
+  /* 98 */ 65276, 0,
+  /* 100 */ 65284, 0,
+  /* 102 */ 65292, 0,
+  /* 104 */ 65299, 0,
+  /* 106 */ 65300, 0,
+  /* 108 */ 65374, 0,
+  /* 110 */ 65376, 0,
+  /* 112 */ 65403, 0,
+  /* 114 */ 65404, 0,
+  /* 116 */ 65489, 0,
+  /* 118 */ 65500, 0,
+  /* 120 */ 65527, 0,
+  /* 122 */ 65532, 0,
+  /* 124 */ 65535, 0,
+};
+
+static uint16_t PPCSubRegIdxLists[] = {
+  /* 0 */ 1, 0,
+  /* 2 */ 3, 2, 0,
+  /* 5 */ 6, 5, 4, 7, 0,
+};
+
+static MCRegisterDesc PPCRegDesc[] = { // Descriptors
+  { 4, 0, 0, 0, 0 },
+  { 962, 1, 61, 1, 1985 },
+  { 1119, 1, 1, 1, 1985 },
+  { 896, 1, 1, 1, 32 },
+  { 1019, 1, 1, 1, 945 },
+  { 965, 1, 77, 1, 945 },
+  { 1016, 1, 1, 1, 945 },
+  { 906, 1, 1, 1, 945 },
+  { 899, 1, 1, 1, 945 },
+  { 957, 1, 86, 1, 945 },
+  { 792, 120, 1, 0, 0 },
+  { 101, 65, 1, 5, 177 },
+  { 212, 65, 1, 5, 273 },
+  { 294, 65, 1, 5, 369 },
+  { 376, 65, 1, 5, 465 },
+  { 458, 65, 1, 5, 561 },
+  { 540, 65, 1, 5, 657 },
+  { 622, 65, 1, 5, 753 },
+  { 704, 65, 1, 5, 849 },
+  { 804, 1, 1, 1, 1153 },
+  { 88, 1, 84, 1, 1153 },
+  { 199, 1, 84, 1, 1153 },
+  { 281, 1, 84, 1, 1153 },
+  { 363, 1, 84, 1, 1153 },
+  { 445, 1, 84, 1, 1153 },
+  { 527, 1, 84, 1, 1153 },
+  { 609, 1, 84, 1, 1153 },
+  { 691, 1, 84, 1, 1153 },
+  { 773, 1, 84, 1, 1153 },
+  { 874, 1, 84, 1, 1153 },
+  { 1, 1, 84, 1, 1153 },
+  { 112, 1, 84, 1, 1153 },
+  { 223, 1, 84, 1, 1153 },
+  { 305, 1, 84, 1, 1153 },
+  { 387, 1, 84, 1, 1153 },
+  { 469, 1, 84, 1, 1153 },
+  { 551, 1, 84, 1, 1153 },
+  { 633, 1, 84, 1, 1153 },
+  { 715, 1, 84, 1, 1153 },
+  { 816, 1, 84, 1, 1153 },
+  { 30, 1, 84, 1, 1153 },
+  { 141, 1, 84, 1, 1153 },
+  { 252, 1, 84, 1, 1153 },
+  { 334, 1, 84, 1, 1153 },
+  { 416, 1, 84, 1, 1153 },
+  { 498, 1, 84, 1, 1153 },
+  { 580, 1, 84, 1, 1153 },
+  { 662, 1, 84, 1, 1153 },
+  { 744, 1, 84, 1, 1153 },
+  { 845, 1, 84, 1, 1153 },
+  { 59, 1, 84, 1, 1153 },
+  { 170, 1, 84, 1, 1153 },
+  { 796, 116, 1, 0, 1008 },
+  { 800, 1, 1, 1, 1121 },
+  { 102, 1, 82, 1, 1121 },
+  { 213, 1, 82, 1, 1121 },
+  { 295, 1, 82, 1, 1121 },
+  { 377, 1, 82, 1, 1121 },
+  { 459, 1, 82, 1, 1121 },
+  { 541, 1, 82, 1, 1121 },
+  { 623, 1, 82, 1, 1121 },
+  { 705, 1, 82, 1, 1121 },
+  { 801, 1, 82, 1, 1121 },
+  { 887, 1, 82, 1, 1121 },
+  { 17, 1, 82, 1, 1121 },
+  { 128, 1, 82, 1, 1121 },
+  { 239, 1, 82, 1, 1121 },
+  { 321, 1, 82, 1, 1121 },
+  { 403, 1, 82, 1, 1121 },
+  { 485, 1, 82, 1, 1121 },
+  { 567, 1, 82, 1, 1121 },
+  { 649, 1, 82, 1, 1121 },
+  { 731, 1, 82, 1, 1121 },
+  { 832, 1, 82, 1, 1121 },
+  { 46, 1, 82, 1, 1121 },
+  { 157, 1, 82, 1, 1121 },
+  { 268, 1, 82, 1, 1121 },
+  { 350, 1, 82, 1, 1121 },
+  { 432, 1, 82, 1, 1121 },
+  { 514, 1, 82, 1, 1121 },
+  { 596, 1, 82, 1, 1121 },
+  { 678, 1, 82, 1, 1121 },
+  { 760, 1, 82, 1, 1121 },
+  { 861, 1, 82, 1, 1121 },
+  { 75, 1, 82, 1, 1121 },
+  { 186, 1, 82, 1, 1121 },
+  { 105, 75, 80, 3, 1121 },
+  { 216, 75, 80, 3, 1121 },
+  { 298, 75, 80, 3, 1121 },
+  { 380, 75, 80, 3, 1121 },
+  { 462, 75, 80, 3, 1121 },
+  { 544, 75, 80, 3, 1121 },
+  { 626, 75, 80, 3, 1121 },
+  { 708, 75, 80, 3, 1121 },
+  { 809, 75, 80, 3, 1121 },
+  { 890, 75, 80, 3, 1121 },
+  { 21, 75, 80, 3, 1121 },
+  { 132, 75, 80, 3, 1121 },
+  { 243, 75, 80, 3, 1121 },
+  { 325, 75, 80, 3, 1121 },
+  { 407, 75, 80, 3, 1121 },
+  { 489, 75, 80, 3, 1121 },
+  { 571, 75, 80, 3, 1121 },
+  { 653, 75, 80, 3, 1121 },
+  { 735, 75, 80, 3, 1121 },
+  { 836, 75, 80, 3, 1121 },
+  { 50, 75, 80, 3, 1121 },
+  { 161, 75, 80, 3, 1121 },
+  { 272, 75, 80, 3, 1121 },
+  { 354, 75, 80, 3, 1121 },
+  { 436, 75, 80, 3, 1121 },
+  { 518, 75, 80, 3, 1121 },
+  { 600, 75, 80, 3, 1121 },
+  { 682, 75, 80, 3, 1121 },
+  { 764, 75, 80, 3, 1121 },
+  { 865, 75, 80, 3, 1121 },
+  { 79, 75, 80, 3, 1121 },
+  { 190, 75, 80, 3, 1121 },
+  { 87, 1, 79, 1, 1953 },
+  { 198, 1, 79, 1, 1953 },
+  { 280, 1, 79, 1, 1953 },
+  { 362, 1, 79, 1, 1953 },
+  { 444, 1, 79, 1, 1953 },
+  { 526, 1, 79, 1, 1953 },
+  { 608, 1, 79, 1, 1953 },
+  { 690, 1, 79, 1, 1953 },
+  { 772, 1, 79, 1, 1953 },
+  { 873, 1, 79, 1, 1953 },
+  { 0, 1, 79, 1, 1953 },
+  { 111, 1, 79, 1, 1953 },
+  { 222, 1, 79, 1, 1953 },
+  { 304, 1, 79, 1, 1953 },
+  { 386, 1, 79, 1, 1953 },
+  { 468, 1, 79, 1, 1953 },
+  { 550, 1, 79, 1, 1953 },
+  { 632, 1, 79, 1, 1953 },
+  { 714, 1, 79, 1, 1953 },
+  { 815, 1, 79, 1, 1953 },
+  { 29, 1, 79, 1, 1953 },
+  { 140, 1, 79, 1, 1953 },
+  { 251, 1, 79, 1, 1953 },
+  { 333, 1, 79, 1, 1953 },
+  { 415, 1, 79, 1, 1953 },
+  { 497, 1, 79, 1, 1953 },
+  { 579, 1, 79, 1, 1953 },
+  { 661, 1, 79, 1, 1953 },
+  { 743, 1, 79, 1, 1953 },
+  { 844, 1, 79, 1, 1953 },
+  { 58, 1, 79, 1, 1953 },
+  { 169, 1, 79, 1, 1953 },
+  { 91, 74, 1, 2, 1889 },
+  { 202, 74, 1, 2, 1889 },
+  { 284, 74, 1, 2, 1889 },
+  { 366, 74, 1, 2, 1889 },
+  { 448, 74, 1, 2, 1889 },
+  { 530, 74, 1, 2, 1889 },
+  { 612, 74, 1, 2, 1889 },
+  { 694, 74, 1, 2, 1889 },
+  { 776, 74, 1, 2, 1889 },
+  { 877, 74, 1, 2, 1889 },
+  { 5, 74, 1, 2, 1889 },
+  { 116, 74, 1, 2, 1889 },
+  { 227, 74, 1, 2, 1889 },
+  { 309, 74, 1, 2, 1889 },
+  { 391, 74, 1, 2, 1889 },
+  { 473, 74, 1, 2, 1889 },
+  { 555, 74, 1, 2, 1889 },
+  { 637, 74, 1, 2, 1889 },
+  { 719, 74, 1, 2, 1889 },
+  { 820, 74, 1, 2, 1889 },
+  { 34, 74, 1, 2, 1889 },
+  { 145, 74, 1, 2, 1889 },
+  { 256, 74, 1, 2, 1889 },
+  { 338, 74, 1, 2, 1889 },
+  { 420, 74, 1, 2, 1889 },
+  { 502, 74, 1, 2, 1889 },
+  { 584, 74, 1, 2, 1889 },
+  { 666, 74, 1, 2, 1889 },
+  { 748, 74, 1, 2, 1889 },
+  { 849, 74, 1, 2, 1889 },
+  { 63, 74, 1, 2, 1889 },
+  { 174, 74, 1, 2, 1889 },
+  { 96, 108, 1, 3, 1793 },
+  { 207, 108, 1, 3, 1793 },
+  { 289, 108, 1, 3, 1793 },
+  { 371, 108, 1, 3, 1793 },
+  { 453, 108, 1, 3, 1793 },
+  { 535, 108, 1, 3, 1793 },
+  { 617, 108, 1, 3, 1793 },
+  { 699, 108, 1, 3, 1793 },
+  { 781, 108, 1, 3, 1793 },
+  { 882, 108, 1, 3, 1793 },
+  { 11, 108, 1, 3, 1793 },
+  { 122, 108, 1, 3, 1793 },
+  { 233, 108, 1, 3, 1793 },
+  { 315, 108, 1, 3, 1793 },
+  { 397, 108, 1, 3, 1793 },
+  { 479, 108, 1, 3, 1793 },
+  { 561, 108, 1, 3, 1793 },
+  { 643, 108, 1, 3, 1793 },
+  { 725, 108, 1, 3, 1793 },
+  { 826, 108, 1, 3, 1793 },
+  { 40, 108, 1, 3, 1793 },
+  { 151, 108, 1, 3, 1793 },
+  { 262, 108, 1, 3, 1793 },
+  { 344, 108, 1, 3, 1793 },
+  { 426, 108, 1, 3, 1793 },
+  { 508, 108, 1, 3, 1793 },
+  { 590, 108, 1, 3, 1793 },
+  { 672, 108, 1, 3, 1793 },
+  { 754, 108, 1, 3, 1793 },
+  { 855, 108, 1, 3, 1793 },
+  { 69, 108, 1, 3, 1793 },
+  { 180, 108, 1, 3, 1793 },
+  { 108, 110, 1, 0, 1825 },
+  { 219, 110, 1, 0, 1825 },
+  { 301, 110, 1, 0, 1825 },
+  { 383, 110, 1, 0, 1825 },
+  { 465, 110, 1, 0, 1825 },
+  { 547, 110, 1, 0, 1825 },
+  { 629, 110, 1, 0, 1825 },
+  { 711, 110, 1, 0, 1825 },
+  { 812, 110, 1, 0, 1825 },
+  { 893, 110, 1, 0, 1825 },
+  { 25, 110, 1, 0, 1825 },
+  { 136, 110, 1, 0, 1825 },
+  { 247, 110, 1, 0, 1825 },
+  { 329, 110, 1, 0, 1825 },
+  { 411, 110, 1, 0, 1825 },
+  { 493, 110, 1, 0, 1825 },
+  { 575, 110, 1, 0, 1825 },
+  { 657, 110, 1, 0, 1825 },
+  { 739, 110, 1, 0, 1825 },
+  { 840, 110, 1, 0, 1825 },
+  { 54, 110, 1, 0, 1825 },
+  { 165, 110, 1, 0, 1825 },
+  { 276, 110, 1, 0, 1825 },
+  { 358, 110, 1, 0, 1825 },
+  { 440, 110, 1, 0, 1825 },
+  { 522, 110, 1, 0, 1825 },
+  { 604, 110, 1, 0, 1825 },
+  { 686, 110, 1, 0, 1825 },
+  { 768, 110, 1, 0, 1825 },
+  { 869, 110, 1, 0, 1825 },
+  { 83, 110, 1, 0, 1825 },
+  { 194, 110, 1, 0, 1825 },
+  { 786, 104, 1, 0, 1539 },
+  { 968, 1, 106, 1, 1539 },
+  { 974, 1, 106, 1, 1508 },
+  { 980, 1, 106, 1, 1508 },
+  { 986, 1, 106, 1, 1508 },
+  { 992, 1, 106, 1, 1508 },
+  { 998, 1, 106, 1, 1508 },
+  { 1004, 1, 106, 1, 1508 },
+  { 1010, 1, 106, 1, 1508 },
+  { 1023, 1, 102, 1, 1476 },
+  { 1029, 1, 102, 1, 1476 },
+  { 1035, 1, 102, 1, 1476 },
+  { 1041, 1, 102, 1, 1476 },
+  { 1047, 1, 102, 1, 1476 },
+  { 1053, 1, 102, 1, 1476 },
+  { 1059, 1, 102, 1, 1476 },
+  { 1065, 1, 102, 1, 1476 },
+  { 1071, 1, 100, 1, 1444 },
+  { 1077, 1, 100, 1, 1444 },
+  { 1083, 1, 100, 1, 1444 },
+  { 1089, 1, 100, 1, 1444 },
+  { 1095, 1, 100, 1, 1444 },
+  { 1101, 1, 100, 1, 1444 },
+  { 1107, 1, 100, 1, 1444 },
+  { 1113, 1, 100, 1, 1444 },
+  { 909, 1, 98, 1, 1412 },
+  { 915, 1, 98, 1, 1412 },
+  { 921, 1, 98, 1, 1412 },
+  { 927, 1, 98, 1, 1412 },
+  { 933, 1, 98, 1, 1412 },
+  { 939, 1, 98, 1, 1412 },
+  { 945, 1, 98, 1, 1412 },
+  { 951, 1, 98, 1, 1412 },
+};
+
+
+  // GPRC Register Class...
+  static MCPhysReg GPRC[] = {
+    PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R0, PPC_R1, PPC_FP, PPC_BP, 
+  };
+
+  // GPRC Bit set.
+  static uint8_t GPRCBits[] = {
+    0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // GPRC_NOR0 Register Class...
+  static MCPhysReg GPRC_NOR0[] = {
+    PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, PPC_ZERO, 
+  };
+
+  // GPRC_NOR0 Bit set.
+  static uint8_t GPRC_NOR0Bits[] = {
+    0x22, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // GPRC_and_GPRC_NOR0 Register Class...
+  static MCPhysReg GPRC_and_GPRC_NOR0[] = {
+    PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, 
+  };
+
+  // GPRC_and_GPRC_NOR0 Bit set.
+  static uint8_t GPRC_and_GPRC_NOR0Bits[] = {
+    0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // CRBITRC Register Class...
+  static MCPhysReg CRBITRC[] = {
+    PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, 
+  };
+
+  // CRBITRC Bit set.
+  static uint8_t CRBITRCBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
+  };
+
+  // F4RC Register Class...
+  static MCPhysReg F4RC[] = {
+    PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, 
+  };
+
+  // F4RC Bit set.
+  static uint8_t F4RCBits[] = {
+    0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
+  };
+
+  // CRRC Register Class...
+  static MCPhysReg CRRC[] = {
+    PPC_CR0, PPC_CR1, PPC_CR5, PPC_CR6, PPC_CR7, PPC_CR2, PPC_CR3, PPC_CR4, 
+  };
+
+  // CRRC Bit set.
+  static uint8_t CRRCBits[] = {
+    0x00, 0xf8, 0x07, 
+  };
+
+  // CARRYRC Register Class...
+  static MCPhysReg CARRYRC[] = {
+    PPC_CARRY, 
+  };
+
+  // CARRYRC Bit set.
+  static uint8_t CARRYRCBits[] = {
+    0x04, 
+  };
+
+  // CCRC Register Class...
+  static MCPhysReg CCRC[] = {
+    PPC_CC, 
+  };
+
+  // CCRC Bit set.
+  static uint8_t CCRCBits[] = {
+    0x08, 
+  };
+
+  // CTRRC Register Class...
+  static MCPhysReg CTRRC[] = {
+    PPC_CTR, 
+  };
+
+  // CTRRC Bit set.
+  static uint8_t CTRRCBits[] = {
+    0x10, 
+  };
+
+  // VRSAVERC Register Class...
+  static MCPhysReg VRSAVERC[] = {
+    PPC_VRSAVE, 
+  };
+
+  // VRSAVERC Bit set.
+  static uint8_t VRSAVERCBits[] = {
+    0x00, 0x01, 
+  };
+
+  // VSFRC Register Class...
+  static MCPhysReg VSFRC[] = {
+    PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, 
+  };
+
+  // VSFRC Bit set.
+  static uint8_t VSFRCBits[] = {
+    0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // G8RC Register Class...
+  static MCPhysReg G8RC[] = {
+    PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8, 
+  };
+
+  // G8RC Bit set.
+  static uint8_t G8RCBits[] = {
+    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // G8RC_NOX0 Register Class...
+  static MCPhysReg G8RC_NOX0[] = {
+    PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, PPC_ZERO8, 
+  };
+
+  // G8RC_NOX0 Bit set.
+  static uint8_t G8RC_NOX0Bits[] = {
+    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
+  };
+
+  // G8RC_and_G8RC_NOX0 Register Class...
+  static MCPhysReg G8RC_and_G8RC_NOX0[] = {
+    PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, 
+  };
+
+  // G8RC_and_G8RC_NOX0 Bit set.
+  static uint8_t G8RC_and_G8RC_NOX0Bits[] = {
+    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // F8RC Register Class...
+  static MCPhysReg F8RC[] = {
+    PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, 
+  };
+
+  // F8RC Bit set.
+  static uint8_t F8RCBits[] = {
+    0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
+  };
+
+  // VFRC Register Class...
+  static MCPhysReg VFRC[] = {
+    PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, 
+  };
+
+  // VFRC Bit set.
+  static uint8_t VFRCBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // CTRRC8 Register Class...
+  static MCPhysReg CTRRC8[] = {
+    PPC_CTR8, 
+  };
+
+  // CTRRC8 Bit set.
+  static uint8_t CTRRC8Bits[] = {
+    0x00, 0x00, 0x08, 
+  };
+
+  // VSRC Register Class...
+  static MCPhysReg VSRC[] = {
+    PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, PPC_VSH2, PPC_VSH3, PPC_VSH4, PPC_VSH5, PPC_VSH0, PPC_VSH1, PPC_VSH6, PPC_VSH7, PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, PPC_VSH31, PPC_VSH30, PPC_VSH29, PPC_VSH28, PPC_VSH27, PPC_VSH26, PPC_VSH25, PPC_VSH24, PPC_VSH23, PPC_VSH22, PPC_VSH21, PPC_VSH20, 
+  };
+
+  // VSRC Bit set.
+  static uint8_t VSRCBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // VRRC Register Class...
+  static MCPhysReg VRRC[] = {
+    PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20, 
+  };
+
+  // VRRC Bit set.
+  static uint8_t VRRCBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // VSHRC Register Class...
+  static MCPhysReg VSHRC[] = {
+    PPC_VSH2, PPC_VSH3, PPC_VSH4, PPC_VSH5, PPC_VSH0, PPC_VSH1, PPC_VSH6, PPC_VSH7, PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, PPC_VSH31, PPC_VSH30, PPC_VSH29, PPC_VSH28, PPC_VSH27, PPC_VSH26, PPC_VSH25, PPC_VSH24, PPC_VSH23, PPC_VSH22, PPC_VSH21, PPC_VSH20, 
+  };
+
+  // VSHRC Bit set.
+  static uint8_t VSHRCBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // VSLRC Register Class...
+  static MCPhysReg VSLRC[] = {
+    PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, 
+  };
+
+  // VSLRC Bit set.
+  static uint8_t VSLRCBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+static MCRegisterClass PPCMCRegisterClasses[] = {
+  { "GPRC", GPRC, GPRCBits, 34, sizeof(GPRCBits), PPC_GPRCRegClassID, 4, 4, 1, 1 },
+  { "GPRC_NOR0", GPRC_NOR0, GPRC_NOR0Bits, 34, sizeof(GPRC_NOR0Bits), PPC_GPRC_NOR0RegClassID, 4, 4, 1, 1 },
+  { "GPRC_and_GPRC_NOR0", GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC_GPRC_and_GPRC_NOR0RegClassID, 4, 4, 1, 1 },
+  { "CRBITRC", CRBITRC, CRBITRCBits, 32, sizeof(CRBITRCBits), PPC_CRBITRCRegClassID, 4, 4, 1, 1 },
+  { "F4RC", F4RC, F4RCBits, 32, sizeof(F4RCBits), PPC_F4RCRegClassID, 4, 4, 1, 1 },
+  { "CRRC", CRRC, CRRCBits, 8, sizeof(CRRCBits), PPC_CRRCRegClassID, 4, 4, 1, 1 },
+  { "CARRYRC", CARRYRC, CARRYRCBits, 1, sizeof(CARRYRCBits), PPC_CARRYRCRegClassID, 4, 4, -1, 1 },
+  { "CCRC", CCRC, CCRCBits, 1, sizeof(CCRCBits), PPC_CCRCRegClassID, 4, 4, 1, 0 },
+  { "CTRRC", CTRRC, CTRRCBits, 1, sizeof(CTRRCBits), PPC_CTRRCRegClassID, 4, 4, 1, 0 },
+  { "VRSAVERC", VRSAVERC, VRSAVERCBits, 1, sizeof(VRSAVERCBits), PPC_VRSAVERCRegClassID, 4, 4, 1, 1 },
+  { "VSFRC", VSFRC, VSFRCBits, 64, sizeof(VSFRCBits), PPC_VSFRCRegClassID, 8, 8, 1, 1 },
+  { "G8RC", G8RC, G8RCBits, 34, sizeof(G8RCBits), PPC_G8RCRegClassID, 8, 8, 1, 1 },
+  { "G8RC_NOX0", G8RC_NOX0, G8RC_NOX0Bits, 34, sizeof(G8RC_NOX0Bits), PPC_G8RC_NOX0RegClassID, 8, 8, 1, 1 },
+  { "G8RC_and_G8RC_NOX0", G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, 33, sizeof(G8RC_and_G8RC_NOX0Bits), PPC_G8RC_and_G8RC_NOX0RegClassID, 8, 8, 1, 1 },
+  { "F8RC", F8RC, F8RCBits, 32, sizeof(F8RCBits), PPC_F8RCRegClassID, 8, 8, 1, 1 },
+  { "VFRC", VFRC, VFRCBits, 32, sizeof(VFRCBits), PPC_VFRCRegClassID, 8, 8, 1, 1 },
+  { "CTRRC8", CTRRC8, CTRRC8Bits, 1, sizeof(CTRRC8Bits), PPC_CTRRC8RegClassID, 8, 8, 1, 0 },
+  { "VSRC", VSRC, VSRCBits, 64, sizeof(VSRCBits), PPC_VSRCRegClassID, 16, 16, 1, 1 },
+  { "VRRC", VRRC, VRRCBits, 32, sizeof(VRRCBits), PPC_VRRCRegClassID, 16, 16, 1, 1 },
+  { "VSHRC", VSHRC, VSHRCBits, 32, sizeof(VSHRCBits), PPC_VSHRCRegClassID, 16, 16, 1, 1 },
+  { "VSLRC", VSLRC, VSLRCBits, 32, sizeof(VSLRCBits), PPC_VSLRCRegClassID, 16, 16, 1, 1 },
+};
+
+#endif // GET_REGINFO_MC_DESC

src/3rd-party/capstone/capstone/arch/PowerPC/PPCGenSubtargetInfo.inc

@@ -0,0 +1,70 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Subtarget Enumeration Source Fragment                                       *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+#define PPC_DeprecatedDST (1ULL << 0)
+#define PPC_DeprecatedMFTB (1ULL << 1)
+#define PPC_Directive32 (1ULL << 2)
+#define PPC_Directive64 (1ULL << 3)
+#define PPC_Directive440 (1ULL << 4)
+#define PPC_Directive601 (1ULL << 5)
+#define PPC_Directive602 (1ULL << 6)
+#define PPC_Directive603 (1ULL << 7)
+#define PPC_Directive604 (1ULL << 8)
+#define PPC_Directive620 (1ULL << 9)
+#define PPC_Directive750 (1ULL << 10)
+#define PPC_Directive970 (1ULL << 11)
+#define PPC_Directive7400 (1ULL << 12)
+#define PPC_DirectiveA2 (1ULL << 13)
+#define PPC_DirectiveE500mc (1ULL << 14)
+#define PPC_DirectiveE5500 (1ULL << 15)
+#define PPC_DirectivePwr3 (1ULL << 16)
+#define PPC_DirectivePwr4 (1ULL << 17)
+#define PPC_DirectivePwr5 (1ULL << 18)
+#define PPC_DirectivePwr5x (1ULL << 19)
+#define PPC_DirectivePwr6 (1ULL << 20)
+#define PPC_DirectivePwr6x (1ULL << 21)
+#define PPC_DirectivePwr7 (1ULL << 22)
+#define PPC_DirectivePwr8 (1ULL << 23)
+#define PPC_Feature64Bit (1ULL << 24)
+#define PPC_Feature64BitRegs (1ULL << 25)
+#define PPC_FeatureAltivec (1ULL << 26)
+#define PPC_FeatureBookE (1ULL << 27)
+#define PPC_FeatureCRBits (1ULL << 28)
+#define PPC_FeatureE500 (1ULL << 29)
+#define PPC_FeatureELFv1 (1ULL << 30)
+#define PPC_FeatureELFv2 (1ULL << 31)
+#define PPC_FeatureFCPSGN (1ULL << 32)
+#define PPC_FeatureFPCVT (1ULL << 33)
+#define PPC_FeatureFPRND (1ULL << 34)
+#define PPC_FeatureFRE (1ULL << 35)
+#define PPC_FeatureFRES (1ULL << 36)
+#define PPC_FeatureFRSQRTE (1ULL << 37)
+#define PPC_FeatureFRSQRTES (1ULL << 38)
+#define PPC_FeatureFSqrt (1ULL << 39)
+#define PPC_FeatureISEL (1ULL << 40)
+#define PPC_FeatureLDBRX (1ULL << 41)
+#define PPC_FeatureLFIWAX (1ULL << 42)
+#define PPC_FeatureMFOCRF (1ULL << 43)
+#define PPC_FeaturePOPCNTD (1ULL << 44)
+#define PPC_FeaturePPC4xx (1ULL << 45)
+#define PPC_FeaturePPC6xx (1ULL << 46)
+#define PPC_FeatureQPX (1ULL << 47)
+#define PPC_FeatureRecipPrec (1ULL << 48)
+#define PPC_FeatureSPE (1ULL << 49)
+#define PPC_FeatureSTFIWX (1ULL << 50)
+#define PPC_FeatureVSX (1ULL << 51)
+
+#endif // GET_SUBTARGETINFO_ENUM
+

src/3rd-party/capstone/capstone/arch/PowerPC/PPCInstPrinter.h

@@ -0,0 +1,15 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_PPCINSTPRINTER_H
+#define CS_PPCINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void PPC_printInst(MCInst *MI, SStream *O, void *Info);
+
+void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
+
+#endif

src/3rd-party/capstone/capstone/arch/PowerPC/PPCMapping.h

@@ -0,0 +1,34 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_PPC_MAP_H
+#define CS_PPC_MAP_H
+
+#include "../../include/capstone.h"
+
+// return name of regiser in friendly string
+const char *PPC_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *PPC_insn_name(csh handle, unsigned int id);
+const char *PPC_group_name(csh handle, unsigned int id);
+
+// map internal raw register to 'public' register
+ppc_reg PPC_map_register(unsigned int r);
+
+struct ppc_alias {
+	unsigned int id;	// instruction id
+	int cc;	// code condition
+	const char *mnem;
+};
+
+// given alias mnemonic, return instruction ID & CC
+bool PPC_alias_insn(const char *name, struct ppc_alias *alias);
+
+// check if this insn is relative branch
+bool PPC_abs_branch(cs_struct *h, unsigned int id);
+
+#endif
+

src/3rd-party/capstone/capstone/arch/PowerPC/PPCModule.c

@@ -0,0 +1,60 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_POWERPC
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "PPCDisassembler.h"
+#include "PPCInstPrinter.h"
+#include "PPCMapping.h"
+
+static cs_err init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	// verify if requested mode is valid
+	if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
+				CS_MODE_BIG_ENDIAN))
+		return CS_ERR_MODE;
+
+	mri = (MCRegisterInfo *) cs_mem_malloc(sizeof(*mri));
+
+	PPC_init(mri);
+	ud->printer = PPC_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = PPC_getInstruction;
+	ud->post_printer = PPC_post_printer;
+
+	ud->reg_name = PPC_reg_name;
+	ud->insn_id = PPC_get_insn_id;
+	ud->insn_name = PPC_insn_name;
+	ud->group_name = PPC_group_name;
+
+	return CS_ERR_OK;
+}
+
+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax = (int) value;
+
+	return CS_ERR_OK;
+}
+
+static void destroy(cs_struct *handle)
+{
+}
+
+void PPC_enable(void)
+{
+	arch_init[CS_ARCH_PPC] = init;
+	arch_option[CS_ARCH_PPC] = option;
+	arch_destroy[CS_ARCH_PPC] = destroy;
+
+	// support this arch
+	all_arch |= (1 << CS_ARCH_PPC);
+}
+
+#endif

src/3rd-party/capstone/capstone/arch/PowerPC/PPCPredicates.h

@@ -0,0 +1,62 @@
+//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the PowerPC branch predicates.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_POWERPC_PPCPREDICATES_H
+#define CS_POWERPC_PPCPREDICATES_H
+
+#include "../../include/ppc.h"
+
+// NOTE: duplicate of ppc_bc in ppc.h to maitain code compatibility with LLVM
+typedef enum ppc_predicate {
+  PPC_PRED_LT       = (0 << 5) | 12,
+  PPC_PRED_LE       = (1 << 5) |  4,
+  PPC_PRED_EQ       = (2 << 5) | 12,
+  PPC_PRED_GE       = (0 << 5) |  4,
+  PPC_PRED_GT       = (1 << 5) | 12,
+  PPC_PRED_NE       = (2 << 5) |  4,
+  PPC_PRED_UN       = (3 << 5) | 12,
+  PPC_PRED_NU       = (3 << 5) |  4,
+  PPC_PRED_LT_MINUS = (0 << 5) | 14,
+  PPC_PRED_LE_MINUS = (1 << 5) |  6,
+  PPC_PRED_EQ_MINUS = (2 << 5) | 14,
+  PPC_PRED_GE_MINUS = (0 << 5) |  6,
+  PPC_PRED_GT_MINUS = (1 << 5) | 14,
+  PPC_PRED_NE_MINUS = (2 << 5) |  6,
+  PPC_PRED_UN_MINUS = (3 << 5) | 14,
+  PPC_PRED_NU_MINUS = (3 << 5) |  6,
+  PPC_PRED_LT_PLUS  = (0 << 5) | 15,
+  PPC_PRED_LE_PLUS  = (1 << 5) |  7,
+  PPC_PRED_EQ_PLUS  = (2 << 5) | 15,
+  PPC_PRED_GE_PLUS  = (0 << 5) |  7,
+  PPC_PRED_GT_PLUS  = (1 << 5) | 15,
+  PPC_PRED_NE_PLUS  = (2 << 5) |  7,
+  PPC_PRED_UN_PLUS  = (3 << 5) | 15,
+  PPC_PRED_NU_PLUS  = (3 << 5) |  7,
+
+  // When dealing with individual condition-register bits, we have simple set
+  // and unset predicates.
+  PPC_PRED_BIT_SET =   1024,
+  PPC_PRED_BIT_UNSET = 1025
+} ppc_predicate;
+
+/// Invert the specified predicate.  != -> ==, < -> >=.
+ppc_predicate InvertPredicate(ppc_predicate Opcode);
+
+/// Assume the condition register is set by MI(a,b), return the predicate if
+/// we modify the instructions such that condition register is set by MI(b,a).
+ppc_predicate getSwappedPredicate(ppc_predicate Opcode);
+
+#endif

src/3rd-party/capstone/capstone/arch/Sparc/Sparc.h

@@ -0,0 +1,63 @@
+//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the entry points for global functions defined in the LLVM
+// Sparc back-end.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_SPARC_TARGET_SPARC_H
+#define CS_SPARC_TARGET_SPARC_H
+
+#include "../../include/sparc.h"
+
+inline static char *SPARCCondCodeToString(sparc_cc CC)
+{
+	switch (CC) {
+		default:	return NULL;	// unreachable
+		case SPARC_CC_ICC_A:  return "a";
+		case SPARC_CC_ICC_N:   return "n";
+		case SPARC_CC_ICC_NE:  return "ne";
+		case SPARC_CC_ICC_E:   return "e";
+		case SPARC_CC_ICC_G:   return "g";
+		case SPARC_CC_ICC_LE:  return "le";
+		case SPARC_CC_ICC_GE:  return "ge";
+		case SPARC_CC_ICC_L:   return "l";
+		case SPARC_CC_ICC_GU:  return "gu";
+		case SPARC_CC_ICC_LEU: return "leu";
+		case SPARC_CC_ICC_CC:  return "cc";
+		case SPARC_CC_ICC_CS:  return "cs";
+		case SPARC_CC_ICC_POS: return "pos";
+		case SPARC_CC_ICC_NEG: return "neg";
+		case SPARC_CC_ICC_VC:  return "vc";
+		case SPARC_CC_ICC_VS:  return "vs";
+
+		case SPARC_CC_FCC_A:   return "a";
+		case SPARC_CC_FCC_N:   return "n";
+		case SPARC_CC_FCC_U:   return "u";
+		case SPARC_CC_FCC_G:   return "g";
+		case SPARC_CC_FCC_UG:  return "ug";
+		case SPARC_CC_FCC_L:   return "l";
+		case SPARC_CC_FCC_UL:  return "ul";
+		case SPARC_CC_FCC_LG:  return "lg";
+		case SPARC_CC_FCC_NE:  return "ne";
+		case SPARC_CC_FCC_E:   return "e";
+		case SPARC_CC_FCC_UE:  return "ue";
+		case SPARC_CC_FCC_GE:  return "ge";
+		case SPARC_CC_FCC_UGE: return "uge";
+		case SPARC_CC_FCC_LE:  return "le";
+		case SPARC_CC_FCC_ULE: return "ule";
+		case SPARC_CC_FCC_O:   return "o";
+	}
+}
+
+#endif

src/3rd-party/capstone/capstone/arch/Sparc/SparcDisassembler.c

@@ -0,0 +1,502 @@
+//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_SPARC
+
+#include <stdio.h>	// DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_ENUM
+#include "SparcGenRegisterInfo.inc"
+static const unsigned IntRegDecoderTable[] = {
+	SP_G0,  SP_G1,  SP_G2,  SP_G3,
+	SP_G4,  SP_G5,  SP_G6,  SP_G7,
+	SP_O0,  SP_O1,  SP_O2,  SP_O3,
+	SP_O4,  SP_O5,  SP_O6,  SP_O7,
+	SP_L0,  SP_L1,  SP_L2,  SP_L3,
+	SP_L4,  SP_L5,  SP_L6,  SP_L7,
+	SP_I0,  SP_I1,  SP_I2,  SP_I3,
+	SP_I4,  SP_I5,  SP_I6,  SP_I7
+};
+
+static const unsigned FPRegDecoderTable[] = {
+	SP_F0,   SP_F1,   SP_F2,   SP_F3,
+	SP_F4,   SP_F5,   SP_F6,   SP_F7,
+	SP_F8,   SP_F9,   SP_F10,  SP_F11,
+	SP_F12,  SP_F13,  SP_F14,  SP_F15,
+	SP_F16,  SP_F17,  SP_F18,  SP_F19,
+	SP_F20,  SP_F21,  SP_F22,  SP_F23,
+	SP_F24,  SP_F25,  SP_F26,  SP_F27,
+	SP_F28,  SP_F29,  SP_F30,  SP_F31
+};
+
+static const unsigned DFPRegDecoderTable[] = {
+	SP_D0,   SP_D16,  SP_D1,   SP_D17,
+	SP_D2,   SP_D18,  SP_D3,   SP_D19,
+	SP_D4,   SP_D20,  SP_D5,   SP_D21,
+	SP_D6,   SP_D22,  SP_D7,   SP_D23,
+	SP_D8,   SP_D24,  SP_D9,   SP_D25,
+	SP_D10,  SP_D26,  SP_D11,  SP_D27,
+	SP_D12,  SP_D28,  SP_D13,  SP_D29,
+	SP_D14,  SP_D30,  SP_D15,  SP_D31
+};
+
+static const unsigned QFPRegDecoderTable[] = {
+	SP_Q0,  SP_Q8,   ~0U,  ~0U,
+	SP_Q1,  SP_Q9,   ~0U,  ~0U,
+	SP_Q2,  SP_Q10,  ~0U,  ~0U,
+	SP_Q3,  SP_Q11,  ~0U,  ~0U,
+	SP_Q4,  SP_Q12,  ~0U,  ~0U,
+	SP_Q5,  SP_Q13,  ~0U,  ~0U,
+	SP_Q6,  SP_Q14,  ~0U,  ~0U,
+	SP_Q7,  SP_Q15,  ~0U,  ~0U
+};
+
+static const unsigned FCCRegDecoderTable[] = {
+	SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3
+};
+
+static uint64_t getFeatureBits(int mode)
+{
+	// support everything
+	return (uint64_t)-1;
+}
+
+static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = IntRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = IntRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = FPRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = DFPRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = QFPRegDecoderTable[RegNo];
+	if (Reg == ~0U)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	if (RegNo > 3)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]);
+
+	return MCDisassembler_Success;
+}
+
+
+static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+
+
+#define GET_SUBTARGETINFO_ENUM
+#include "SparcGenSubtargetInfo.inc"
+#include "SparcGenDisassemblerTables.inc"
+
+/// readInstruction - read four bytes and return 32 bit word.
+static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn)
+{
+	uint8_t Bytes[4];
+
+	if (len < 4)
+		// not enough data
+		return MCDisassembler_Fail;
+
+	memcpy(Bytes, code, 4);
+
+	// Encoded as a big-endian 32-bit word in the stream.
+	*Insn = (Bytes[3] <<  0) |
+		(Bytes[2] <<  8) |
+		(Bytes[1] << 16) |
+		(Bytes[0] << 24);
+
+	return MCDisassembler_Success;
+}
+
+bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
+		uint16_t *size, uint64_t address, void *info)
+{
+	uint32_t Insn;
+	DecodeStatus Result;
+	
+	Result = readInstruction32(code, code_len, &Insn);
+	if (Result == MCDisassembler_Fail)
+		return false;
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
+	}
+
+	Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address,
+			(MCRegisterInfo *)info, 0);
+	if (Result != MCDisassembler_Fail) {
+		*size = 4;
+		return true;
+	}
+
+	return false;
+}
+
+typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder);
+
+static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder,
+		bool isLoad, DecodeFunc DecodeRD)
+{
+	DecodeStatus status;
+	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
+	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
+	bool isImm = fieldFromInstruction_4(insn, 13, 1);
+	unsigned rs2 = 0;
+	unsigned simm13 = 0;
+
+	if (isImm)
+		simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+	else
+		rs2 = fieldFromInstruction_4(insn, 0, 5);
+
+	if (isLoad) {
+		status = DecodeRD(MI, rd, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	// Decode rs1.
+	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode imm|rs2.
+	if (isImm)
+		MCOperand_CreateImm0(MI, simm13);
+	else {
+		status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	if (!isLoad) {
+		status = DecodeRD(MI, rd, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, true,
+			DecodeIntRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, true,
+			DecodeFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, true,
+			DecodeDFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, true,
+			DecodeQFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, false,
+			DecodeIntRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, false,
+			DecodeFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, false,
+			DecodeDFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, false,
+			DecodeQFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeCall(MCInst *MI, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned tgt = fieldFromInstruction_4(insn, 0, 30);
+	tgt <<= 2;
+
+	MCOperand_CreateImm0(MI, tgt);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+
+	MCOperand_CreateImm0(MI, tgt);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	DecodeStatus status;
+	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
+	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
+	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
+	unsigned rs2 = 0;
+	unsigned simm13 = 0;
+
+	if (isImm)
+		simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+	else
+		rs2 = fieldFromInstruction_4(insn, 0, 5);
+
+	// Decode RD.
+	status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS1.
+	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS1 | SIMM13.
+	if (isImm)
+		MCOperand_CreateImm0(MI, simm13);
+	else {
+		status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	DecodeStatus status;
+	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
+	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
+	unsigned rs2 = 0;
+	unsigned simm13 = 0;
+	if (isImm)
+		simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+	else
+		rs2 = fieldFromInstruction_4(insn, 0, 5);
+
+	// Decode RS1.
+	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS2 | SIMM13.
+	if (isImm)
+		MCOperand_CreateImm0(MI, simm13);
+	else {
+		status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	DecodeStatus status;
+	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
+	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
+	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
+	unsigned rs2 = 0;
+	unsigned simm13 = 0;
+
+	if (isImm)
+		simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+	else
+		rs2 = fieldFromInstruction_4(insn, 0, 5);
+
+	// Decode RD.
+	status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS1.
+	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS1 | SIMM13.
+	if (isImm)
+		MCOperand_CreateImm0(MI, simm13);
+	else {
+		status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+void Sparc_init(MCRegisterInfo *MRI)
+{
+	/*
+	InitMCRegisterInfo(SparcRegDesc, 119, RA, PC,
+			SparcMCRegisterClasses, 8,
+			SparcRegUnitRoots,
+			86,
+			SparcRegDiffLists,
+			SparcRegStrings,
+			SparcSubRegIdxLists,
+			7,
+			SparcSubRegIdxRanges,
+			SparcRegEncodingTable);
+	*/
+
+	MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119,
+			0, 0,
+			SparcMCRegisterClasses, 8,
+			0, 0,
+			SparcRegDiffLists,
+			0,
+			SparcSubRegIdxLists, 7,
+			0);
+}
+
+#endif

src/3rd-party/capstone/capstone/arch/Sparc/SparcDisassembler.h

@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_SPARCDISASSEMBLER_H
+#define CS_SPARCDISASSEMBLER_H
+
+#include <stdint.h>
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void Sparc_init(MCRegisterInfo *MRI);
+
+bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+

src/3rd-party/capstone/capstone/arch/Sparc/SparcGenInstrInfo.inc

@@ -0,0 +1,512 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Instruction Enum Values                                              *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+enum {
+    SP_PHI	= 0,
+    SP_INLINEASM	= 1,
+    SP_CFI_INSTRUCTION	= 2,
+    SP_EH_LABEL	= 3,
+    SP_GC_LABEL	= 4,
+    SP_KILL	= 5,
+    SP_EXTRACT_SUBREG	= 6,
+    SP_INSERT_SUBREG	= 7,
+    SP_IMPLICIT_DEF	= 8,
+    SP_SUBREG_TO_REG	= 9,
+    SP_COPY_TO_REGCLASS	= 10,
+    SP_DBG_VALUE	= 11,
+    SP_REG_SEQUENCE	= 12,
+    SP_COPY	= 13,
+    SP_BUNDLE	= 14,
+    SP_LIFETIME_START	= 15,
+    SP_LIFETIME_END	= 16,
+    SP_STACKMAP	= 17,
+    SP_PATCHPOINT	= 18,
+    SP_LOAD_STACK_GUARD	= 19,
+    SP_ADDCCri	= 20,
+    SP_ADDCCrr	= 21,
+    SP_ADDCri	= 22,
+    SP_ADDCrr	= 23,
+    SP_ADDEri	= 24,
+    SP_ADDErr	= 25,
+    SP_ADDXC	= 26,
+    SP_ADDXCCC	= 27,
+    SP_ADDXri	= 28,
+    SP_ADDXrr	= 29,
+    SP_ADDri	= 30,
+    SP_ADDrr	= 31,
+    SP_ADJCALLSTACKDOWN	= 32,
+    SP_ADJCALLSTACKUP	= 33,
+    SP_ALIGNADDR	= 34,
+    SP_ALIGNADDRL	= 35,
+    SP_ANDCCri	= 36,
+    SP_ANDCCrr	= 37,
+    SP_ANDNCCri	= 38,
+    SP_ANDNCCrr	= 39,
+    SP_ANDNri	= 40,
+    SP_ANDNrr	= 41,
+    SP_ANDXNrr	= 42,
+    SP_ANDXri	= 43,
+    SP_ANDXrr	= 44,
+    SP_ANDri	= 45,
+    SP_ANDrr	= 46,
+    SP_ARRAY16	= 47,
+    SP_ARRAY32	= 48,
+    SP_ARRAY8	= 49,
+    SP_ATOMIC_LOAD_ADD_32	= 50,
+    SP_ATOMIC_LOAD_ADD_64	= 51,
+    SP_ATOMIC_LOAD_AND_32	= 52,
+    SP_ATOMIC_LOAD_AND_64	= 53,
+    SP_ATOMIC_LOAD_MAX_32	= 54,
+    SP_ATOMIC_LOAD_MAX_64	= 55,
+    SP_ATOMIC_LOAD_MIN_32	= 56,
+    SP_ATOMIC_LOAD_MIN_64	= 57,
+    SP_ATOMIC_LOAD_NAND_32	= 58,
+    SP_ATOMIC_LOAD_NAND_64	= 59,
+    SP_ATOMIC_LOAD_OR_32	= 60,
+    SP_ATOMIC_LOAD_OR_64	= 61,
+    SP_ATOMIC_LOAD_SUB_32	= 62,
+    SP_ATOMIC_LOAD_SUB_64	= 63,
+    SP_ATOMIC_LOAD_UMAX_32	= 64,
+    SP_ATOMIC_LOAD_UMAX_64	= 65,
+    SP_ATOMIC_LOAD_UMIN_32	= 66,
+    SP_ATOMIC_LOAD_UMIN_64	= 67,
+    SP_ATOMIC_LOAD_XOR_32	= 68,
+    SP_ATOMIC_LOAD_XOR_64	= 69,
+    SP_ATOMIC_SWAP_64	= 70,
+    SP_BA	= 71,
+    SP_BCOND	= 72,
+    SP_BCONDA	= 73,
+    SP_BINDri	= 74,
+    SP_BINDrr	= 75,
+    SP_BMASK	= 76,
+    SP_BPFCC	= 77,
+    SP_BPFCCA	= 78,
+    SP_BPFCCANT	= 79,
+    SP_BPFCCNT	= 80,
+    SP_BPGEZapn	= 81,
+    SP_BPGEZapt	= 82,
+    SP_BPGEZnapn	= 83,
+    SP_BPGEZnapt	= 84,
+    SP_BPGZapn	= 85,
+    SP_BPGZapt	= 86,
+    SP_BPGZnapn	= 87,
+    SP_BPGZnapt	= 88,
+    SP_BPICC	= 89,
+    SP_BPICCA	= 90,
+    SP_BPICCANT	= 91,
+    SP_BPICCNT	= 92,
+    SP_BPLEZapn	= 93,
+    SP_BPLEZapt	= 94,
+    SP_BPLEZnapn	= 95,
+    SP_BPLEZnapt	= 96,
+    SP_BPLZapn	= 97,
+    SP_BPLZapt	= 98,
+    SP_BPLZnapn	= 99,
+    SP_BPLZnapt	= 100,
+    SP_BPNZapn	= 101,
+    SP_BPNZapt	= 102,
+    SP_BPNZnapn	= 103,
+    SP_BPNZnapt	= 104,
+    SP_BPXCC	= 105,
+    SP_BPXCCA	= 106,
+    SP_BPXCCANT	= 107,
+    SP_BPXCCNT	= 108,
+    SP_BPZapn	= 109,
+    SP_BPZapt	= 110,
+    SP_BPZnapn	= 111,
+    SP_BPZnapt	= 112,
+    SP_BSHUFFLE	= 113,
+    SP_CALL	= 114,
+    SP_CALLri	= 115,
+    SP_CALLrr	= 116,
+    SP_CASXrr	= 117,
+    SP_CASrr	= 118,
+    SP_CMASK16	= 119,
+    SP_CMASK32	= 120,
+    SP_CMASK8	= 121,
+    SP_CMPri	= 122,
+    SP_CMPrr	= 123,
+    SP_EDGE16	= 124,
+    SP_EDGE16L	= 125,
+    SP_EDGE16LN	= 126,
+    SP_EDGE16N	= 127,
+    SP_EDGE32	= 128,
+    SP_EDGE32L	= 129,
+    SP_EDGE32LN	= 130,
+    SP_EDGE32N	= 131,
+    SP_EDGE8	= 132,
+    SP_EDGE8L	= 133,
+    SP_EDGE8LN	= 134,
+    SP_EDGE8N	= 135,
+    SP_FABSD	= 136,
+    SP_FABSQ	= 137,
+    SP_FABSS	= 138,
+    SP_FADDD	= 139,
+    SP_FADDQ	= 140,
+    SP_FADDS	= 141,
+    SP_FALIGNADATA	= 142,
+    SP_FAND	= 143,
+    SP_FANDNOT1	= 144,
+    SP_FANDNOT1S	= 145,
+    SP_FANDNOT2	= 146,
+    SP_FANDNOT2S	= 147,
+    SP_FANDS	= 148,
+    SP_FBCOND	= 149,
+    SP_FBCONDA	= 150,
+    SP_FCHKSM16	= 151,
+    SP_FCMPD	= 152,
+    SP_FCMPEQ16	= 153,
+    SP_FCMPEQ32	= 154,
+    SP_FCMPGT16	= 155,
+    SP_FCMPGT32	= 156,
+    SP_FCMPLE16	= 157,
+    SP_FCMPLE32	= 158,
+    SP_FCMPNE16	= 159,
+    SP_FCMPNE32	= 160,
+    SP_FCMPQ	= 161,
+    SP_FCMPS	= 162,
+    SP_FDIVD	= 163,
+    SP_FDIVQ	= 164,
+    SP_FDIVS	= 165,
+    SP_FDMULQ	= 166,
+    SP_FDTOI	= 167,
+    SP_FDTOQ	= 168,
+    SP_FDTOS	= 169,
+    SP_FDTOX	= 170,
+    SP_FEXPAND	= 171,
+    SP_FHADDD	= 172,
+    SP_FHADDS	= 173,
+    SP_FHSUBD	= 174,
+    SP_FHSUBS	= 175,
+    SP_FITOD	= 176,
+    SP_FITOQ	= 177,
+    SP_FITOS	= 178,
+    SP_FLCMPD	= 179,
+    SP_FLCMPS	= 180,
+    SP_FLUSHW	= 181,
+    SP_FMEAN16	= 182,
+    SP_FMOVD	= 183,
+    SP_FMOVD_FCC	= 184,
+    SP_FMOVD_ICC	= 185,
+    SP_FMOVD_XCC	= 186,
+    SP_FMOVQ	= 187,
+    SP_FMOVQ_FCC	= 188,
+    SP_FMOVQ_ICC	= 189,
+    SP_FMOVQ_XCC	= 190,
+    SP_FMOVRGEZD	= 191,
+    SP_FMOVRGEZQ	= 192,
+    SP_FMOVRGEZS	= 193,
+    SP_FMOVRGZD	= 194,
+    SP_FMOVRGZQ	= 195,
+    SP_FMOVRGZS	= 196,
+    SP_FMOVRLEZD	= 197,
+    SP_FMOVRLEZQ	= 198,
+    SP_FMOVRLEZS	= 199,
+    SP_FMOVRLZD	= 200,
+    SP_FMOVRLZQ	= 201,
+    SP_FMOVRLZS	= 202,
+    SP_FMOVRNZD	= 203,
+    SP_FMOVRNZQ	= 204,
+    SP_FMOVRNZS	= 205,
+    SP_FMOVRZD	= 206,
+    SP_FMOVRZQ	= 207,
+    SP_FMOVRZS	= 208,
+    SP_FMOVS	= 209,
+    SP_FMOVS_FCC	= 210,
+    SP_FMOVS_ICC	= 211,
+    SP_FMOVS_XCC	= 212,
+    SP_FMUL8SUX16	= 213,
+    SP_FMUL8ULX16	= 214,
+    SP_FMUL8X16	= 215,
+    SP_FMUL8X16AL	= 216,
+    SP_FMUL8X16AU	= 217,
+    SP_FMULD	= 218,
+    SP_FMULD8SUX16	= 219,
+    SP_FMULD8ULX16	= 220,
+    SP_FMULQ	= 221,
+    SP_FMULS	= 222,
+    SP_FNADDD	= 223,
+    SP_FNADDS	= 224,
+    SP_FNAND	= 225,
+    SP_FNANDS	= 226,
+    SP_FNEGD	= 227,
+    SP_FNEGQ	= 228,
+    SP_FNEGS	= 229,
+    SP_FNHADDD	= 230,
+    SP_FNHADDS	= 231,
+    SP_FNMULD	= 232,
+    SP_FNMULS	= 233,
+    SP_FNOR	= 234,
+    SP_FNORS	= 235,
+    SP_FNOT1	= 236,
+    SP_FNOT1S	= 237,
+    SP_FNOT2	= 238,
+    SP_FNOT2S	= 239,
+    SP_FNSMULD	= 240,
+    SP_FONE	= 241,
+    SP_FONES	= 242,
+    SP_FOR	= 243,
+    SP_FORNOT1	= 244,
+    SP_FORNOT1S	= 245,
+    SP_FORNOT2	= 246,
+    SP_FORNOT2S	= 247,
+    SP_FORS	= 248,
+    SP_FPACK16	= 249,
+    SP_FPACK32	= 250,
+    SP_FPACKFIX	= 251,
+    SP_FPADD16	= 252,
+    SP_FPADD16S	= 253,
+    SP_FPADD32	= 254,
+    SP_FPADD32S	= 255,
+    SP_FPADD64	= 256,
+    SP_FPMERGE	= 257,
+    SP_FPSUB16	= 258,
+    SP_FPSUB16S	= 259,
+    SP_FPSUB32	= 260,
+    SP_FPSUB32S	= 261,
+    SP_FQTOD	= 262,
+    SP_FQTOI	= 263,
+    SP_FQTOS	= 264,
+    SP_FQTOX	= 265,
+    SP_FSLAS16	= 266,
+    SP_FSLAS32	= 267,
+    SP_FSLL16	= 268,
+    SP_FSLL32	= 269,
+    SP_FSMULD	= 270,
+    SP_FSQRTD	= 271,
+    SP_FSQRTQ	= 272,
+    SP_FSQRTS	= 273,
+    SP_FSRA16	= 274,
+    SP_FSRA32	= 275,
+    SP_FSRC1	= 276,
+    SP_FSRC1S	= 277,
+    SP_FSRC2	= 278,
+    SP_FSRC2S	= 279,
+    SP_FSRL16	= 280,
+    SP_FSRL32	= 281,
+    SP_FSTOD	= 282,
+    SP_FSTOI	= 283,
+    SP_FSTOQ	= 284,
+    SP_FSTOX	= 285,
+    SP_FSUBD	= 286,
+    SP_FSUBQ	= 287,
+    SP_FSUBS	= 288,
+    SP_FXNOR	= 289,
+    SP_FXNORS	= 290,
+    SP_FXOR	= 291,
+    SP_FXORS	= 292,
+    SP_FXTOD	= 293,
+    SP_FXTOQ	= 294,
+    SP_FXTOS	= 295,
+    SP_FZERO	= 296,
+    SP_FZEROS	= 297,
+    SP_GETPCX	= 298,
+    SP_JMPLri	= 299,
+    SP_JMPLrr	= 300,
+    SP_LDDFri	= 301,
+    SP_LDDFrr	= 302,
+    SP_LDFri	= 303,
+    SP_LDFrr	= 304,
+    SP_LDQFri	= 305,
+    SP_LDQFrr	= 306,
+    SP_LDSBri	= 307,
+    SP_LDSBrr	= 308,
+    SP_LDSHri	= 309,
+    SP_LDSHrr	= 310,
+    SP_LDSWri	= 311,
+    SP_LDSWrr	= 312,
+    SP_LDUBri	= 313,
+    SP_LDUBrr	= 314,
+    SP_LDUHri	= 315,
+    SP_LDUHrr	= 316,
+    SP_LDXri	= 317,
+    SP_LDXrr	= 318,
+    SP_LDri	= 319,
+    SP_LDrr	= 320,
+    SP_LEAX_ADDri	= 321,
+    SP_LEA_ADDri	= 322,
+    SP_LZCNT	= 323,
+    SP_MEMBARi	= 324,
+    SP_MOVDTOX	= 325,
+    SP_MOVFCCri	= 326,
+    SP_MOVFCCrr	= 327,
+    SP_MOVICCri	= 328,
+    SP_MOVICCrr	= 329,
+    SP_MOVRGEZri	= 330,
+    SP_MOVRGEZrr	= 331,
+    SP_MOVRGZri	= 332,
+    SP_MOVRGZrr	= 333,
+    SP_MOVRLEZri	= 334,
+    SP_MOVRLEZrr	= 335,
+    SP_MOVRLZri	= 336,
+    SP_MOVRLZrr	= 337,
+    SP_MOVRNZri	= 338,
+    SP_MOVRNZrr	= 339,
+    SP_MOVRRZri	= 340,
+    SP_MOVRRZrr	= 341,
+    SP_MOVSTOSW	= 342,
+    SP_MOVSTOUW	= 343,
+    SP_MOVWTOS	= 344,
+    SP_MOVXCCri	= 345,
+    SP_MOVXCCrr	= 346,
+    SP_MOVXTOD	= 347,
+    SP_MULXri	= 348,
+    SP_MULXrr	= 349,
+    SP_NOP	= 350,
+    SP_ORCCri	= 351,
+    SP_ORCCrr	= 352,
+    SP_ORNCCri	= 353,
+    SP_ORNCCrr	= 354,
+    SP_ORNri	= 355,
+    SP_ORNrr	= 356,
+    SP_ORXNrr	= 357,
+    SP_ORXri	= 358,
+    SP_ORXrr	= 359,
+    SP_ORri	= 360,
+    SP_ORrr	= 361,
+    SP_PDIST	= 362,
+    SP_PDISTN	= 363,
+    SP_POPCrr	= 364,
+    SP_RDY	= 365,
+    SP_RESTOREri	= 366,
+    SP_RESTORErr	= 367,
+    SP_RET	= 368,
+    SP_RETL	= 369,
+    SP_RETTri	= 370,
+    SP_RETTrr	= 371,
+    SP_SAVEri	= 372,
+    SP_SAVErr	= 373,
+    SP_SDIVCCri	= 374,
+    SP_SDIVCCrr	= 375,
+    SP_SDIVXri	= 376,
+    SP_SDIVXrr	= 377,
+    SP_SDIVri	= 378,
+    SP_SDIVrr	= 379,
+    SP_SELECT_CC_DFP_FCC	= 380,
+    SP_SELECT_CC_DFP_ICC	= 381,
+    SP_SELECT_CC_FP_FCC	= 382,
+    SP_SELECT_CC_FP_ICC	= 383,
+    SP_SELECT_CC_Int_FCC	= 384,
+    SP_SELECT_CC_Int_ICC	= 385,
+    SP_SELECT_CC_QFP_FCC	= 386,
+    SP_SELECT_CC_QFP_ICC	= 387,
+    SP_SETHIXi	= 388,
+    SP_SETHIi	= 389,
+    SP_SHUTDOWN	= 390,
+    SP_SIAM	= 391,
+    SP_SLLXri	= 392,
+    SP_SLLXrr	= 393,
+    SP_SLLri	= 394,
+    SP_SLLrr	= 395,
+    SP_SMULCCri	= 396,
+    SP_SMULCCrr	= 397,
+    SP_SMULri	= 398,
+    SP_SMULrr	= 399,
+    SP_SRAXri	= 400,
+    SP_SRAXrr	= 401,
+    SP_SRAri	= 402,
+    SP_SRArr	= 403,
+    SP_SRLXri	= 404,
+    SP_SRLXrr	= 405,
+    SP_SRLri	= 406,
+    SP_SRLrr	= 407,
+    SP_STBAR	= 408,
+    SP_STBri	= 409,
+    SP_STBrr	= 410,
+    SP_STDFri	= 411,
+    SP_STDFrr	= 412,
+    SP_STFri	= 413,
+    SP_STFrr	= 414,
+    SP_STHri	= 415,
+    SP_STHrr	= 416,
+    SP_STQFri	= 417,
+    SP_STQFrr	= 418,
+    SP_STXri	= 419,
+    SP_STXrr	= 420,
+    SP_STri	= 421,
+    SP_STrr	= 422,
+    SP_SUBCCri	= 423,
+    SP_SUBCCrr	= 424,
+    SP_SUBCri	= 425,
+    SP_SUBCrr	= 426,
+    SP_SUBEri	= 427,
+    SP_SUBErr	= 428,
+    SP_SUBXri	= 429,
+    SP_SUBXrr	= 430,
+    SP_SUBri	= 431,
+    SP_SUBrr	= 432,
+    SP_SWAPri	= 433,
+    SP_SWAPrr	= 434,
+    SP_TA3	= 435,
+    SP_TA5	= 436,
+    SP_TADDCCTVri	= 437,
+    SP_TADDCCTVrr	= 438,
+    SP_TADDCCri	= 439,
+    SP_TADDCCrr	= 440,
+    SP_TICCri	= 441,
+    SP_TICCrr	= 442,
+    SP_TLS_ADDXrr	= 443,
+    SP_TLS_ADDrr	= 444,
+    SP_TLS_CALL	= 445,
+    SP_TLS_LDXrr	= 446,
+    SP_TLS_LDrr	= 447,
+    SP_TSUBCCTVri	= 448,
+    SP_TSUBCCTVrr	= 449,
+    SP_TSUBCCri	= 450,
+    SP_TSUBCCrr	= 451,
+    SP_TXCCri	= 452,
+    SP_TXCCrr	= 453,
+    SP_UDIVCCri	= 454,
+    SP_UDIVCCrr	= 455,
+    SP_UDIVXri	= 456,
+    SP_UDIVXrr	= 457,
+    SP_UDIVri	= 458,
+    SP_UDIVrr	= 459,
+    SP_UMULCCri	= 460,
+    SP_UMULCCrr	= 461,
+    SP_UMULXHI	= 462,
+    SP_UMULri	= 463,
+    SP_UMULrr	= 464,
+    SP_UNIMP	= 465,
+    SP_V9FCMPD	= 466,
+    SP_V9FCMPED	= 467,
+    SP_V9FCMPEQ	= 468,
+    SP_V9FCMPES	= 469,
+    SP_V9FCMPQ	= 470,
+    SP_V9FCMPS	= 471,
+    SP_V9FMOVD_FCC	= 472,
+    SP_V9FMOVQ_FCC	= 473,
+    SP_V9FMOVS_FCC	= 474,
+    SP_V9MOVFCCri	= 475,
+    SP_V9MOVFCCrr	= 476,
+    SP_WRYri	= 477,
+    SP_WRYrr	= 478,
+    SP_XMULX	= 479,
+    SP_XMULXHI	= 480,
+    SP_XNORCCri	= 481,
+    SP_XNORCCrr	= 482,
+    SP_XNORXrr	= 483,
+    SP_XNORri	= 484,
+    SP_XNORrr	= 485,
+    SP_XORCCri	= 486,
+    SP_XORCCrr	= 487,
+    SP_XORXri	= 488,
+    SP_XORXrr	= 489,
+    SP_XORri	= 490,
+    SP_XORrr	= 491,
+    SP_INSTRUCTION_LIST_END = 492
+};
+
+#endif // GET_INSTRINFO_ENUM