DeepSeek on Metal: compile fixes on the 0.2.7 tree (huge pages, wmma include, DeviceProp.integrated, iq256x stubs)

metal/include/strata/gpu/runtime.hpp

@@ -38,6 +38,7 @@ struct DeviceProp {   // the fields the host code reads
     char gcnArchName[256] = {};
     int major = 0, minor = 0, warpSize = 32, multiProcessorCount = 0;
     size_t totalGlobalMem = 0;
+    int integrated = 0;   // the DeepSeek engine reads it (a GPU on the PC's RAM: Strix Halo); 0 here: its rules for that part were not tuned for Apple GPUs
 };
 
 inline constexpr unsigned kHostAllocDefault = 0;

metal/src/engine/stubs_ds4.cpp

@@ -0,0 +1,16 @@
+// metal/src/engine/stubs_ds4.cpp - CPU-kernel entry points the DeepSeek engine (strata_ds4) references that have no Apple
+// implementation.  strata::ds4::gguf::dots() asks iq256x_supported() before it uses iq256x_rows(); on arm64 the answer is no and the
+// CPU lane keeps ggml-cpu's rows, which have their own NEON kernels.
+#include "strata/kernels/cpu/iq_avx2.hpp"
+
+#include <cstdlib>
+
+namespace strata::kernels::cpu {
+
+bool iq256x_supported(int) noexcept { return false; }
+
+void iq256x_rows(int, const uint8_t*, size_t, int, const void* const*, int, float* const*, int, int) {
+    std::abort();   // unreachable: iq256x_supported() is false here, and callers check it
+}
+
+}   // namespace strata::kernels::cpu

src/dsv41/ds4_gg_cpu.cpp

@@ -169,7 +169,7 @@ static int amd_family() {
         if (!__get_cpuid(1, &a, &b, &c, &d)) return 0;
         const unsigned eax = a;
 #else
-        return 0;
+        const unsigned eax = 0;   // (not an x86 host: no family)
 #endif
         const unsigned base = (eax >> 8) & 0xF;
         return (int) (base == 0xF ? base + ((eax >> 20) & 0xFF) : base);

src/dsv41/ds4_model.cu

@@ -31,7 +31,9 @@
 #include "strata/kernels/f16_bits.hpp"
 #include "strata/dsv41/moe_win.hpp"
 #include "strata/dsv41/sampler.hpp"
+#if defined(STRATA_USE_HIP)
 #include "wmma_gemm.h"   // strata_pf_gemm_f16_ld: the RDNA3 WMMA dense GEMM (gemm() prefers it over hipBLAS on gfx11; -Isrc/prefill)
+#endif
 
 #include <cublas_v2.h>
 #include <cuda_runtime.h>
@@ -6354,7 +6356,6 @@ struct Model::Impl {
         ++n_calls;
         double tp0 = now_ms();
         const float lim = g.lim;
-        const double tp0 = now_ms();
         {   // (os::prefetch_cold, as above: the resident ones are left alone - on Windows the hint walks every page of a
             // range, ~0.13 ms an IQ2_XXS expert, on the lane's critical path before the first entry computes.
             // off by default (the mmap path, owner PC: not faster in every pair); DS4_IQ_PF_COLD=1 turns it on)

src/dsv41/ds4_os.hpp

@@ -434,7 +434,7 @@ inline uint64_t huge_free_bytes() {
 /// or the kernel cannot.  (Unlike THP, a pin of this memory keeps 2 MB pages: a DMA from it does not need 4 KB
 /// translations, which is what DS4_COPY_PIN's registered arena wanted.)
 inline void* huge_alloc(size_t bytes, size_t* got = nullptr) {
-#if defined(_WIN32)
+#if defined(_WIN32) || defined(__APPLE__)   // (macOS has no MAP_HUGETLB)
     (void) bytes, (void) got;
     return nullptr;
 #else

src/kernels/cpu/portable.cpp

@@ -122,6 +122,10 @@ bool iq512x_supported(int) noexcept { return false; }
 void iq512x_rows(int, const uint8_t*, size_t, int, const void* const*, int, float* const*, int, int) {
     unsupported("the AVX-512 exact i-quant kernel");
 }
+bool iq256x_supported(int) noexcept { return false; }   // (the DeepSeek CPU lane's multi-token rows: ggml-cpu's NEON dots instead)
+void iq256x_rows(int, const uint8_t*, size_t, int, const void* const*, int, float* const*, int, int) {
+    unsupported("the AVX2 multi-token i-quant rows");
+}
 int iq256_variant() noexcept { return 0; }
 int iq256_variants() noexcept { return 0; }
 void iq256_gu_rows_v(int, int, const uint8_t*, size_t, size_t, int, const void* const*, int, float* const*, int, int) {