Engine: no Windows 2560 MiB reserve floor on an integrated (UMA) HIP device (G16)

On Windows HIP, an auto expert cache with no --vram-reserve-mib kept a floor of 2560 MiB free on any card of 15 GiB or more (#1376, made for a 20 GB discrete
card that paged). On a Strix Halo that room is not free: the RAM budget's page-locked complement takes it straight back (cache + complement 71.72 GiB at 2560 and
71.73 GiB at 700 on UD-Q4_K_XL), so the prompt path's own buffers found 0 MiB and the engine stepped its chunk down 16384 ... 1024 for ever; strata launch of a
UD-Q4_K_XL config with no reserve (pictures off, or a model with no picture reader) never started.

The floor now goes through strata::core::wddm_auto_reserve_mib(integrated, total, current, floor): a discrete card of 15 GiB or more still gets 2560, an
integrated GPU (the device property the UMA sizing already reads) keeps the engine's default 700. Discrete cards, Linux and every config that passes
--vram-reserve-mib are unchanged (the block is under _WIN32 + STRATA_USE_HIP and behind !vram_reserve_given). Unit test in uma_cache_test.

CUDA sm_120 sm build (vendored ggml), base vs change from the same path: the binaries are bit-identical (sha256 2b603395...).
Strix (gfx1151, public-0.2.12-style config with no reserve) with the new engine: starts in 77 s and answers 3 chats; the old engine never started it.

include/strata/core/uma_cache.hpp

@@ -31,4 +31,15 @@ inline uint64_t uma_cache_room_bytes(uint64_t available, uint64_t reserve) {
     return available > reserve ? available - reserve : 0;
 }
 
+/// G16 (Q4-P8, 2026-11-08): the reserve the auto cache keeps free on Windows HIP when none was given.  A DISCRETE card of 15 GiB or more gets the floor (#1376: a
+/// 20 GB card ended with 323 MiB free at the default 700 and Windows paged); an INTEGRATED GPU (the device property `integrated`, the same test the UMA sizing above
+/// uses) does not: its pool is the RAM, the room the floor frees is taken straight back by the RAM budget's page-locked complement, and on a Strix Halo with
+/// UD-Q4_K_XL the prompt path's own buffers then found 0 MiB and the engine stepped its chunk down for ever.  `current_mib` is what the engine would use without
+/// the floor (the default 700); a reserve given on the command line never comes here.
+inline int wddm_auto_reserve_mib(bool integrated, uint64_t total_bytes, int current_mib, int floor_mib = 2560) {
+    constexpr uint64_t GiB = 1ull << 30;
+    if (integrated || total_bytes < 15 * GiB || current_mib >= floor_mib) return current_mib;
+    return floor_mib;
+}
+
 }  // namespace strata::core

src/core/uma_cache_test.cpp

@@ -27,6 +27,16 @@ int main() {
     CHECK(uma_cache_room_bytes(10 * GiB, 10 * GiB) == 0);
     CHECK(uma_cache_room_bytes(5 * GiB, 10 * GiB) == 0);
     CHECK(uma_cache_room_bytes(5 * GiB, 0) == 5 * GiB);
+    // G16: the Windows HIP floor of the auto cache's reserve is for a discrete card of 15 GiB or more only
+    CHECK(wddm_auto_reserve_mib(false, 20 * GiB, 700) == 2560);              // a 20 GB discrete card (#1376): the floor
+    CHECK(wddm_auto_reserve_mib(false, 15 * GiB, 700) == 2560);              // 15 GiB: the floor (#1709)
+    CHECK(wddm_auto_reserve_mib(false, 16 * GiB - 1, 700) == 2560);          // a 16 GB card reports just under 16
+    CHECK(wddm_auto_reserve_mib(false, 8 * GiB, 700) == 700);                // a smaller card keeps its own sizing
+    CHECK(wddm_auto_reserve_mib(false, 15 * GiB - 1, 700) == 700);
+    CHECK(wddm_auto_reserve_mib(true, 94027ull << 20, 700) == 700);          // a Strix Halo (94,027 MiB pool): no floor
+    CHECK(wddm_auto_reserve_mib(true, 20 * GiB, 700) == 700);                // integrated wins whatever the size
+    CHECK(wddm_auto_reserve_mib(false, 20 * GiB, 3000) == 3000);             // a larger reserve is never lowered
+    CHECK(wddm_auto_reserve_mib(true, 94027ull << 20, 3000) == 3000);
     if (fails == 0) std::printf("uma_cache_test: all checks passed\n");
     return fails == 0 ? 0 : 1;
 }

src/program/generate.cpp

@@ -7953,7 +7953,13 @@ int main(int argc, char** argv) {
 #if defined(_WIN32) && defined(STRATA_USE_HIP)
             size_t fb_now = 0, tb_now = 0;
             // #1709: a 16 GB card (RX 9070 XT, 7800 XT) reports 15.9 GiB, just under 16: the floor is for 15 GiB and up
-            if (cudaMemGetInfo(&fb_now, &tb_now) == cudaSuccess && tb_now >= (15ull << 30)) {
+            // G16: and for a DISCRETE card only.  An integrated GPU (the device property, as the UMA sizing above reads it) shares the RAM with the budget's
+            // page-locked complement, which takes the freed room straight back: on a Strix Halo the floor left UD-Q4_K_XL no room for the prompt path (wddm_auto_reserve_mib)
+            cudaDeviceProp fl_prop{};
+            int fl_dev = 0;
+            const bool fl_integrated = cudaGetDevice(&fl_dev) == cudaSuccess && cudaGetDeviceProperties(&fl_prop, fl_dev) == cudaSuccess && fl_prop.integrated != 0;
+            if (cudaMemGetInfo(&fb_now, &tb_now) == cudaSuccess &&
+                strata::core::wddm_auto_reserve_mib(fl_integrated, (uint64_t) tb_now, o.vram_reserve_mib, kWddmAutoReserveMib) == kWddmAutoReserveMib) {
                 std::fprintf(stderr, "strata generate: expert cache auto: Windows keeps %d MiB free after the cache on a card "
                                      "this size (the default %d MiB left 323 MiB on a 20 GB card and Windows paged, #1376); "
                                      "--vram-reserve-mib N sets it\n", kWddmAutoReserveMib, o.vram_reserve_mib);