Niko1221 41717f29c1 qsa_real_shapes() takes the compiled geometry; gdn_parity's prefill cases and native_grouped_parity follow the build's shape ...

qsa_real_shapes() (24 / 2 / 256 / 64, indexer 4 x 128) is the shape every QSA parity program builds from; it now reads kCompiledGeometry (the same values for the default build), so the
q4_* builds' kv_stream / qsa_prompt_attn / snapshot checks run at their own head counts instead of being refused.  gdn_parity's prefill cases used 48 value heads; native_grouped_parity's
compiled-shape loop no longer asks the K-quant checker for an IQ4_NL down.

2026-11-08 07:00:42 +01:00

..

cpu

geometry: attention G, fused_gr tiles and fast up for hc_lr 256-512, top-k from the geometry in native_moe, native activation buffers follow n_embd/n_ff, PLE hash constants read from the model file

2026-11-07 21:21:16 +01:00

bf16_bits.hpp

bf16: a NaN stays a quiet NaN in f32 -> bf16, as in ggml

2026-09-30 11:45:44 +02:00

bf16_gemv.hpp

V100: operator fusions for the decode GEMV / MoE paths, bitwise

2026-10-14 07:05:13 +02:00

cvec.hpp

prefill: STRATA_CVEC_FUSE=1 - a steered layer's write, control vector and next norm in one pass over R, bitwise

2026-10-04 04:50:20 +02:00

dequant_bf16.hpp

dequant: a thread per 8 values for Q4_K / Q5_K / Q6_K / IQ4_XS, sm_61's default (bitwise; Q6_K 7.2 -> 0.33 ms on a Tesla P40)

2026-10-13 04:12:24 +02:00

dequant_s2.hpp

Strata: Qwen3.8-Flash-Next on a 12-24 GB NVIDIA GPU + 64 GB RAM, one-click install

2026-09-24 18:42:20 +02:00

dflash2.hpp

Merge f-0291-df2-comm (Q4_0 selector codebooks in the select kernel and the packer, STRATA_DF2_HEAD=native) into rc1; the engine says 'selector codebooks: Q4_0 rows' when it loads such a pack

2026-11-02 11:38:53 +01:00

dp4a.hpp

tools: sm60_dp4a_check (STRATA_DP4A vs byte reference, bit-exact + timing)

2026-10-06 14:58:47 +02:00

elementwise.hpp

gfx12 decode: the split HC norm from registers (-1.8 us a read), the host-flag waits folded into the copies that follow them (-2 nodes a layer); STRATA_VERIFY_NODES lists the window graph on HIP; the stage profile splits the FFN-side HC read; STRATA_DUMMY_NODES=k measures what an empty graph node costs

2026-10-11 04:04:07 +02:00

f16_bits.hpp

AMD HIP backend for gfx1100 (PR #121, squashed onto its 0.1.21 base)

2026-09-29 14:33:45 +02:00

fuse_decode.hpp

V100 fusions (#1097) behind STRATA_FUSE_DECODE=1; pf_wmma opt-in and only when every visible card is cc 7+; WMMA path skips NVFP4 layers; docs

2026-10-15 08:39:46 +02:00

fused_gdn.hpp

Qwen3.6 T1: SiLU-gated GDN step and a 256/8 router in the native kernels; q36ref runs on them

2026-10-12 21:11:03 +02:00

fused_gr.hpp

gr_v3_screen: print registers, local memory, smem and resident blocks of the v3 kernels (--resources)

2026-10-31 17:52:33 +01:00

gdn.hpp

Strata: Qwen3.8-Flash-Next on a 12-24 GB NVIDIA GPU + 64 GB RAM, one-click install

2026-09-24 18:42:20 +02:00

gfx_arch.hpp

gfx1103 (Radeon 780M) joins the gfx11 WMMA kernels: decode x1.53, same answers

2026-10-12 07:40:49 +02:00

gr.hpp

verify window: PDL on sm_90+, mixer graph branches, batched Q4_0 query path, PLE post-ops in one pass (all opt-in)

2026-10-07 04:08:11 +02:00

iq_kernels.hpp

RDNA4 routed-expert, draft, shared-expert and head kernels (PR 3259 and PR 3264, author bsorensen110)

2026-10-31 23:35:50 +01:00

kv_q4.hpp

perf(kv): batched K/V and indexer append for the verify window, the commit graph and the MTP catch-up (#783 PR-d)

2026-10-06 00:51:29 +02:00

kv_q8.hpp

verify: fewer launches around the shared expert and the KV append, bitwise (opt-in STRATA_LFUSE=1)

2026-10-04 00:41:01 +00:00

kv_stream.hpp

kv: --kv k8v4 streams with --kv-resident

2026-10-05 19:57:34 +02:00

mrope.hpp

gfx906 build (PR #638 follow-up): mrope.hpp's HIP include only in the gfx906 build; tests.list dropped

2026-10-03 23:33:16 +02:00

native_flash_attn.hpp

Strata: Qwen3.8-Flash-Next on a 12-24 GB NVIDIA GPU + 64 GB RAM, one-click install

2026-09-24 18:42:20 +02:00

native_gdn_preprocess.hpp

Strata: Qwen3.8-Flash-Next on a 12-24 GB NVIDIA GPU + 64 GB RAM, one-click install

2026-09-24 18:42:20 +02:00

native_gdn.hpp

Strata: Qwen3.8-Flash-Next on a 12-24 GB NVIDIA GPU + 64 GB RAM, one-click install

2026-09-24 18:42:20 +02:00

native_gr_norm.hpp

perf(gr): multi-token hyper-connection read/write, exact-T GR and BF16 projections (#783 PR-g)

2026-10-06 00:51:30 +02:00

native_gr_postops.hpp

verify window: PDL on sm_90+, mixer graph branches, batched Q4_0 query path, PLE post-ops in one pass (all opt-in)

2026-10-07 04:08:11 +02:00

native_mmvq.hpp

Merge f-027-gh-eng-n (#3779 sm_80 tuning: wide dequant, MMVQ-IL sm_80 tables and the opt-ins)

2026-10-27 00:57:59 +01:00

native_moe.hpp

gfx12 decode: the HC up kernel owns whole q8_1 groups and writes its consumer's image itself (STRATA_QFUSE_HC, no atomics), moe_hit_add folded into the combine (STRATA_FUSE_HITS); STRATA_FUSE_CONVAB (conv + a/b in one launch, opt-in, measured slower)

2026-10-11 05:59:48 +02:00

native_ple_postops.hpp

verify window: PDL on sm_90+, mixer graph branches, batched Q4_0 query path, PLE post-ops in one pass (all opt-in)

2026-10-07 04:08:11 +02:00

native_qsa_indexer.hpp

Commit graph: every GDN layer's conv history + state, and every QSA layer's tail restore + indexer append, in one launch each (STRATA_COMMIT_BATCH, default on; =0 keeps the per-layer loop)

2026-10-13 01:24:55 +02:00

native_qsa_score.hpp

Strata: Qwen3.8-Flash-Next on a 12-24 GB NVIDIA GPU + 64 GB RAM, one-click install

2026-09-24 18:42:20 +02:00

native_qsa.hpp

Speculation: --lookup-chain (prompt lookup chained after the MTP drafts), --mtp-hnorm stream, draft sources

2026-10-03 03:17:34 +00:00

native_rope.hpp

perf(rope): fused per-head RMSNorm + RoPE for the verify window and the MTP drafter, off on HIP (#783 PR-f)

2026-10-06 00:51:29 +02:00

native_router.hpp

Qwen3.6 T1: SiLU-gated GDN step and a 256/8 router in the native kernels; q36ref runs on them

2026-10-12 21:11:03 +02:00

ngram.hpp

geometry: attention G, fused_gr tiles and fast up for hc_lr 256-512, top-k from the geometry in native_moe, native activation buffers follow n_embd/n_ff, PLE hash constants read from the model file

2026-11-07 21:21:16 +01:00

pdl.hpp

Dispatch counters: which kernel path a run really took (dense MMVQ by type/shape/rows, grouped experts and gate/up form, HC read form, window graph kind, layer paths, PDL edges, head), written as JSON at exit with STRATA_DISPATCH_REPORT

2026-10-31 15:03:07 +01:00

ple.hpp

Prefill PLE: opt-in STRATA_PLE_COMPACT=1 uploads the raw IQ4_NL rows and dequantizes them on the device (#3779, #3712)

2026-10-26 20:40:20 +01:00

q8_1_finite.hpp

QFUSE: the fused q8_1 producers divide the way the separate quantiser does; they gave a different code at about one element in a million (#3948)

2026-10-27 02:02:46 +01:00

qsa_decode_attn.hpp

Merge perf-PR group batch (f-145-pp-batch)

2026-10-16 10:49:15 +02:00

qsa_pattn.hpp

qsa_pattn: sm_6x prompt attention without partials, opt-in STRATA_PATTN_SM60=1 (#3943)

2026-10-26 19:24:50 +01:00

qsa_prompt_attn.hpp

gfx12 prompt staging ring (a1e6ef324): only on a gfx12 card. The branch was keyed on the matrix-core attention being active, which the Strix Halo (gfx1151) also has on by default on Windows, so it took the 256 / 192 slot ring that was measured on an R9700 only. gfx1151 keeps the 96-slot ring of 0.2.10; gfx12 is unchanged.

2026-11-03 16:13:46 +01:00

qsa_select.hpp

Exact two-pass QSA prompt selection (opt-in STRATA_SELECT_TWO_PASS=1)

2026-11-06 15:47:43 +01:00

qsa_two_pass_status.hpp

Exact two-pass QSA prompt selection (opt-in STRATA_SELECT_TWO_PASS=1)

2026-11-06 15:47:43 +01:00

qsa_two_pass.hpp

Exact two-pass QSA prompt selection (opt-in STRATA_SELECT_TWO_PASS=1)

2026-11-06 15:47:43 +01:00

qsa.hpp

qsa_real_shapes() takes the compiled geometry; gdn_parity's prefill cases and native_grouped_parity follow the build's shape

2026-11-08 07:00:42 +01:00

quantize_act_dev.cuh

V100: operator fusions for the decode GEMV / MoE paths, bitwise

2026-10-14 07:05:13 +02:00

quantize_act.hpp

V100: operator fusions for the decode GEMV / MoE paths, bitwise

2026-10-14 07:05:13 +02:00

rope_scaling.hpp

rope: one validity rule for the resolved config; none passes the identity constants to every analytic site

2026-09-30 16:44:48 +02:00

rope.hpp

kernels: rope scaling config and the scaled cos/sin table (none/linear/YaRN)

2026-09-30 16:31:31 +02:00

route_prior.hpp

STRATA_ROUTE_PRIOR=lambda: cache-conditioned routing in verify windows (opt-in, changes the output)

2026-10-09 15:23:32 +02:00

router_top10.hpp

HIP (S6): router_top10 without its serial parts on AMD, bitwise the same (default on HIP; STRATA_HIP_ROUTER_OLD=1: old)

2026-10-01 07:24:19 +02:00

s2_expert_grouped.hpp

Verify and batch windows of up to 16 rows: HIP builds default to 16, narrow builds unchanged

2026-10-29 15:06:02 +01:00

s2_gemv_q8.hpp

Strata: Qwen3.8-Flash-Next on a 12-24 GB NVIDIA GPU + 64 GB RAM, one-click install

2026-09-24 18:42:20 +02:00

s2_gemv.hpp

Strata: Qwen3.8-Flash-Next on a 12-24 GB NVIDIA GPU + 64 GB RAM, one-click install

2026-09-24 18:42:20 +02:00

s_gemv.hpp

V100: operator fusions for the decode GEMV / MoE paths, bitwise

2026-10-14 07:05:13 +02:00

s_rowdev.cuh

V100: operator fusions for the decode GEMV / MoE paths, bitwise

2026-10-14 07:05:13 +02:00

sampler.hpp

--parallel slots honour the request's repeat / frequency / presence penalties and logit bias (CUDA, HIP): each penalised slot's reply tail is staged before its window (set_slot_history), the verifier builds the per-row history (slot_penalty_rows: the tail plus the slot's tokens in the window up to the row) and draws the row with sample_tokens; the slot's own logit bias array (set_slot_logit_bias); a logit_bias request is no longer refused with --batch; plain greedy slots keep the window's argmax. CPU test slot_history_test

2026-11-02 07:12:53 +01:00

shared_expert.hpp

Merge the Aurora gfx1151 branch (f-halo-int + HCD_EXACT + the expert bundle) onto 0.1.39

2026-10-05 11:07:15 +02:00

swiglu.cuh

V100: operator fusions for the decode GEMV / MoE paths, bitwise

2026-10-14 07:05:13 +02:00

verify_kernels.hpp

Admit the PCIe share's fetched misses to the GPU cache (opt-in STRATA_ADAPT_FETCH=1|2)

2026-11-06 15:47:43 +01:00

window_limits.hpp

window limit: STRATA_WINDOW_MAX_T=12 as a third value (8, 12, 16)

2026-11-01 03:02:28 +01:00

window_start.hpp

KVA: leave the draft window alone; a per-session cell floor keeps the draft layer off approximated cells

2026-10-26 12:14:30 +01:00