diff --git a/common/emitter/groups.cpp b/common/emitter/groups.cpp
index 013534d5c2..e92857703e 100644
--- a/common/emitter/groups.cpp
+++ b/common/emitter/groups.cpp
@@ -92,12 +92,12 @@ namespace x86Emitter
 		}
 	}
 
-	const xImpl_G1Logic xAND = {{G1Type_AND}, {0x00, 0x54}, {0x66, 0x54}};
-	const xImpl_G1Logic xOR  = {{G1Type_OR}, {0x00, 0x56}, {0x66, 0x56}};
-	const xImpl_G1Logic xXOR = {{G1Type_XOR}, {0x00, 0x57}, {0x66, 0x57}};
+	const xImpl_G1Logic xAND = {{G1Type_AND}, {SIMDInstructionInfo(0x54).commutative()}, {SIMDInstructionInfo(0x54).commutative().p66()}};
+	const xImpl_G1Logic xOR  = {{G1Type_OR},  {SIMDInstructionInfo(0x56).commutative()}, {SIMDInstructionInfo(0x56).commutative().p66()}};
+	const xImpl_G1Logic xXOR = {{G1Type_XOR}, {SIMDInstructionInfo(0x57).commutative()}, {SIMDInstructionInfo(0x57).commutative().p66()}};
 
-	const xImpl_G1Arith xADD = {{G1Type_ADD}, {0x00, 0x58}, {0x66, 0x58}, {0xf3, 0x58}, {0xf2, 0x58}};
-	const xImpl_G1Arith xSUB = {{G1Type_SUB}, {0x00, 0x5c}, {0x66, 0x5c}, {0xf3, 0x5c}, {0xf2, 0x5c}};
+	const xImpl_G1Arith xADD = {{G1Type_ADD}, {SIMDInstructionInfo(0x58).commutative()}, {SIMDInstructionInfo(0x58).commutative().p66()}, {SIMDInstructionInfo(0x58).pf3()}, {SIMDInstructionInfo(0x58).pf2()}};
+	const xImpl_G1Arith xSUB = {{G1Type_SUB}, {SIMDInstructionInfo(0x5c)}, {SIMDInstructionInfo(0x5c).p66()}, {SIMDInstructionInfo(0x5c).pf3()}, {SIMDInstructionInfo(0x5c).pf2()}};
 
 	const xImpl_Group1 xADC = {G1Type_ADC};
 	const xImpl_Group1 xSBB = {G1Type_SBB};
@@ -212,8 +212,8 @@ namespace x86Emitter
 	const xImpl_Group3 xUMUL = {G3Type_MUL};
 	const xImpl_Group3 xUDIV = {G3Type_DIV};
 
-	const xImpl_iDiv xDIV = {{G3Type_iDIV}, {0x00, 0x5e}, {0x66, 0x5e}, {0xf3, 0x5e}, {0xf2, 0x5e}};
-	const xImpl_iMul xMUL = {{G3Type_iMUL}, {0x00, 0x59}, {0x66, 0x59}, {0xf3, 0x59}, {0xf2, 0x59}};
+	const xImpl_iDiv xDIV = {{G3Type_iDIV}, {SIMDInstructionInfo(0x5e)}, {SIMDInstructionInfo(0x5e).p66()}, {SIMDInstructionInfo(0x5e).pf3()}, {SIMDInstructionInfo(0x5e).pf2()}};
+	const xImpl_iMul xMUL = {{G3Type_iMUL}, {SIMDInstructionInfo(0x59).commutative()}, {SIMDInstructionInfo(0x59).commutative().p66()}, {SIMDInstructionInfo(0x59).pf3()}, {SIMDInstructionInfo(0x59).pf2()}};
 
 	// =====================================================================================================
 	//  Group 8 Instructions
diff --git a/common/emitter/implement/group1.h b/common/emitter/implement/group1.h
index 2cb5da6eba..5fbd695ad1 100644
--- a/common/emitter/implement/group1.h
+++ b/common/emitter/implement/group1.h
@@ -39,8 +39,8 @@ namespace x86Emitter
 	//
 	struct xImpl_G1Logic : public xImpl_Group1
 	{
-		xImplSimd_DestRegSSE PS; // packed single precision
-		xImplSimd_DestRegSSE PD; // packed double precision
+		xImplSimd_3Arg PS; // packed single precision
+		xImplSimd_3Arg PD; // packed double precision
 	};
 
 	// ------------------------------------------------------------------------
@@ -48,10 +48,10 @@ namespace x86Emitter
 	//
 	struct xImpl_G1Arith : public xImpl_Group1
 	{
-		xImplSimd_DestRegSSE PS; // packed single precision
-		xImplSimd_DestRegSSE PD; // packed double precision
-		xImplSimd_DestRegSSE SS; // scalar single precision
-		xImplSimd_DestRegSSE SD; // scalar double precision
+		xImplSimd_3Arg PS; // packed single precision
+		xImplSimd_3Arg PD; // packed double precision
+		xImplSimd_3Arg SS; // scalar single precision
+		xImplSimd_3Arg SD; // scalar double precision
 	};
 
 } // End namespace x86Emitter
diff --git a/common/emitter/implement/group3.h b/common/emitter/implement/group3.h
index cb6289dd74..5554aa4600 100644
--- a/common/emitter/implement/group3.h
+++ b/common/emitter/implement/group3.h
@@ -32,10 +32,10 @@ namespace x86Emitter
 	// --------------------------------------------------------------------------------------
 	struct xImpl_iDiv : public xImpl_Group3
 	{
-		const xImplSimd_DestRegSSE PS;
-		const xImplSimd_DestRegSSE PD;
-		const xImplSimd_DestRegSSE SS;
-		const xImplSimd_DestRegSSE SD;
+		const xImplSimd_3Arg PS;
+		const xImplSimd_3Arg PD;
+		const xImplSimd_3Arg SS;
+		const xImplSimd_3Arg SD;
 	};
 
 	// --------------------------------------------------------------------------------------
@@ -58,9 +58,9 @@ namespace x86Emitter
 		void operator()(const xRegister16& to, const xRegister16& from, s16 imm) const;
 		void operator()(const xRegister16& to, const xIndirectVoid& from, s16 imm) const;
 
-		const xImplSimd_DestRegSSE PS;
-		const xImplSimd_DestRegSSE PD;
-		const xImplSimd_DestRegSSE SS;
-		const xImplSimd_DestRegSSE SD;
+		const xImplSimd_3Arg PS;
+		const xImplSimd_3Arg PD;
+		const xImplSimd_3Arg SS;
+		const xImplSimd_3Arg SD;
 	};
 } // namespace x86Emitter
diff --git a/tests/ctest/common/x86emitter/codegen_tests_main.cpp b/tests/ctest/common/x86emitter/codegen_tests_main.cpp
index e295653c45..235a2a5c43 100644
--- a/tests/ctest/common/x86emitter/codegen_tests_main.cpp
+++ b/tests/ctest/common/x86emitter/codegen_tests_main.cpp
@@ -155,6 +155,10 @@ TEST(CodegenTests, SSETest)
 	CODEGEN_TEST(xPXOR(xmm9, xmm4),  "66 44 0f ef cc");
 	CODEGEN_TEST(xPTEST(xmm2, xmm9), "66 41 0f 38 17 d1");
 
+	CODEGEN_TEST(xAND.PS(xmm3, xmm8),  "41 0f 54 d8");
+	CODEGEN_TEST(xOR.PS(xmm5, xmm8),   "41 0f 56 e8");
+	CODEGEN_TEST(xXOR.PS(xmm9, xmm4),  "44 0f 57 cc");
+
 	CODEGEN_TEST(xCVTDQ2PD(xmm0, ptr64[rax]), "f3 0f e6 00");
 	CODEGEN_TEST(xCVTDQ2PS(xmm0, xmm8),       "41 0f 5b c0");
 	CODEGEN_TEST(xCVTPD2DQ(xmm8, ptr128[r8]), "f2 45 0f e6 00");
@@ -217,6 +221,23 @@ TEST(CodegenTests, SSETest)
 	CODEGEN_TEST(xPMUL.LD(xmm1, xmm8),    "66 41 0f 38 40 c8");
 	CODEGEN_TEST(xPMUL.DQ(xmm4, xmm9),    "66 41 0f 38 28 e1");
 
+	CODEGEN_TEST(xADD.SS(xmm1, xmm8),     "f3 41 0f 58 c8");
+	CODEGEN_TEST(xADD.SD(xmm4, xmm7),     "f2 0f 58 e7");
+	CODEGEN_TEST(xADD.PS(xmm2, ptr[rcx]), "0f 58 11");
+	CODEGEN_TEST(xADD.PD(xmm8, xmm2),     "66 44 0f 58 c2");
+	CODEGEN_TEST(xSUB.SS(xmm1, xmm8),     "f3 41 0f 5c c8");
+	CODEGEN_TEST(xSUB.SD(xmm4, xmm7),     "f2 0f 5c e7");
+	CODEGEN_TEST(xSUB.PS(xmm2, ptr[rcx]), "0f 5c 11");
+	CODEGEN_TEST(xSUB.PD(xmm8, xmm2),     "66 44 0f 5c c2");
+	CODEGEN_TEST(xMUL.SS(xmm2, xmm8),     "f3 41 0f 59 d0");
+	CODEGEN_TEST(xMUL.SD(xmm9, ptr[r9]),  "f2 45 0f 59 09");
+	CODEGEN_TEST(xMUL.PS(xmm4, xmm3),     "0f 59 e3");
+	CODEGEN_TEST(xMUL.PD(xmm1, xmm8),     "66 41 0f 59 c8");
+	CODEGEN_TEST(xDIV.SS(xmm2, xmm4),     "f3 0f 5e d4");
+	CODEGEN_TEST(xDIV.SD(xmm1, xmm8),     "f2 41 0f 5e c8");
+	CODEGEN_TEST(xDIV.PS(xmm4, xmm9),     "41 0f 5e e1");
+	CODEGEN_TEST(xDIV.PD(xmm9, xmm2),     "66 44 0f 5e ca");
+
 	CODEGEN_TEST(xRSQRT.PS(xmm0, xmm8),    "41 0f 52 c0");
 	CODEGEN_TEST(xRSQRT.SS(xmm4, ptr[r9]), "f3 41 0f 52 21");
 	CODEGEN_TEST(xRCP.PS(xmm4, ptr[rcx]),  "0f 53 21");
@@ -432,6 +453,10 @@ TEST(CodegenTests, AVXTest)
 	CODEGEN_TEST(xPXOR(xmm9, xmm4),  "c5 31 ef cc");
 	CODEGEN_TEST(xPTEST(xmm2, xmm9), "c4 c2 79 17 d1");
 
+	CODEGEN_TEST(xAND.PS(xmm3, xmm8),  "c5 b8 54 db"); // => andps xmm3, xmm8, xmm3
+	CODEGEN_TEST(xOR.PS(xmm5, xmm8),   "c5 b8 56 ed"); // => orps xmm5, xmm8, xmm5
+	CODEGEN_TEST(xXOR.PS(xmm9, xmm4),  "c5 30 57 cc");
+
 	CODEGEN_TEST(xCVTDQ2PD(xmm0, ptr64[rax]), "c5 fa e6 00");
 	CODEGEN_TEST(xCVTDQ2PS(xmm0, xmm8),       "c4 c1 78 5b c0");
 	CODEGEN_TEST(xCVTPD2DQ(xmm8, ptr128[r8]), "c4 41 7b e6 00");
@@ -494,6 +519,23 @@ TEST(CodegenTests, AVXTest)
 	CODEGEN_TEST(xPMUL.LD(xmm1, xmm8),    "c4 c2 71 40 c8");
 	CODEGEN_TEST(xPMUL.DQ(xmm4, xmm9),    "c4 c2 59 28 e1");
 
+	CODEGEN_TEST(xADD.SS(xmm1, xmm8),     "c4 c1 72 58 c8");
+	CODEGEN_TEST(xADD.SD(xmm4, xmm7),     "c5 db 58 e7");
+	CODEGEN_TEST(xADD.PS(xmm2, ptr[rcx]), "c5 e8 58 11");
+	CODEGEN_TEST(xADD.PD(xmm8, xmm2),     "c5 39 58 c2");
+	CODEGEN_TEST(xSUB.SS(xmm1, xmm8),     "c4 c1 72 5c c8");
+	CODEGEN_TEST(xSUB.SD(xmm4, xmm7),     "c5 db 5c e7");
+	CODEGEN_TEST(xSUB.PS(xmm2, ptr[rcx]), "c5 e8 5c 11");
+	CODEGEN_TEST(xSUB.PD(xmm8, xmm2),     "c5 39 5c c2");
+	CODEGEN_TEST(xMUL.SS(xmm2, xmm8),     "c4 c1 6a 59 d0");
+	CODEGEN_TEST(xMUL.SD(xmm9, ptr[r9]),  "c4 41 33 59 09");
+	CODEGEN_TEST(xMUL.PS(xmm4, xmm3),     "c5 d8 59 e3");
+	CODEGEN_TEST(xMUL.PD(xmm1, xmm8),     "c5 b9 59 c9"); // => vmulpd xmm1, xmm8, xmm1
+	CODEGEN_TEST(xDIV.SS(xmm2, xmm4),     "c5 ea 5e d4");
+	CODEGEN_TEST(xDIV.SD(xmm1, xmm8),     "c4 c1 73 5e c8");
+	CODEGEN_TEST(xDIV.PS(xmm4, xmm9),     "c4 c1 58 5e e1");
+	CODEGEN_TEST(xDIV.PD(xmm9, xmm2),     "c5 31 5e ca");
+
 	CODEGEN_TEST(xRSQRT.PS(xmm0, xmm8),    "c4 c1 78 52 c0");
 	CODEGEN_TEST(xRSQRT.SS(xmm4, ptr[r9]), "c4 c1 5a 52 21");
 	CODEGEN_TEST(xRCP.PS(xmm4, ptr[rcx]),  "c5 f8 53 21");