diff --git a/3rdparty/cpuinfo/CMakeLists.txt b/3rdparty/cpuinfo/CMakeLists.txt index d8d514ad03..0542f3140f 100644 --- a/3rdparty/cpuinfo/CMakeLists.txt +++ b/3rdparty/cpuinfo/CMakeLists.txt @@ -1,4 +1,4 @@ -CMAKE_MINIMUM_REQUIRED(VERSION 3.5 FATAL_ERROR) +CMAKE_MINIMUM_REQUIRED(VERSION 3.18 FATAL_ERROR) # ---[ Setup project PROJECT( @@ -108,7 +108,7 @@ IF(NOT CMAKE_SYSTEM_NAME) "Target operating system is not specified. " "cpuinfo will compile, but cpuinfo_initialize() will always fail.") SET(CPUINFO_SUPPORTED_PLATFORM FALSE) -ELSEIF(NOT CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS|Darwin|Linux|Android|FreeBSD)$") +ELSEIF(NOT CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS|Darwin|Linux|Android|FreeBSD|Emscripten)$") IF(${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.14" AND NOT IS_APPLE_OS) MESSAGE(WARNING "Target operating system \"${CMAKE_SYSTEM_NAME}\" is not supported in cpuinfo. " @@ -184,10 +184,11 @@ IF(CPUINFO_SUPPORTED_PLATFORM) ELSEIF(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") LIST(APPEND CPUINFO_SRCS src/x86/freebsd/init.c) ENDIF() - ELSEIF(CMAKE_SYSTEM_NAME MATCHES "^Windows" AND CPUINFO_TARGET_PROCESSOR MATCHES "^(ARM64|arm64)$") + ELSEIF(CMAKE_SYSTEM_NAME MATCHES "^Windows" AND CPUINFO_TARGET_PROCESSOR MATCHES "^(ARM64|arm64|aarch64)$") LIST(APPEND CPUINFO_SRCS src/arm/windows/init-by-logical-sys-info.c - src/arm/windows/init.c) + src/arm/windows/init.c + src/arm/uarch.c) ELSEIF(CPUINFO_TARGET_PROCESSOR MATCHES "^(armv[5-8].*|aarch64|arm64.*)$" OR IOS_ARCH MATCHES "^(armv7.*|arm64.*)$") LIST(APPEND CPUINFO_SRCS src/arm/uarch.c @@ -218,7 +219,7 @@ IF(CPUINFO_SUPPORTED_PLATFORM) ELSEIF(CPUINFO_TARGET_PROCESSOR MATCHES "^(riscv(32|64))$") LIST(APPEND CPUINFO_SRCS src/riscv/uarch.c) - IF(CMAKE_SYSTEM_NAME STREQUAL "Linux") + IF(CMAKE_SYSTEM_NAME STREQUAL "Linux" OR CMAKE_SYSTEM_NAME STREQUAL "Android") LIST(APPEND CPUINFO_SRCS src/riscv/linux/init.c src/riscv/linux/riscv-hw.c @@ -747,6 +748,11 @@ IF(CPUINFO_SUPPORTED_PLATFORM AND CPUINFO_BUILD_MOCK_TESTS) TARGET_LINK_LIBRARIES(pixel-2-xl-test PRIVATE cpuinfo_mock gtest) ADD_TEST(NAME pixel-2-xl-test COMMAND pixel-2-xl-test) + ADD_EXECUTABLE(pixel-8-test test/mock/pixel-8.cc) + TARGET_INCLUDE_DIRECTORIES(pixel-8-test BEFORE PRIVATE test/mock) + TARGET_LINK_LIBRARIES(pixel-8-test PRIVATE cpuinfo_mock gtest) + ADD_TEST(NAME pixel-8-test COMMAND pixel-8-test) + ADD_EXECUTABLE(xiaomi-mi-5c-test test/mock/xiaomi-mi-5c.cc) TARGET_INCLUDE_DIRECTORIES(xiaomi-mi-5c-test BEFORE PRIVATE test/mock) TARGET_LINK_LIBRARIES(xiaomi-mi-5c-test PRIVATE cpuinfo_mock gtest) diff --git a/3rdparty/cpuinfo/cmake/DownloadGoogleBenchmark.cmake b/3rdparty/cpuinfo/cmake/DownloadGoogleBenchmark.cmake index fd99d0ef81..94364df4b1 100644 --- a/3rdparty/cpuinfo/cmake/DownloadGoogleBenchmark.cmake +++ b/3rdparty/cpuinfo/cmake/DownloadGoogleBenchmark.cmake @@ -1,11 +1,11 @@ -CMAKE_MINIMUM_REQUIRED(VERSION 2.8.12 FATAL_ERROR) +CMAKE_MINIMUM_REQUIRED(VERSION 3.18 FATAL_ERROR) PROJECT(googlebenchmark-download NONE) INCLUDE(ExternalProject) ExternalProject_Add(googlebenchmark - URL https://github.com/google/benchmark/archive/v1.6.1.zip - URL_HASH SHA256=367e963b8620080aff8c831e24751852cffd1f74ea40f25d9cc1b667a9dd5e45 + URL https://github.com/google/benchmark/archive/refs/tags/v1.9.4.tar.gz + URL_HASH SHA256=b334658edd35efcf06a99d9be21e4e93e092bd5f95074c1673d5c8705d95c104 SOURCE_DIR "${CONFU_DEPENDENCIES_SOURCE_DIR}/googlebenchmark" BINARY_DIR "${CONFU_DEPENDENCIES_BINARY_DIR}/googlebenchmark" CONFIGURE_COMMAND "" diff --git a/3rdparty/cpuinfo/cmake/DownloadGoogleTest.cmake b/3rdparty/cpuinfo/cmake/DownloadGoogleTest.cmake index c58fd0985c..22f7fe4023 100644 --- a/3rdparty/cpuinfo/cmake/DownloadGoogleTest.cmake +++ b/3rdparty/cpuinfo/cmake/DownloadGoogleTest.cmake @@ -1,11 +1,11 @@ -CMAKE_MINIMUM_REQUIRED(VERSION 2.8.12 FATAL_ERROR) +CMAKE_MINIMUM_REQUIRED(VERSION 3.18 FATAL_ERROR) PROJECT(googletest-download NONE) INCLUDE(ExternalProject) ExternalProject_Add(googletest - URL https://github.com/google/googletest/archive/release-1.11.0.zip - URL_HASH SHA256=353571c2440176ded91c2de6d6cd88ddd41401d14692ec1f99e35d013feda55a + URL https://github.com/google/googletest/archive/refs/tags/v1.17.0.zip + URL_HASH SHA256=40d4ec942217dcc84a9ebe2a68584ada7d4a33a8ee958755763278ea1c5e18ff SOURCE_DIR "${CONFU_DEPENDENCIES_SOURCE_DIR}/googletest" BINARY_DIR "${CONFU_DEPENDENCIES_BINARY_DIR}/googletest" CONFIGURE_COMMAND "" diff --git a/3rdparty/cpuinfo/include/cpuinfo.h b/3rdparty/cpuinfo/include/cpuinfo.h index 891416abda..9659f4d7ee 100644 --- a/3rdparty/cpuinfo/include/cpuinfo.h +++ b/3rdparty/cpuinfo/include/cpuinfo.h @@ -373,10 +373,14 @@ enum cpuinfo_uarch { cpuinfo_uarch_goldmont = 0x00100404, /** Intel Goldmont Plus microarchitecture (Gemini Lake). */ cpuinfo_uarch_goldmont_plus = 0x00100405, - /** Intel Gracemont microarchitecture (Twin Lake). */ - cpuinfo_uarch_gracemont = 0x00100406, + /** Intel Airmont microarchitecture (10 nm out-of-order Atom). */ + cpuinfo_uarch_tremont = 0x00100406, + /** Intel Gracemont microarchitecture (AlderLake N). */ + cpuinfo_uarch_gracemont = 0x00100407, /** Intel Crestmont microarchitecture (Sierra Forest). */ - cpuinfo_uarch_crestmont = 0x00100407, + cpuinfo_uarch_crestmont = 0x00100408, + /** Intel Darkmont microarchitecture (e-core used in Clearwater Forest). */ + cpuinfo_uarch_darkmont = 0x00100409, /** Intel Knights Ferry HPC boards. */ cpuinfo_uarch_knights_ferry = 0x00100500, @@ -388,8 +392,6 @@ enum cpuinfo_uarch { cpuinfo_uarch_knights_hill = 0x00100503, /** Intel Knights Mill Xeon Phi. */ cpuinfo_uarch_knights_mill = 0x00100504, - /** Intel Darkmont microarchitecture (e-core used in Clearwater Forest). */ - cpuinfo_uarch_darkmont = 0x00100505, /** Intel/Marvell XScale series. */ cpuinfo_uarch_xscale = 0x00100600, @@ -508,6 +510,8 @@ enum cpuinfo_uarch { cpuinfo_uarch_cortex_x3 = 0x00300503, /** ARM Cortex-X4. */ cpuinfo_uarch_cortex_x4 = 0x00300504, + /** ARM Cortex-X925. */ + cpuinfo_uarch_cortex_x925 = 0x00300505, /** ARM Cortex-A510. */ cpuinfo_uarch_cortex_a510 = 0x00300551, @@ -519,6 +523,8 @@ enum cpuinfo_uarch { cpuinfo_uarch_cortex_a715 = 0x00300572, /** ARM Cortex-A720. */ cpuinfo_uarch_cortex_a720 = 0x00300573, + /** ARM Cortex-A725. */ + cpuinfo_uarch_cortex_a725 = 0x00300574, /** Qualcomm Scorpion. */ cpuinfo_uarch_scorpion = 0x00400100, @@ -730,7 +736,7 @@ struct cpuinfo_cluster { uint64_t frequency; }; -#define CPUINFO_PACKAGE_NAME_MAX 48 +#define CPUINFO_PACKAGE_NAME_MAX 64 struct cpuinfo_package { /** SoC or processor chip model name */ diff --git a/3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c b/3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c index d87a964a6b..29663a70cc 100644 --- a/3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c +++ b/3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c @@ -149,8 +149,6 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc T310"); } else if (chipset->series == cpuinfo_arm_chipset_series_unisoc_ums && chipset->model == 312) { cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc UMS312"); - } else if (chipset->vendor == cpuinfo_arm_chipset_vendor_unknown) { - cpuinfo_log_warning("VDOT instructions disabled: unknown chipset"); } else { switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case UINT32_C(0x4100D0B0): /* Cortex-A76 */ diff --git a/3rdparty/cpuinfo/src/arm/linux/chipset.c b/3rdparty/cpuinfo/src/arm/linux/chipset.c index c4977c3888..993a9aefa3 100644 --- a/3rdparty/cpuinfo/src/arm/linux/chipset.c +++ b/3rdparty/cpuinfo/src/arm/linux/chipset.c @@ -468,6 +468,56 @@ static bool match_universal(const char* start, const char* end, struct cpuinfo_a return true; } +/** + * Tries to match /s5e\d{4}$/ signature for Samsung Exynos chipsets. + * If match successful, extracts model information into \p chipset argument. + * + * @param start - start of the platform identifier (ro.product.board or + * ro.board.platform) to match. + * @param end - end of the platform identifier (ro.product.board or + * ro.board.platform) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. + * + * @returns true if signature matched, false otherwise. + */ +static bool match_s5e(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 7 symbols: "s5e" (3 symbols) + 4-digit model number */ + if (start + 7 != end) { + return false; + } + + /* Check that string starts with "s5e" */ + if (start[0] != 's') { + return false; + } + + /* Load next 2 bytes as little endian 16-bit word */ + const uint16_t expected_5e = load_u16le(start + 1); + if (expected_5e != UINT16_C(0x6535) /* "e5" = reverse("5e") */) { + return false; + } + + /* Check and parse 4-digit model number */ + uint32_t model = 0; + for (uint32_t i = 3; i < 7; i++) { + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; + if (digit >= 10) { + /* Not really a digit */ + return false; + } + model = model * 10 + digit; + } + + /* Return parsed chipset. */ + *chipset = (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_samsung, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = model, + }; + return true; +} + /** * Compares, case insensitively, a string to known values "SMDK4210" and * "SMDK4x12" for Samsung Exynos chipsets. If platform identifier matches one of @@ -903,7 +953,7 @@ static bool match_sc(const char* start, const char* end, struct cpuinfo_arm_chip } /** - * Tries to match, case-sentitively, /Unisoc T\d{3,4}/ signature for Unisoc T + * Tries to match, case-sentitively, /Unisoc T\d{3,4}/ or /UNISOC T\d{3,4}/ signature for Unisoc T * chipset. If match successful, extracts model information into \p chipset * argument. * @@ -917,7 +967,7 @@ static bool match_sc(const char* start, const char* end, struct cpuinfo_arm_chip * @returns true if signature matched, false otherwise. */ static bool match_t(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { - /* Expect 11-12 symbols: "Unisoc T" (8 symbols) + 3-4-digit model number + /* Expect 11-12 symbols: "Unisoc T" / "UNISOC T" (8 symbols) + 3-4-digit model number */ const size_t length = end - start; switch (length) { @@ -928,16 +978,18 @@ static bool match_t(const char* start, const char* end, struct cpuinfo_arm_chips return false; } - /* Check that string starts with "Unisoc T". The first four characters + /* Check that string starts with "Unisoc T" or "UNISOC T". The first four characters * are loaded as 32-bit little endian word */ const uint32_t expected_unis = load_u32le(start); - if (expected_unis != UINT32_C(0x73696E55) /* "sinU" = reverse("Unis") */) { + if (expected_unis != UINT32_C(0x73696E55) /* "sinU" = reverse("Unis") */ && + expected_unis != UINT32_C(0x53494E55) /* "SINU" = reverse("UNIS") */) { return false; } /* The next four characters are loaded as 32-bit little endian word */ const uint32_t expected_oc_t = load_u32le(start + 4); - if (expected_oc_t != UINT32_C(0x5420636F) /* "T co" = reverse("oc T") */) { + if (expected_oc_t != UINT32_C(0x5420636F) /* "T co" = reverse("oc T") */ && + expected_oc_t != UINT32_C(0x5420434F) /* "T CO" = reverse("OC T") */) { return false; } @@ -2837,6 +2889,15 @@ struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_bo return chipset; } + /* Check s5eXXXX (Samsung Exynos) signature */ + if (match_s5e(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched S5E (Samsung Exynos) signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } + #if CPUINFO_ARCH_ARM /* Check SMDK (Samsung Exynos) signature */ if (match_and_parse_smdk(board, board_end, cores, &chipset)) { @@ -3949,6 +4010,20 @@ static inline struct cpuinfo_arm_chipset disambiguate_spreadtrum_chipset( return *ro_board_platform_chipset; } +static enum cpuinfo_arm_chipset_vendor disambiguate_chipset_vendor( + enum cpuinfo_arm_chipset_vendor vendor_a, + enum cpuinfo_arm_chipset_vendor vendor_b) { + /* Some UNISOC-based platforms reporting conflicting vendor names depending + * on the source. For phones that report both UNISOC and Spreadtrum, treat it + * as UNISOC. */ + if ((vendor_a == cpuinfo_arm_chipset_vendor_unisoc && vendor_b == cpuinfo_arm_chipset_vendor_spreadtrum) || + (vendor_a == cpuinfo_arm_chipset_vendor_spreadtrum && vendor_b == cpuinfo_arm_chipset_vendor_unisoc)) { + return cpuinfo_arm_chipset_vendor_unisoc; + } + + return cpuinfo_arm_chipset_vendor_unknown; +} + /* * Decodes chipset name from Android system properties: * - /proc/cpuinfo Hardware string @@ -4009,10 +4084,19 @@ struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( } else if (vendor != decoded_vendor) { /* Parsing different system properties produces * different chipset vendors. This situation is - * rare. */ - cpuinfo_log_error( - "chipset detection failed: different chipset vendors reported in different system properties"); - goto finish; + * rare. Try to disambiguate for known cases, + * otherwise treat as unknown. */ + + enum cpuinfo_arm_chipset_vendor disambiguated_vendor = + disambiguate_chipset_vendor(vendor, decoded_vendor); + + if (disambiguated_vendor != cpuinfo_arm_chipset_vendor_unknown) { + vendor = disambiguated_vendor; + } else { + cpuinfo_log_error( + "chipset detection failed: different chipset vendors reported in different system properties"); + goto finish; + } } } } diff --git a/3rdparty/cpuinfo/src/arm/uarch.c b/3rdparty/cpuinfo/src/arm/uarch.c index 9679f5004e..38c2abac3d 100644 --- a/3rdparty/cpuinfo/src/arm/uarch.c +++ b/3rdparty/cpuinfo/src/arm/uarch.c @@ -125,6 +125,18 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD4F: /* Neoverse V2 */ *uarch = cpuinfo_uarch_neoverse_v2; break; + case 0xD81: /* Cortex-A720 */ + *uarch = cpuinfo_uarch_cortex_a720; + break; + case 0xD82: /* Cortex-X4 */ + *uarch = cpuinfo_uarch_cortex_x4; + break; + case 0xD85: /* Cortex-X925 */ + *uarch = cpuinfo_uarch_cortex_x925; + break; + case 0xD87: /* Cortex-A725 */ + *uarch = cpuinfo_uarch_cortex_a725; + break; default: switch (midr_get_part(midr) >> 8) { #if CPUINFO_ARCH_ARM diff --git a/3rdparty/cpuinfo/src/arm/windows/init-by-logical-sys-info.c b/3rdparty/cpuinfo/src/arm/windows/init-by-logical-sys-info.c index 32c9b54683..ff6d991aad 100644 --- a/3rdparty/cpuinfo/src/arm/windows/init-by-logical-sys-info.c +++ b/3rdparty/cpuinfo/src/arm/windows/init-by-logical-sys-info.c @@ -750,12 +750,6 @@ void store_core_info_per_processor( if (cores) { processors[processor_global_index].core = cores + core_id; cores[core_id].core_id = core_id; - - if (chip_info->uarchs == NULL) { - cpuinfo_log_error("uarch is NULL for core %d", core_id); - return; - } - cores[core_id].uarch = chip_info->uarchs[0].uarch; cores[core_id].frequency = chip_info->uarchs[0].frequency; @@ -842,7 +836,6 @@ static bool connect_packages_cores_clusters_by_processors( processor->cluster = cluster; if (chip_info) { - size_t converted_chars = 0; if (!WideCharToMultiByte( CP_UTF8, WC_ERR_INVALID_CHARS, diff --git a/3rdparty/cpuinfo/src/arm/windows/init.c b/3rdparty/cpuinfo/src/arm/windows/init.c index ffbe554d16..e6334d3d17 100644 --- a/3rdparty/cpuinfo/src/arm/windows/init.c +++ b/3rdparty/cpuinfo/src/arm/windows/init.c @@ -21,7 +21,6 @@ static struct woa_chip_info woa_chip_unknown = {L"Unknown", {{cpuinfo_vendor_unk BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context) { struct woa_chip_info* chip_info = NULL; - enum cpuinfo_vendor vendor = cpuinfo_vendor_unknown; set_cpuinfo_isa_fields(); @@ -134,6 +133,26 @@ static struct core_info_by_chip_name get_core_info_from_midr(uint32_t midr, uint return info; } +/* https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers + CP 4000: MIDR_EL1 + CP 4020: ID_AA64PFR0_EL1 + CP 4021: ID_AA64PFR1_EL1 + CP 4028: ID_AA64DFR0_EL1 + CP 4029: ID_AA64DFR1_EL1 + CP 402C: ID_AA64AFR0_EL1 + CP 402D: ID_AA64AFR1_EL1 + CP 4030: ID_AA64ISAR0_EL1 + CP 4031: ID_AA64ISAR1_EL1 + CP 4038: ID_AA64MMFR0_EL1 + CP 4039: ID_AA64MMFR1_EL1 + CP 403A: ID_AA64MMFR2_EL1 + CP 4080: ? + CP 4081: ? + CP 4100: ? + CP 4510: ? + CP 5801: ? + */ + static struct woa_chip_info* get_system_info_from_registry(void) { wchar_t* text_buffer = NULL; LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; @@ -195,21 +214,40 @@ static void set_cpuinfo_isa_fields(void) { const bool dotprod = IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != 0; cpuinfo_isa.dot = dotprod; - SYSTEM_INFO system_info; - GetSystemInfo(&system_info); - switch (system_info.wProcessorLevel) { - case 0x803: // Kryo 385 Silver (Snapdragon 850) - cpuinfo_isa.fp16arith = dotprod; - cpuinfo_isa.rdm = dotprod; - break; - default: - // Assume that Dot Product support implies FP16 - // arithmetics and RDM support. ARM manuals don't - // guarantee that, but it holds in practice. - cpuinfo_isa.fp16arith = dotprod; - cpuinfo_isa.rdm = dotprod; - break; - } + cpuinfo_isa.sve = IsProcessorFeaturePresent(PF_ARM_SVE_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.sve2 = IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.i8mm = IsProcessorFeaturePresent(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.jscvt = IsProcessorFeaturePresent(PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.fcma = IsProcessorFeaturePresent(PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE) != 0; + // FEAT_FP16 Implies FEAT_FHM in 8.4 + // https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv8-4-architecture-extension?lang=en + cpuinfo_isa.fhm = IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.fp16arith = cpuinfo_isa.fhm; + + cpuinfo_isa.sme = IsProcessorFeaturePresent(PF_ARM_SME_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.sme2 = IsProcessorFeaturePresent(PF_ARM_SME2_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.sme2p1 = IsProcessorFeaturePresent(PF_ARM_SME2_1_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.sme_b16b16 = IsProcessorFeaturePresent(PF_ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.sme_f16f16 = IsProcessorFeaturePresent(PF_ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE) != 0; + + // TODO: Add when available in Windows SDK + // - sme_i16i32 + // - sme_bi32i32 + + cpuinfo_isa.bf16 = IsProcessorFeaturePresent(PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE) != 0; + + // TODO: This is not available in the Windows SDK yet , so conservatively go with the lowest value (128 bits) + // https://developer.arm.com/documentation/101427/0102/Register-descriptions/Scalable-vector-extensions--SVE--registers/ZCR-EL1--SVE-Control-Register--EL1 + cpuinfo_isa.svelen = + cpuinfo_isa.sve ? 128 / 8 : 0; // This value is in bytes, see cpuinfo_get_max_arm_sve_length + + // TODO : Fetch from feature registers when available + // cpuinfo_isa.smelen = 0; + + // Assume that Dot Product support implies FP16 + // arithmetics and RDM support. ARM manuals don't + // guarantee that, but it holds in practice. + cpuinfo_isa.rdm = dotprod; /* Windows API reports all or nothing for cryptographic instructions. */ const bool crypto = IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE) != 0; @@ -219,4 +257,4 @@ static void set_cpuinfo_isa_fields(void) { cpuinfo_isa.pmull = crypto; cpuinfo_isa.crc32 = IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE) != 0; -} \ No newline at end of file +} diff --git a/3rdparty/cpuinfo/src/arm/windows/windows-arm-init.h b/3rdparty/cpuinfo/src/arm/windows/windows-arm-init.h index 0448243d08..fc88a4404a 100644 --- a/3rdparty/cpuinfo/src/arm/windows/windows-arm-init.h +++ b/3rdparty/cpuinfo/src/arm/windows/windows-arm-init.h @@ -19,3 +19,63 @@ struct woa_chip_info { }; bool cpu_info_init_by_logical_sys_info(const struct woa_chip_info* chip_info, enum cpuinfo_vendor vendor); + +#ifndef PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE +#define PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE (27) +#endif + +#ifndef PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE +#define PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE (34) +#endif + +#ifndef PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE +#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE (44) +#endif + +#ifndef PF_ARM_SVE_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE (46) +#endif + +#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE (47) +#endif + +#ifndef PF_ARM_SME_BI32I32_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SME_BI32I32_INSTRUCTIONS_AVAILABLE (55) +#endif + +#ifndef PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE +#define PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE (66) +#endif + +#ifndef PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE +#define PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE (68) +#endif + +#ifndef PF_ARM_SME_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SME_INSTRUCTIONS_AVAILABLE (70) +#endif + +#ifndef PF_ARM_SME2_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SME2_INSTRUCTIONS_AVAILABLE (71) +#endif + +#ifndef PF_ARM_SME2_1_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SME2_1_INSTRUCTIONS_AVAILABLE (72) +#endif + +#ifndef PF_ARM_SME2_2_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SME2_2_INSTRUCTIONS_AVAILABLE (73) +#endif + +#ifndef PF_ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE (83) +#endif + +#ifndef PF_ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE (84) +#endif + +#ifndef PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE +#define PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE (67) +#endif diff --git a/3rdparty/cpuinfo/src/x86/api.h b/3rdparty/cpuinfo/src/x86/api.h index 1331ed0432..4d456c539a 100644 --- a/3rdparty/cpuinfo/src/x86/api.h +++ b/3rdparty/cpuinfo/src/x86/api.h @@ -105,6 +105,7 @@ CPUINFO_INTERNAL void cpuinfo_x86_detect_topology( CPUINFO_INTERNAL void cpuinfo_x86_detect_cache( uint32_t max_base_index, uint32_t max_extended_index, + /* amd_topology_extensions is not used, kept for backward compatibility */ bool amd_topology_extensions, enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, diff --git a/3rdparty/cpuinfo/src/x86/cache/init.c b/3rdparty/cpuinfo/src/x86/cache/init.c index 34af90e7f3..b07e61e78a 100644 --- a/3rdparty/cpuinfo/src/x86/cache/init.c +++ b/3rdparty/cpuinfo/src/x86/cache/init.c @@ -87,7 +87,7 @@ void cpuinfo_x86_detect_cache( } } } - if (amd_topology_extensions && max_extended_index >= UINT32_C(0x8000001D)) { + if (max_extended_index >= UINT32_C(0x8000001D)) { struct cpuid_regs leaf0x8000001D; uint32_t input_ecx = 0; do { diff --git a/3rdparty/cpuinfo/src/x86/init.c b/3rdparty/cpuinfo/src/x86/init.c index adc5d361b3..b2d27631d9 100644 --- a/3rdparty/cpuinfo/src/x86/init.c +++ b/3rdparty/cpuinfo/src/x86/init.c @@ -72,7 +72,7 @@ void cpuinfo_x86_init_processor(struct cpuinfo_x86_processor* processor) { for (uint32_t i = 0; i < 3; i++) { brand_string[i] = cpuid(UINT32_C(0x80000002) + i); } - memcpy(processor->brand_string, brand_string, sizeof(processor->brand_string)); + memcpy(processor->brand_string, brand_string, sizeof(brand_string)); cpuinfo_log_debug("raw CPUID brand string: \"%48s\"", processor->brand_string); } } diff --git a/3rdparty/cpuinfo/src/x86/uarch.c b/3rdparty/cpuinfo/src/x86/uarch.c index 2f4292bbb4..a0c900f435 100644 --- a/3rdparty/cpuinfo/src/x86/uarch.c +++ b/3rdparty/cpuinfo/src/x86/uarch.c @@ -188,10 +188,17 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x5A: // Moorefield case 0x5D: // SoFIA return cpuinfo_uarch_silvermont; - case 0xBE: // Twin Lake + case 0x86: // Jasper Lake + case 0x8A: // Lakefield + case 0x96: // Elkhart Lake + case 0x9C: // Jacobsville + return cpuinfo_uarch_tremont; + case 0xBE: // Alder Lake-N return cpuinfo_uarch_gracemont; case 0xAF: // Sierra Forest return cpuinfo_uarch_crestmont; + case 0xDD: // Clearwater Forest + return cpuinfo_uarch_darkmont; case 0x4C: // Braswell, Cherry // Trail case 0x75: // Spreadtrum @@ -208,8 +215,6 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( return cpuinfo_uarch_knights_landing; case 0x85: return cpuinfo_uarch_knights_mill; - case 0xDD: // Clearwater Forest - return cpuinfo_uarch_darkmont; } break; case 0x0F: