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Common: Switch pmovzx/sx to auto SSE/AVX

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This commit is contained in:
TellowKrinkle
2025-08-09 21:57:25 -05:00
committed by TellowKrinkle
parent 7eeb6c7aca
commit d9fc763f82
3 changed files with 49 additions and 23 deletions
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14
common/emitter/implement/simd_moremovs.h
View File

@@ -119,36 +119,36 @@ namespace x86Emitter
//
struct xImplSimd_PMove
{
u16 OpcodeBase;
SIMDInstructionInfo info;
// [SSE-4.1] Zero/Sign-extend the low byte values in src into word integers
// and store them in dest.
void BW(const xRegisterSSE& to, const xRegisterSSE& from) const;
void BW(const xRegisterSSE& to, const xIndirect64& from) const;
void BW(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low byte values in src into dword integers
// and store them in dest.
void BD(const xRegisterSSE& to, const xRegisterSSE& from) const;
void BD(const xRegisterSSE& to, const xIndirect32& from) const;
void BD(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low byte values in src into qword integers
// and store them in dest.
void BQ(const xRegisterSSE& to, const xRegisterSSE& from) const;
void BQ(const xRegisterSSE& to, const xIndirect16& from) const;
void BQ(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low word values in src into dword integers
// and store them in dest.
void WD(const xRegisterSSE& to, const xRegisterSSE& from) const;
void WD(const xRegisterSSE& to, const xIndirect64& from) const;
void WD(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low word values in src into qword integers
// and store them in dest.
void WQ(const xRegisterSSE& to, const xRegisterSSE& from) const;
void WQ(const xRegisterSSE& to, const xIndirect32& from) const;
void WQ(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low dword values in src into qword integers
// and store them in dest.
void DQ(const xRegisterSSE& to, const xRegisterSSE& from) const;
void DQ(const xRegisterSSE& to, const xIndirect64& from) const;
void DQ(const xRegisterSSE& to, const xIndirectVoid& from) const;
};
} // namespace x86Emitter

32
common/emitter/simd.cpp
View File

@@ -628,9 +628,9 @@ namespace x86Emitter
const xImplSimd_PInsert xPINSR;
const SimdImpl_PExtract xPEXTR;
static SIMDInstructionInfo nextop(SIMDInstructionInfo op)
static SIMDInstructionInfo nextop(SIMDInstructionInfo op, u32 offset = 1)
{
op.opcode++;
op.opcode += offset;
return op;
}
@@ -698,23 +698,23 @@ namespace x86Emitter
EmitSIMD(IsAligned(src, dst) ? aligned_store : op.unaligned_store, src, src, dst);
}
void xImplSimd_PMove::BW(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase); }
void xImplSimd_PMove::BW(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase); }
void xImplSimd_PMove::BW(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(info, dst, dst, src); }
void xImplSimd_PMove::BW(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(info, dst, dst, src); }
void xImplSimd_PMove::BD(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x100); }
void xImplSimd_PMove::BD(const xRegisterSSE& to, const xIndirect32& from) const { OpWriteSSE(0x66, OpcodeBase + 0x100); }
void xImplSimd_PMove::BD(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info), dst, dst, src); }
void xImplSimd_PMove::BD(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info), dst, dst, src); }
void xImplSimd_PMove::BQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x200); }
void xImplSimd_PMove::BQ(const xRegisterSSE& to, const xIndirect16& from) const { OpWriteSSE(0x66, OpcodeBase + 0x200); }
void xImplSimd_PMove::BQ(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info, 2), dst, dst, src); }
void xImplSimd_PMove::BQ(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info, 2), dst, dst, src); }
void xImplSimd_PMove::WD(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x300); }
void xImplSimd_PMove::WD(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase + 0x300); }
void xImplSimd_PMove::WD(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info, 3), dst, dst, src); }
void xImplSimd_PMove::WD(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info, 3), dst, dst, src); }
void xImplSimd_PMove::WQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x400); }
void xImplSimd_PMove::WQ(const xRegisterSSE& to, const xIndirect32& from) const { OpWriteSSE(0x66, OpcodeBase + 0x400); }
void xImplSimd_PMove::WQ(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info, 4), dst, dst, src); }
void xImplSimd_PMove::WQ(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info, 4), dst, dst, src); }
void xImplSimd_PMove::DQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x500); }
void xImplSimd_PMove::DQ(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase + 0x500); }
void xImplSimd_PMove::DQ(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info, 5), dst, dst, src); }
void xImplSimd_PMove::DQ(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info, 5), dst, dst, src); }
const xImplSimd_MoveSSE xMOVAPS = {
@@ -773,8 +773,8 @@ namespace x86Emitter
{SIMDInstructionInfo(0x15).p66().d().m0f38(), SIMDInstructionInfo(0x4b).d().p66().m0f3a()}, // VPD
};
const xImplSimd_PMove xPMOVSX = {0x2038};
const xImplSimd_PMove xPMOVZX = {0x3038};
const xImplSimd_PMove xPMOVSX = {SIMDInstructionInfo(0x20).p66().m0f38().mov()};
const xImplSimd_PMove xPMOVZX = {SIMDInstructionInfo(0x30).p66().m0f38().mov()};
// [SSE-3]
const xImplSimd_DestRegSSE xMOVSLDUP = {0xf3, 0x12};