mirror of
https://github.com/PCSX2/pcsx2.git
synced 2026-01-31 01:15:24 +01:00
cd9b6c7ac3
The VF cycle count doesn't go above 4, across 32 registers that saves 64 bytes. Also gets rid of blockhasmbit, since save states are getting invalidated anyway, it was never used. [SAVEVERSION+] VU struct changes.
292 lines
6.1 KiB
C++
292 lines
6.1 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "VUmicro.h"
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#include <cfenv>
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extern void _vuFlushAll(VURegs* VU);
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static void _vu0ExecUpper(VURegs* VU, u32* ptr)
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{
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VU->code = ptr[1];
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IdebugUPPER(VU0);
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VU0_UPPER_OPCODE[VU->code & 0x3f]();
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}
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static void _vu0ExecLower(VURegs* VU, u32* ptr)
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{
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VU->code = ptr[0];
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IdebugLOWER(VU0);
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VU0_LOWER_OPCODE[VU->code >> 25]();
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}
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int vu0branch = 0;
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static void _vu0Exec(VURegs* VU)
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{
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_VURegsNum lregs;
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_VURegsNum uregs;
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u32* ptr;
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ptr = (u32*)&VU->Micro[VU->VI[REG_TPC].UL];
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VU->VI[REG_TPC].UL += 8;
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if (ptr[1] & 0x40000000) // E flag
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{
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VU->ebit = 2;
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}
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if (ptr[1] & 0x20000000 && VU == &VU0) // M flag
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{
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VU->flags |= VUFLAG_MFLAGSET;
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// Console.WriteLn("fixme: M flag set");
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}
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if (ptr[1] & 0x10000000) // D flag
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{
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if (VU0.VI[REG_FBRST].UL & 0x4)
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{
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VU0.VI[REG_VPU_STAT].UL |= 0x2;
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hwIntcIrq(INTC_VU0);
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VU->ebit = 1;
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}
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}
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if (ptr[1] & 0x08000000) // T flag
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{
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if (VU0.VI[REG_FBRST].UL & 0x8)
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{
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VU0.VI[REG_VPU_STAT].UL |= 0x4;
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hwIntcIrq(INTC_VU0);
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VU->ebit = 1;
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}
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}
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VU->code = ptr[1];
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VU0regs_UPPER_OPCODE[VU->code & 0x3f](&uregs);
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u32 cyclesBeforeOp = VU0.cycle - 1;
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_vuTestUpperStalls(VU, &uregs);
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/* check upper flags */
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if (ptr[1] & 0x80000000) // I flag
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{
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_vuTestPipes(VU);
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if (VU->VIBackupCycles > 0)
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VU->VIBackupCycles -= std::min((u8)(VU0.cycle - cyclesBeforeOp), VU->VIBackupCycles);
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_vu0ExecUpper(VU, ptr);
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VU->VI[REG_I].UL = ptr[0];
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memset(&lregs, 0, sizeof(lregs));
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}
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else
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{
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VECTOR _VF;
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VECTOR _VFc;
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REG_VI _VI;
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REG_VI _VIc;
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int vfreg = 0;
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int vireg = 0;
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int discard = 0;
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VU->code = ptr[0];
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lregs.cycles = 0;
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VU0regs_LOWER_OPCODE[VU->code >> 25](&lregs);
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_vuTestLowerStalls(VU, &lregs);
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_vuTestPipes(VU);
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if (VU->VIBackupCycles > 0)
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VU->VIBackupCycles -= std::min((u8)(VU0.cycle - cyclesBeforeOp), VU->VIBackupCycles);
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vu0branch = lregs.pipe == VUPIPE_BRANCH;
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if (uregs.VFwrite)
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{
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if (lregs.VFwrite == uregs.VFwrite)
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{
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// Console.Warning("*PCSX2*: Warning, VF write to the same reg in both lower/upper cycle");
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discard = 1;
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}
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if (lregs.VFread0 == uregs.VFwrite ||
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lregs.VFread1 == uregs.VFwrite)
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{
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// Console.WriteLn("saving reg %d at pc=%x", i, VU->VI[REG_TPC].UL);
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_VF = VU->VF[uregs.VFwrite];
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vfreg = uregs.VFwrite;
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}
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}
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if (uregs.VIread & (1 << REG_CLIP_FLAG))
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{
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if (lregs.VIwrite & (1 << REG_CLIP_FLAG))
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{
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//Console.Warning("*PCSX2*: Warning, VI write to the same reg in both lower/upper cycle");
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discard = 1;
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}
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if (lregs.VIread & (1 << REG_CLIP_FLAG))
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{
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_VI = VU0.VI[REG_CLIP_FLAG];
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vireg = REG_CLIP_FLAG;
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}
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}
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_vu0ExecUpper(VU, ptr);
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if (discard == 0)
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{
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if (vfreg)
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{
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_VFc = VU->VF[vfreg];
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VU->VF[vfreg] = _VF;
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}
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if (vireg)
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{
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_VIc = VU->VI[vireg];
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VU->VI[vireg] = _VI;
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}
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_vu0ExecLower(VU, ptr);
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if (vfreg)
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{
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VU->VF[vfreg] = _VFc;
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}
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if (vireg)
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{
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VU->VI[vireg] = _VIc;
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}
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}
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}
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if (uregs.pipe == VUPIPE_FMAC || lregs.pipe == VUPIPE_FMAC)
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_vuClearFMAC(VU);
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_vuAddUpperStalls(VU, &uregs);
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_vuAddLowerStalls(VU, &lregs);
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if (VU->branch > 0)
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{
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if (VU->branch-- == 1)
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{
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VU->VI[REG_TPC].UL = VU->branchpc;
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if (VU->takedelaybranch)
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{
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DevCon.Warning("VU0 - Branch/Jump in Delay Slot");
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VU->branch = 1;
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VU->branchpc = VU->delaybranchpc;
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VU->takedelaybranch = false;
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}
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}
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}
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if (VU->ebit > 0)
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{
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if (VU->ebit-- == 1)
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{
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VU->VIBackupCycles = 0;
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_vuFlushAll(VU);
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VU0.VI[REG_VPU_STAT].UL &= ~0x1; /* E flag */
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vif0Regs.stat.VEW = false;
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}
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}
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// Progress the write position of the FMAC pipeline by one place
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if (uregs.pipe == VUPIPE_FMAC || lregs.pipe == VUPIPE_FMAC)
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VU->fmacwritepos = (VU->fmacwritepos + 1) & 3;
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}
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void vu0Exec(VURegs* VU)
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{
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VU0.VI[REG_TPC].UL &= VU0_PROGMASK;
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VU->cycle++;
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_vu0Exec(VU);
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if (VU->VI[0].UL != 0)
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DbgCon.Error("VI[0] != 0!!!!\n");
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if (VU->VF[0].f.x != 0.0f)
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DbgCon.Error("VF[0].x != 0.0!!!!\n");
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if (VU->VF[0].f.y != 0.0f)
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DbgCon.Error("VF[0].y != 0.0!!!!\n");
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if (VU->VF[0].f.z != 0.0f)
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DbgCon.Error("VF[0].z != 0.0!!!!\n");
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if (VU->VF[0].f.w != 1.0f)
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DbgCon.Error("VF[0].w != 1.0!!!!\n");
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}
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// --------------------------------------------------------------------------------------
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// VU0microInterpreter
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// --------------------------------------------------------------------------------------
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InterpVU0 CpuIntVU0;
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InterpVU0::InterpVU0()
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{
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m_Idx = 0;
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IsInterpreter = true;
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}
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void InterpVU0::Reset()
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{
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DevCon.Warning("VU0 Int Reset");
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VU0.fmacwritepos = 0;
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VU0.fmacreadpos = 0;
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VU0.fmaccount = 0;
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VU0.ialuwritepos = 0;
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VU0.ialureadpos = 0;
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VU0.ialucount = 0;
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}
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void InterpVU0::SetStartPC(u32 startPC)
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{
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VU0.start_pc = startPC;
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}
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void InterpVU0::Step()
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{
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vu0Exec(&VU0);
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}
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void InterpVU0::Execute(u32 cycles)
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{
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const int originalRounding = fegetround();
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fesetround(g_sseVU0MXCSR.RoundingControl << 8);
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VU0.VI[REG_TPC].UL <<= 3;
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VU0.flags &= ~VUFLAG_MFLAGSET;
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u32 startcycles = VU0.cycle;
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while ((VU0.cycle - startcycles) < cycles)
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{
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if (!(VU0.VI[REG_VPU_STAT].UL & 0x1))
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{
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// Branches advance the PC to the new location if there was a branch in the E-Bit delay slot
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if (VU0.branch)
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{
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VU0.VI[REG_TPC].UL = VU0.branchpc;
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VU0.branch = 0;
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}
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break;
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}
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if (VU0.flags & VUFLAG_MFLAGSET)
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break;
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vu0Exec(&VU0);
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}
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VU0.VI[REG_TPC].UL >>= 3;
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VU0.nextBlockCycles = (VU0.cycle - cpuRegs.cycle) + 1;
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fesetround(originalRounding);
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}
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