mirror of
https://github.com/PCSX2/pcsx2.git
synced 2026-01-31 01:15:24 +01:00
2223b97fa1
* Translate more stuff in various place * Fix issue with pot generation on linux namely empty string & quote in asm comment * add missing key on generate_pot script. Note: it also updates the po files with latest pot modification * regenerate new pot & po files. Translator note: previous Tertiary pot miss half of the strings. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4359 96395faa-99c1-11dd-bbfe-3dabce05a288
601 lines
14 KiB
C++
601 lines
14 KiB
C++
/******************************************************************************
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Copyright (c) 2001 Advanced Micro Devices, Inc.
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LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED *AS IS* WITHOUT ANY
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EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY,
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NONINFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY
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PARTICULAR PURPOSE. IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY
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DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
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BUSINESS INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
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INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION OR LIMITATION
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OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE LIMITATION MAY
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NOT APPLY TO YOU.
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AMD does not assume any responsibility for any errors which may appear in the
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Materials nor any responsibility to support or update the Materials. AMD retains
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the right to make changes to its test specifications at any time, without notice.
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NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
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further information, software, technical information, know-how, or show-how
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available to you.
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So that all may benefit from your experience, please report any problems
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or suggestions about this software to 3dsdk.support@amd.com
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AMD Developer Technologies, M/S 585
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Advanced Micro Devices, Inc.
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5900 E. Ben White Blvd.
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Austin, TX 78741
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3dsdk.support@amd.com
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******************************************************************************/
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#include "PrecompiledHeader.h"
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#ifdef _MSC_VER
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#pragma warning(disable:4414)
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#endif
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/*****************************************************************************
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MEMCPY_AMD.CPP
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******************************************************************************/
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// NOTE: Since this code uses MOVNTQ (also known as "Non-Temporal MOV" or
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// "Streaming Store"), and also uses the software prefetch instructions,
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// be sure you're running on P4/Core2/i7, Athlon/Phenom or newer CPUs before
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// calling!
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#define TINY_BLOCK_COPY 64 // upper limit for movsd type copy
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// The smallest copy uses the X86 "movsd" instruction, in an optimized
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// form which is an "unrolled loop".
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#define IN_CACHE_COPY 2 * 1024 // upper limit for movq/movq copy w/SW prefetch
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// Next is a copy that uses the MMX registers to copy 8 bytes at a time,
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// also using the "unrolled loop" optimization. This code uses
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// the software prefetch instruction to get the data into the cache.
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#define UNCACHED_COPY 4 * 1024 // upper limit for movq/movntq w/SW prefetch
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// For larger blocks, which will spill beyond the cache, it's faster to
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// use the Streaming Store instruction MOVNTQ. This write instruction
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// bypasses the cache and writes straight to main memory. This code also
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// uses the software prefetch instruction to pre-read the data.
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// USE 64 * 1024 FOR THIS VALUE IF YOU'RE ALWAYS FILLING A "CLEAN CACHE"
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// Inline assembly syntax for use with Visual C++
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#if defined(_MSC_VER)
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// Fast memcpy as coded by AMD, and then improved by air for PCSX2 needs.
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__declspec(naked) void __fastcall memcpy_amd_(void *dest, const void *src, size_t n)
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{
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__asm
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{
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push edi
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push esi
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mov edi, ecx ; destination
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mov esi, edx ; source
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mov ecx, [esp+12] ; number of bytes to copy
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mov eax, ecx ; keep a copy of count
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cld
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cmp eax, TINY_BLOCK_COPY
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jb $memcpy_ic_3 ; tiny? skip mmx copy
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cmp eax, 32*1024 ; dont align between 32k-64k because
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jbe $memcpy_do_align ; it appears to be slower
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cmp eax, 64*1024
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jbe $memcpy_align_done
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$memcpy_do_align:
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mov eax, 8 ; a trick that s faster than rep movsb...
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sub eax, edi ; align destination to qword
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and eax, 111b ; get the low bits
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sub ecx, eax ; update copy count
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neg eax ; set up to jump into the array
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add eax, offset $memcpy_align_done
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jmp eax ; jump to array of movsb s
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align 4
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movsb
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movsb
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movsb
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movsb
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movsb
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movsb
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movsb
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movsb
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$memcpy_align_done: ; destination is dword aligned
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mov eax, ecx ; number of bytes left to copy
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shr eax, 6 ; get 64-byte block count
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jz $memcpy_ic_2 ; finish the last few bytes
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cmp eax, IN_CACHE_COPY/64 ; too big 4 cache? use uncached copy
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jae $memcpy_uc_test
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// This is small block copy that uses the MMX registers to copy 8 bytes
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// at a time. It uses the "unrolled loop" optimization, and also uses
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// the software prefetch instruction to get the data into the cache.
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align 16
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$memcpy_ic_1: ; 64-byte block copies, in-cache copy
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prefetchnta [esi + (200*64/34+192)] ; start reading ahead
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movq mm0, [esi+0] ; read 64 bits
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movq mm1, [esi+8]
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movq [edi+0], mm0 ; write 64 bits
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movq [edi+8], mm1 ; note: the normal movq writes the
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movq mm2, [esi+16] ; data to cache; a cache line will be
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movq mm3, [esi+24] ; allocated as needed, to store the data
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movq [edi+16], mm2
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movq [edi+24], mm3
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movq mm0, [esi+32]
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movq mm1, [esi+40]
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movq [edi+32], mm0
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movq [edi+40], mm1
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movq mm2, [esi+48]
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movq mm3, [esi+56]
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movq [edi+48], mm2
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movq [edi+56], mm3
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add esi, 64 ; update source pointer
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add edi, 64 ; update destination pointer
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sub eax, 1
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jnz $memcpy_ic_1 ; last 64-byte block?
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$memcpy_ic_2:
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mov eax, ecx ; has valid low 6 bits of the byte count
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$memcpy_ic_3:
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shr eax, 2 ; dword count
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and eax, 1111b ; only look at the "remainder" bits
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neg eax ; set up to jump into the array
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add eax, offset $memcpy_last_few
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jmp eax ; jump to array of movsd s
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$memcpy_uc_test:
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or eax, eax ; tail end of block prefetch will jump here
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jz $memcpy_ic_2 ; no more 64-byte blocks left
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// For larger blocks, which will spill beyond the cache, it's faster to
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// use the Streaming Store instruction MOVNTQ. This write instruction
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// bypasses the cache and writes straight to main memory. This code also
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// uses the software prefetch instruction to pre-read the data.
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align 16
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$memcpy_uc_1: ; 64-byte blocks, uncached copy
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prefetchnta [esi + (200*64/34+192)] ; start reading ahead
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movq mm0,[esi+0] ; read 64 bits
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add edi,64 ; update destination pointer
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movq mm1,[esi+8]
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add esi,64 ; update source pointer
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movq mm2,[esi-48]
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movntq [edi-64], mm0 ; write 64 bits, bypassing the cache
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movq mm0,[esi-40] ; note: movntq also prevents the CPU
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movntq [edi-56], mm1 ; from READING the destination address
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movq mm1,[esi-32] ; into the cache, only to be over-written
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movntq [edi-48], mm2 ; so that also helps performance
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movq mm2,[esi-24]
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movntq [edi-40], mm0
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movq mm0,[esi-16]
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movntq [edi-32], mm1
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movq mm1,[esi-8]
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movntq [edi-24], mm2
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movntq [edi-16], mm0
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movntq [edi-8], mm1
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sub eax, 1
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jnz $memcpy_uc_1 ; last 64-byte block?
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jmp $memcpy_ic_2 ; almost done (not needed because large copy below was removed)
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// Note: Pcsx2 rarely invokes large copies, so the large copy "block prefetch" mode has been
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// disabled to help keep the code cache footprint of memcpy_fast to a minimum.
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// The smallest copy uses the X86 "movsd" instruction, in an optimized
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// form which is an "unrolled loop". Then it handles the last few bytes.
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align 16
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movsd
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movsd ; perform last 1-15 dword copies
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movsd
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movsd
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movsd
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movsd
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movsd
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movsd
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movsd
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movsd ; perform last 1-7 dword copies
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movsd
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movsd
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movsd
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movsd
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movsd
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movsd
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$memcpy_last_few: ; dword aligned from before movsd s
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and ecx, 11b ; the last few cows must come home
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jz $memcpy_final ; no more, let s leave
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rep movsb ; the last 1, 2, or 3 bytes
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$memcpy_final:
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pop esi
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pop edi
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emms ; clean up the MMX state
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sfence ; flush the write buffer
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//mov eax, [dest] ; ret value = destination pointer
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ret 4
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}
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}
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// Quadword Copy! Count is in QWCs (128 bits). Neither source nor dest need to be aligned.
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__fi void memcpy_amd_qwc(void *dest, const void *src, size_t qwc)
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{
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// Optimization Analysis: This code is *nearly* optimal. Do not think that using XMM
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// registers will improve copy performance, because they won't. Use of XMMs is only
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// warranted in situations where both source and dest are guaranteed aligned to 16 bytes,
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// and even then the benefits are typically minimal (sometimes slower depending on the
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// amount of data being copied).
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//
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// Thus: MMX are alignment safe, fast, and widely available. Lets just stick with them.
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// --air
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// Linux Conversion note:
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// This code would benefit nicely from having inline-able GAS syntax, since it should
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// allow GCC to optimize the first 3 instructions out of existence in many scenarios.
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// And its called enough times to probably merit the extra effort to ensure proper
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// optimization. --air
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__asm
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{
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mov ecx, dest
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mov edx, src
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mov eax, qwc ; keep a copy of count
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shr eax, 1
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jz $memcpy_qwc_1 ; only one 16 byte block to copy?
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cmp eax, IN_CACHE_COPY/32
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jb $memcpy_qwc_loop1 ; small copies should be cached (definite speedup --air)
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$memcpy_qwc_loop2: ; 32-byte blocks, uncached copy
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prefetchnta [edx + 568] ; start reading ahead (tested: it helps! --air)
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movq mm0,[edx+0] ; read 64 bits
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movq mm1,[edx+8]
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movq mm2,[edx+16]
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movntq [ecx+0], mm0 ; write 64 bits, bypassing the cache
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movntq [ecx+8], mm1
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movq mm3,[edx+24]
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movntq [ecx+16], mm2
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movntq [ecx+24], mm3
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add edx,32 ; update source pointer
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add ecx,32 ; update destination pointer
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sub eax,1
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jnz $memcpy_qwc_loop2 ; last 64-byte block?
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sfence ; flush the write buffer
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jmp $memcpy_qwc_1
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; 32-byte blocks, cached!
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; This *is* important. Removing this and using exclusively non-temporal stores
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; results in noticable speed loss!
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$memcpy_qwc_loop1:
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prefetchnta [edx + 568] ; start reading ahead (tested: it helps! --air)
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movq mm0,[edx+0] ; read 64 bits
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movq mm1,[edx+8]
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movq mm2,[edx+16]
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movq [ecx+0], mm0 ; write 64 bits, bypassing the cache
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movq [ecx+8], mm1
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movq mm3,[edx+24]
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movq [ecx+16], mm2
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movq [ecx+24], mm3
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add edx,32 ; update source pointer
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add ecx,32 ; update destination pointer
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sub eax,1
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jnz $memcpy_qwc_loop1 ; last 64-byte block?
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$memcpy_qwc_1:
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test qwc,1
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jz $memcpy_qwc_final
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movq mm0,[edx]
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movq mm1,[edx+8]
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movq [ecx], mm0
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movq [ecx+8], mm1
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$memcpy_qwc_final:
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emms ; clean up the MMX state
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}
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}
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// mmx mem-compare implementation, size has to be a multiple of 8
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// returns 0 is equal, nonzero value if not equal
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// ~10 times faster than standard memcmp
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// (zerofrog)
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u8 memcmp_mmx(const void* src1, const void* src2, int cmpsize)
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{
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pxAssert( (cmpsize&7) == 0 );
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__asm {
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mov ecx, cmpsize
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mov edx, src1
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mov esi, src2
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cmp ecx, 32
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jl Done4
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// custom test first 8 to make sure things are ok
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movq mm0, [esi]
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movq mm1, [esi+8]
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pcmpeqd mm0, [edx]
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pcmpeqd mm1, [edx+8]
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pand mm0, mm1
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movq mm2, [esi+16]
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pmovmskb eax, mm0
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movq mm3, [esi+24]
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// check if eq
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cmp eax, 0xff
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je NextComp
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mov eax, 1
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jmp End
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NextComp:
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pcmpeqd mm2, [edx+16]
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pcmpeqd mm3, [edx+24]
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pand mm2, mm3
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pmovmskb eax, mm2
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sub ecx, 32
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add esi, 32
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add edx, 32
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// check if eq
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cmp eax, 0xff
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je ContinueTest
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mov eax, 1
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jmp End
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cmp ecx, 64
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jl Done8
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Cmp8:
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movq mm0, [esi]
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movq mm1, [esi+8]
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movq mm2, [esi+16]
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movq mm3, [esi+24]
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movq mm4, [esi+32]
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movq mm5, [esi+40]
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movq mm6, [esi+48]
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movq mm7, [esi+56]
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pcmpeqd mm0, [edx]
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pcmpeqd mm1, [edx+8]
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pcmpeqd mm2, [edx+16]
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pcmpeqd mm3, [edx+24]
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pand mm0, mm1
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pcmpeqd mm4, [edx+32]
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pand mm0, mm2
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pcmpeqd mm5, [edx+40]
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pand mm0, mm3
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pcmpeqd mm6, [edx+48]
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pand mm0, mm4
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pcmpeqd mm7, [edx+56]
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pand mm0, mm5
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pand mm0, mm6
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pand mm0, mm7
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pmovmskb eax, mm0
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// check if eq
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cmp eax, 0xff
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je Continue
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mov eax, 1
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jmp End
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Continue:
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sub ecx, 64
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add esi, 64
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add edx, 64
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ContinueTest:
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cmp ecx, 64
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jge Cmp8
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Done8:
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test ecx, 0x20
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jz Done4
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movq mm0, [esi]
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movq mm1, [esi+8]
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movq mm2, [esi+16]
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movq mm3, [esi+24]
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pcmpeqd mm0, [edx]
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pcmpeqd mm1, [edx+8]
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pcmpeqd mm2, [edx+16]
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pcmpeqd mm3, [edx+24]
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pand mm0, mm1
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pand mm0, mm2
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pand mm0, mm3
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pmovmskb eax, mm0
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sub ecx, 32
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add esi, 32
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add edx, 32
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// check if eq
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cmp eax, 0xff
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je Done4
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mov eax, 1
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jmp End
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Done4:
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cmp ecx, 24
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jne Done2
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movq mm0, [esi]
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movq mm1, [esi+8]
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movq mm2, [esi+16]
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pcmpeqd mm0, [edx]
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pcmpeqd mm1, [edx+8]
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pcmpeqd mm2, [edx+16]
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pand mm0, mm1
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pand mm0, mm2
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pmovmskb eax, mm0
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// check if eq
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cmp eax, 0xff
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setne al
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jmp End
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Done2:
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cmp ecx, 16
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jne Done1
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movq mm0, [esi]
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movq mm1, [esi+8]
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pcmpeqd mm0, [edx]
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pcmpeqd mm1, [edx+8]
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pand mm0, mm1
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pmovmskb eax, mm0
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// check if eq
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cmp eax, 0xff
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setne al
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jmp End
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Done1:
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cmp ecx, 8
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jne Done
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mov eax, [esi]
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mov esi, [esi+4]
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cmp eax, [edx]
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je Next
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mov eax, 1
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jmp End
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Next:
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cmp esi, [edx+4]
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setne al
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jmp End
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Done:
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xor eax, eax
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End:
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emms
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}
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}
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// returns the xor of all elements, cmpsize has to be mult of 8
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void memxor_mmx(void* dst, const void* src1, int cmpsize)
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{
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pxAssert( (cmpsize&7) == 0 );
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__asm {
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mov ecx, cmpsize
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mov eax, src1
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mov edx, dst
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cmp ecx, 64
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jl Setup4
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movq mm0, [eax]
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movq mm1, [eax+8]
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movq mm2, [eax+16]
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movq mm3, [eax+24]
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movq mm4, [eax+32]
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movq mm5, [eax+40]
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movq mm6, [eax+48]
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movq mm7, [eax+56]
|
|
sub ecx, 64
|
|
add eax, 64
|
|
cmp ecx, 64
|
|
jl End8
|
|
|
|
Cmp8:
|
|
pxor mm0, [eax]
|
|
pxor mm1, [eax+8]
|
|
pxor mm2, [eax+16]
|
|
pxor mm3, [eax+24]
|
|
pxor mm4, [eax+32]
|
|
pxor mm5, [eax+40]
|
|
pxor mm6, [eax+48]
|
|
pxor mm7, [eax+56]
|
|
|
|
sub ecx, 64
|
|
add eax, 64
|
|
cmp ecx, 64
|
|
jge Cmp8
|
|
|
|
End8:
|
|
pxor mm0, mm4
|
|
pxor mm1, mm5
|
|
pxor mm2, mm6
|
|
pxor mm3, mm7
|
|
|
|
cmp ecx, 32
|
|
jl End4
|
|
pxor mm0, [eax]
|
|
pxor mm1, [eax+8]
|
|
pxor mm2, [eax+16]
|
|
pxor mm3, [eax+24]
|
|
sub ecx, 32
|
|
add eax, 32
|
|
jmp End4
|
|
|
|
Setup4:
|
|
cmp ecx, 32
|
|
jl Setup2
|
|
|
|
movq mm0, [eax]
|
|
movq mm1, [eax+8]
|
|
movq mm2, [eax+16]
|
|
movq mm3, [eax+24]
|
|
sub ecx, 32
|
|
add eax, 32
|
|
|
|
End4:
|
|
pxor mm0, mm2
|
|
pxor mm1, mm3
|
|
|
|
cmp ecx, 16
|
|
jl End2
|
|
pxor mm0, [eax]
|
|
pxor mm1, [eax+8]
|
|
sub ecx, 16
|
|
add eax, 16
|
|
jmp End2
|
|
|
|
Setup2:
|
|
cmp ecx, 16
|
|
jl Setup1
|
|
|
|
movq mm0, [eax]
|
|
movq mm1, [eax+8]
|
|
sub ecx, 16
|
|
add eax, 16
|
|
|
|
End2:
|
|
pxor mm0, mm1
|
|
|
|
cmp ecx, 8
|
|
jl End1
|
|
pxor mm0, [eax]
|
|
End1:
|
|
movq [edx], mm0
|
|
jmp End
|
|
|
|
Setup1:
|
|
movq mm0, [eax]
|
|
movq [edx], mm0
|
|
End:
|
|
emms
|
|
}
|
|
}
|
|
|
|
#endif
|