mirror of
https://github.com/PCSX2/pcsx2.git
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26392e7f3e
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5160 96395faa-99c1-11dd-bbfe-3dabce05a288
522 lines
17 KiB
C++
522 lines
17 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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//------------------------------------------------------------------
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// Micro VU - Pass 1 Functions
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Helper Functions
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//------------------------------------------------------------------
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// Read a VF reg
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__ri void analyzeReg1(mV, int xReg, microVFreg& vfRead) {
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if (xReg) {
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if (_X) { mVUstall = max(mVUstall, mVUregs.VF[xReg].x); vfRead.reg = xReg; vfRead.x = 1; }
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if (_Y) { mVUstall = max(mVUstall, mVUregs.VF[xReg].y); vfRead.reg = xReg; vfRead.y = 1; }
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if (_Z) { mVUstall = max(mVUstall, mVUregs.VF[xReg].z); vfRead.reg = xReg; vfRead.z = 1; }
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if (_W) { mVUstall = max(mVUstall, mVUregs.VF[xReg].w); vfRead.reg = xReg; vfRead.w = 1; }
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}
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}
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// Write to a VF reg
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__ri void analyzeReg2(mV, int xReg, microVFreg& vfWrite, bool isLowOp) {
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if (xReg) {
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#define bReg(x, y) mVUregsTemp.VFreg[y] = x; mVUregsTemp.VF[y]
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if (_X) { bReg(xReg, isLowOp).x = 4; vfWrite.reg = xReg; vfWrite.x = 4; }
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if (_Y) { bReg(xReg, isLowOp).y = 4; vfWrite.reg = xReg; vfWrite.y = 4; }
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if (_Z) { bReg(xReg, isLowOp).z = 4; vfWrite.reg = xReg; vfWrite.z = 4; }
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if (_W) { bReg(xReg, isLowOp).w = 4; vfWrite.reg = xReg; vfWrite.w = 4; }
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}
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}
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// Read a VF reg (BC opcodes)
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__ri void analyzeReg3(mV, int xReg, microVFreg& vfRead) {
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if (xReg) {
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if (_bc_x) { mVUstall = max(mVUstall, mVUregs.VF[xReg].x); vfRead.reg = xReg; vfRead.x = 1; }
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elif (_bc_y) { mVUstall = max(mVUstall, mVUregs.VF[xReg].y); vfRead.reg = xReg; vfRead.y = 1; }
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elif (_bc_z) { mVUstall = max(mVUstall, mVUregs.VF[xReg].z); vfRead.reg = xReg; vfRead.z = 1; }
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else { mVUstall = max(mVUstall, mVUregs.VF[xReg].w); vfRead.reg = xReg; vfRead.w = 1; }
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}
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}
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// For Clip Opcode
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__ri void analyzeReg4(mV, int xReg, microVFreg& vfRead) {
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if (xReg) {
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mVUstall = max(mVUstall, mVUregs.VF[xReg].w);
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vfRead.reg = xReg;
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vfRead.w = 1;
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}
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}
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// Read VF reg (FsF/FtF)
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__ri void analyzeReg5(mV, int xReg, int fxf, microVFreg& vfRead) {
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if (xReg) {
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switch (fxf) {
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case 0: mVUstall = max(mVUstall, mVUregs.VF[xReg].x); vfRead.reg = xReg; vfRead.x = 1; break;
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case 1: mVUstall = max(mVUstall, mVUregs.VF[xReg].y); vfRead.reg = xReg; vfRead.y = 1; break;
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case 2: mVUstall = max(mVUstall, mVUregs.VF[xReg].z); vfRead.reg = xReg; vfRead.z = 1; break;
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case 3: mVUstall = max(mVUstall, mVUregs.VF[xReg].w); vfRead.reg = xReg; vfRead.w = 1; break;
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}
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}
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}
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// Flips xyzw stalls to yzwx (MR32 Opcode)
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__ri void analyzeReg6(mV, int xReg, microVFreg& vfRead) {
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if (xReg) {
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if (_X) { mVUstall = max(mVUstall, mVUregs.VF[xReg].y); vfRead.reg = xReg; vfRead.y = 1; }
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if (_Y) { mVUstall = max(mVUstall, mVUregs.VF[xReg].z); vfRead.reg = xReg; vfRead.z = 1; }
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if (_Z) { mVUstall = max(mVUstall, mVUregs.VF[xReg].w); vfRead.reg = xReg; vfRead.w = 1; }
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if (_W) { mVUstall = max(mVUstall, mVUregs.VF[xReg].x); vfRead.reg = xReg; vfRead.x = 1; }
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}
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}
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// Reading a VI reg
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__ri void analyzeVIreg1(mV, int xReg, microVIreg& viRead) {
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if (xReg) {
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mVUstall = max(mVUstall, mVUregs.VI[xReg]);
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viRead.reg = xReg;
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viRead.used = 1;
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}
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}
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// Writing to a VI reg
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__ri void analyzeVIreg2(mV, int xReg, microVIreg& viWrite, int aCycles) {
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if (xReg) {
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mVUconstReg[xReg].isValid = 0;
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mVUregsTemp.VIreg = xReg;
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mVUregsTemp.VI = aCycles;
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viWrite.reg = xReg;
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viWrite.used = aCycles;
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}
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}
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#define analyzeQreg(x) { mVUregsTemp.q = x; mVUstall = max(mVUstall, mVUregs.q); }
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#define analyzePreg(x) { mVUregsTemp.p = x; mVUstall = max(mVUstall, (u8)((mVUregs.p) ? (mVUregs.p - 1) : 0)); }
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#define analyzeRreg() { mVUregsTemp.r = 1; }
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#define analyzeXGkick1() { mVUstall = max(mVUstall, mVUregs.xgkick); }
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#define analyzeXGkick2(x) { mVUregsTemp.xgkick = x; }
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#define setConstReg(x, v) { if (x) { mVUconstReg[x].isValid = 1; mVUconstReg[x].regValue = v; } }
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//------------------------------------------------------------------
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// FMAC1 - Normal FMAC Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeFMAC1(mV, int Fd, int Fs, int Ft) {
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sFLAG.doFlag = 1;
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analyzeReg1(mVU, Fs, mVUup.VF_read[0]);
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analyzeReg1(mVU, Ft, mVUup.VF_read[1]);
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analyzeReg2(mVU, Fd, mVUup.VF_write, 0);
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}
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//------------------------------------------------------------------
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// FMAC2 - ABS/FTOI/ITOF Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeFMAC2(mV, int Fs, int Ft) {
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analyzeReg1(mVU, Fs, mVUup.VF_read[0]);
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analyzeReg2(mVU, Ft, mVUup.VF_write, 0);
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}
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//------------------------------------------------------------------
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// FMAC3 - BC(xyzw) FMAC Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeFMAC3(mV, int Fd, int Fs, int Ft) {
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sFLAG.doFlag = 1;
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analyzeReg1(mVU, Fs, mVUup.VF_read[0]);
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analyzeReg3(mVU, Ft, mVUup.VF_read[1]);
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analyzeReg2(mVU, Fd, mVUup.VF_write, 0);
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}
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//------------------------------------------------------------------
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// FMAC4 - Clip FMAC Opcode
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//------------------------------------------------------------------
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__fi void mVUanalyzeFMAC4(mV, int Fs, int Ft) {
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cFLAG.doFlag = 1;
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analyzeReg1(mVU, Fs, mVUup.VF_read[0]);
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analyzeReg4(mVU, Ft, mVUup.VF_read[1]);
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}
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//------------------------------------------------------------------
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// IALU - IALU Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeIALU1(mV, int Id, int Is, int It) {
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if (!Id) mVUlow.isNOP = 1;
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analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
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analyzeVIreg1(mVU, It, mVUlow.VI_read[1]);
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analyzeVIreg2(mVU, Id, mVUlow.VI_write, 1);
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}
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__fi void mVUanalyzeIALU2(mV, int Is, int It) {
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if (!It) mVUlow.isNOP = 1;
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analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
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analyzeVIreg2(mVU, It, mVUlow.VI_write, 1);
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}
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__fi void mVUanalyzeIADDI(mV, int Is, int It, s16 imm) {
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mVUanalyzeIALU2(mVU, Is, It);
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if (!Is) { setConstReg(It, imm); }
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}
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//------------------------------------------------------------------
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// MR32 - MR32 Opcode
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//------------------------------------------------------------------
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__fi void mVUanalyzeMR32(mV, int Fs, int Ft) {
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if (!Ft) { mVUlow.isNOP = 1; }
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analyzeReg6(mVU, Fs, mVUlow.VF_read[0]);
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analyzeReg2(mVU, Ft, mVUlow.VF_write, 1);
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}
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//------------------------------------------------------------------
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// FDIV - DIV/SQRT/RSQRT Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeFDIV(mV, int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) {
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analyzeReg5(mVU, Fs, Fsf, mVUlow.VF_read[0]);
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analyzeReg5(mVU, Ft, Ftf, mVUlow.VF_read[1]);
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analyzeQreg(xCycles);
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}
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//------------------------------------------------------------------
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// EFU - EFU Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeEFU1(mV, int Fs, int Fsf, u8 xCycles) {
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analyzeReg5(mVU, Fs, Fsf, mVUlow.VF_read[0]);
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analyzePreg(xCycles);
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}
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__fi void mVUanalyzeEFU2(mV, int Fs, u8 xCycles) {
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analyzeReg1(mVU, Fs, mVUlow.VF_read[0]);
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analyzePreg(xCycles);
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}
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//------------------------------------------------------------------
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// MFP - MFP Opcode
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//------------------------------------------------------------------
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__fi void mVUanalyzeMFP(mV, int Ft) {
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if (!Ft) mVUlow.isNOP = 1;
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analyzeReg2(mVU, Ft, mVUlow.VF_write, 1);
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}
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//------------------------------------------------------------------
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// MOVE - MOVE Opcode
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//------------------------------------------------------------------
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__fi void mVUanalyzeMOVE(mV, int Fs, int Ft) {
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if (!Ft||(Ft == Fs)) mVUlow.isNOP = 1;
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analyzeReg1(mVU, Fs, mVUlow.VF_read[0]);
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analyzeReg2(mVU, Ft, mVUlow.VF_write, 1);
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}
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//------------------------------------------------------------------
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// LQx - LQ/LQD/LQI Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeLQ(mV, int Ft, int Is, bool writeIs) {
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analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
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analyzeReg2 (mVU, Ft, mVUlow.VF_write, 1);
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if (!Ft) { if (writeIs && Is) { mVUlow.noWriteVF = 1; } else { mVUlow.isNOP = 1; } }
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if (writeIs) { analyzeVIreg2(mVU, Is, mVUlow.VI_write, 1); }
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}
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//------------------------------------------------------------------
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// SQx - SQ/SQD/SQI Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeSQ(mV, int Fs, int It, bool writeIt) {
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analyzeReg1 (mVU, Fs, mVUlow.VF_read[0]);
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analyzeVIreg1(mVU, It, mVUlow.VI_read[0]);
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if (writeIt) { analyzeVIreg2(mVU, It, mVUlow.VI_write, 1); }
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}
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//------------------------------------------------------------------
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// R*** - R Reg Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeR1(mV, int Fs, int Fsf) {
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analyzeReg5(mVU, Fs, Fsf, mVUlow.VF_read[0]);
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analyzeRreg();
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}
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__fi void mVUanalyzeR2(mV, int Ft, bool canBeNOP) {
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if (!Ft) {
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if (canBeNOP) mVUlow.isNOP = 1;
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else mVUlow.noWriteVF = 1;
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}
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analyzeReg2(mVU, Ft, mVUlow.VF_write, 1);
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analyzeRreg();
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}
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//------------------------------------------------------------------
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// Sflag - Status Flag Opcodes
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//------------------------------------------------------------------
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__ri void flagSet(mV, bool setMacFlag) {
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int curPC = iPC;
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for (int i = mVUcount, j = 0; i > 0; i--, j++) {
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j += mVUstall;
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incPC2(-2);
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if (sFLAG.doFlag && (j >= 3)) {
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if (setMacFlag) { mFLAG.doFlag = 1; }
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else { sFLAG.doNonSticky = 1; }
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break;
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}
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}
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iPC = curPC;
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}
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__ri void mVUanalyzeSflag(mV, int It) {
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mVUlow.readFlags = 1;
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analyzeVIreg2(mVU, It, mVUlow.VI_write, 1);
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if (!It) { mVUlow.isNOP = 1; }
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else {
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mVUsFlagHack = 0; // Don't Optimize Out Status Flags for this block
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mVUinfo.swapOps = 1;
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flagSet(mVU, 0);
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if (mVUcount < 4) {
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if (!(mVUpBlock->pState.needExactMatch & 1)) // The only time this should happen is on the first program block
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DevCon.WriteLn(Color_Green, "microVU%d: pState's sFlag Info was expected to be set [%04x]", getIndex, xPC);
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}
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}
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}
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__ri void mVUanalyzeFSSET(mV) {
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mVUlow.isFSSET = 1;
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mVUlow.readFlags = 1;
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}
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//------------------------------------------------------------------
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// Mflag - Mac Flag Opcodes
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//------------------------------------------------------------------
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__ri void mVUanalyzeMflag(mV, int Is, int It) {
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mVUlow.readFlags = 1;
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analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
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analyzeVIreg2(mVU, It, mVUlow.VI_write, 1);
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if (!It) { mVUlow.isNOP = 1; }
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else {
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mVUinfo.swapOps = 1;
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flagSet(mVU, 1);
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if (mVUcount < 4) {
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if (!(mVUpBlock->pState.needExactMatch & 2)) // The only time this should happen is on the first program block
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DevCon.WriteLn(Color_Green, "microVU%d: pState's mFlag Info was expected to be set [%04x]", getIndex, xPC);
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}
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}
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}
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//------------------------------------------------------------------
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// Cflag - Clip Flag Opcodes
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//------------------------------------------------------------------
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__fi void mVUanalyzeCflag(mV, int It) {
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mVUinfo.swapOps = 1;
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mVUlow.readFlags = 1;
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if (mVUcount < 4) {
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if (!(mVUpBlock->pState.needExactMatch & 4)) // The only time this should happen is on the first program block
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DevCon.WriteLn(Color_Green, "microVU%d: pState's cFlag Info was expected to be set [%04x]", getIndex, xPC);
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}
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analyzeVIreg2(mVU, It, mVUlow.VI_write, 1);
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}
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//------------------------------------------------------------------
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// XGkick
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//------------------------------------------------------------------
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__fi void mVUanalyzeXGkick(mV, int Fs, int xCycles) {
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analyzeVIreg1(mVU, Fs, mVUlow.VI_read[0]);
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analyzeXGkick1(); // Stall will cause mVUincCycles() to trigger pending xgkick
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analyzeXGkick2(xCycles);
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// Note: Technically XGKICK should stall on the next instruction,
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// this code stalls on the same instruction. The only case where this
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// will be a problem with, is if you have very-specifically placed
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// FMxxx or FSxxx opcodes checking flags near this instruction AND
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// the XGKICK instruction stalls. No-game should be effected by
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// this minor difference.
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}
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//------------------------------------------------------------------
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// Branches - Branch Opcodes
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//------------------------------------------------------------------
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// If the VI reg is modified directly before the branch, then the VI
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// value read by the branch is the value the VI reg had at the start
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// of the instruction 4 instructions ago (assuming no stalls).
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// See: http://forums.pcsx2.net/Thread-blog-PS2-VU-Vector-Unit-Documentation-Part-1
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static void analyzeBranchVI(mV, int xReg, bool& infoVar) {
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if (!xReg) return;
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if (mVUstall) { // I assume a stall on branch means the vi reg is not modified directly b4 the branch...
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DevCon.Warning("microVU%d: %d cycle stall on branch instruction [%04x]", getIndex, mVUstall, xPC);
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return;
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}
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int i, j = 0;
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int cyc = 0;
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int iEnd = 4;
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int bPC = iPC;
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incPC2(-2);
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for (i = 0; i < iEnd && cyc < iEnd; i++) {
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if (i && mVUstall) {
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DevCon.Warning("microVU%d: Branch VI-Delay with %d cycle stall (%d) [%04x]", getIndex, mVUstall, i, xPC);
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}
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if (i == mVUcount) {
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bool warn = 0;
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if (i == 1) warn = 1;
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if (mVUpBlock->pState.viBackUp == xReg) {
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DevCon.WriteLn(Color_Green, "microVU%d: Loading Branch VI value from previous block", getIndex);
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if (i == 0) warn = 1;
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infoVar = 1;
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j = i; i++;
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}
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if (warn) DevCon.Warning("microVU%d: Branch VI-Delay with small block (%d) [%04x]", getIndex, i, xPC);
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break; // if (warn), we don't have enough information to always guarantee the correct result.
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}
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if ((mVUlow.VI_write.reg == xReg) && mVUlow.VI_write.used) {
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if (mVUlow.readFlags) {
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if (i) DevCon.Warning("microVU%d: Branch VI-Delay with Read Flags Set (%d) [%04x]", getIndex, i, xPC);
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break; // Not sure if on the above "if (i)" case, if we need to "continue" or if we should "break"
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}
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j = i;
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}
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elif (i == 0) break;
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cyc += mVUstall + 1;
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incPC2(-2);
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}
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if (i) {
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if (!infoVar) {
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iPC = bPC;
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incPC2(-2*(j+1));
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mVUlow.backupVI = 1;
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infoVar = 1;
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}
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iPC = bPC;
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DevCon.WriteLn(Color_Green, "microVU%d: Branch VI-Delay (%d) [%04x][%03d]", getIndex, j+1, xPC, mVU.prog.cur->idx);
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}
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else iPC = bPC;
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}
|
|
|
|
/*
|
|
// Dead Code... the old version of analyzeBranchVI()
|
|
__fi void analyzeBranchVI(mV, int xReg, bool& infoVar) {
|
|
if (!xReg) return;
|
|
int i;
|
|
int iEnd = aMin(5, (mVUcount+1));
|
|
int bPC = iPC;
|
|
incPC2(-2);
|
|
for (i = 0; i < iEnd; i++) {
|
|
if ((i == mVUcount) && (i < 5)) {
|
|
if (mVUpBlock->pState.viBackUp == xReg) {
|
|
infoVar = 1;
|
|
i++;
|
|
}
|
|
break;
|
|
}
|
|
if ((mVUlow.VI_write.reg == xReg) && mVUlow.VI_write.used) {
|
|
if (mVUlow.readFlags || i == 5) break;
|
|
if (i == 0) { incPC2(-2); continue; }
|
|
if (((mVUlow.VI_read[0].reg == xReg) && (mVUlow.VI_read[0].used))
|
|
|| ((mVUlow.VI_read[1].reg == xReg) && (mVUlow.VI_read[1].used)))
|
|
{ incPC2(-2); continue; }
|
|
}
|
|
break;
|
|
}
|
|
if (i) {
|
|
if (!infoVar) {
|
|
incPC2(2);
|
|
mVUlow.backupVI = 1;
|
|
infoVar = 1;
|
|
}
|
|
iPC = bPC;
|
|
DevCon.WriteLn( Color_Green, "microVU%d: Branch VI-Delay (%d) [%04x]", getIndex, i, xPC);
|
|
}
|
|
else iPC = bPC;
|
|
}
|
|
*/
|
|
|
|
// Branch in Branch Delay-Slots
|
|
__ri int mVUbranchCheck(mV) {
|
|
if (!mVUcount) return 0;
|
|
incPC(-2);
|
|
if (mVUlow.branch) {
|
|
u32 branchType = mVUlow.branch;
|
|
if (doBranchInDelaySlot) {
|
|
mVUlow.badBranch = 1;
|
|
incPC(2);
|
|
mVUlow.evilBranch = 1;
|
|
mVUregs.blockType = 2;
|
|
mVUregs.needExactMatch |= 7; // This might not be necessary, but w/e...
|
|
mVUregs.flagInfo = 0;
|
|
mVUregs.fullFlags0 = 0;
|
|
mVUregs.fullFlags1 = 0;
|
|
DevCon.Warning("microVU%d: %s in %s delay slot! [%04x]", mVU.index,
|
|
branchSTR[mVUlow.branch&0xf], branchSTR[branchType&0xf], xPC);
|
|
return 1;
|
|
}
|
|
else {
|
|
incPC(2);
|
|
mVUlow.isNOP = 1;
|
|
DevCon.Warning("microVU%d: %s in %s delay slot! [%04x]", mVU.index,
|
|
branchSTR[mVUlow.branch&0xf], branchSTR[branchType&0xf], xPC);
|
|
return 0;
|
|
}
|
|
}
|
|
incPC(2);
|
|
return 0;
|
|
}
|
|
|
|
__fi void mVUanalyzeCondBranch1(mV, int Is) {
|
|
analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
|
|
if (!mVUbranchCheck(mVU)) {
|
|
analyzeBranchVI(mVU, Is, mVUlow.memReadIs);
|
|
}
|
|
}
|
|
|
|
__fi void mVUanalyzeCondBranch2(mV, int Is, int It) {
|
|
analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
|
|
analyzeVIreg1(mVU, It, mVUlow.VI_read[1]);
|
|
if (!mVUbranchCheck(mVU)) {
|
|
analyzeBranchVI(mVU, Is, mVUlow.memReadIs);
|
|
analyzeBranchVI(mVU, It, mVUlow.memReadIt);
|
|
}
|
|
}
|
|
|
|
__fi void mVUanalyzeNormBranch(mV, int It, bool isBAL) {
|
|
mVUbranchCheck(mVU);
|
|
if (isBAL) {
|
|
analyzeVIreg2(mVU, It, mVUlow.VI_write, 1);
|
|
setConstReg(It, bSaveAddr);
|
|
}
|
|
}
|
|
|
|
__ri void mVUanalyzeJump(mV, int Is, int It, bool isJALR) {
|
|
mVUlow.branch = (isJALR) ? 10 : 9;
|
|
mVUbranchCheck(mVU);
|
|
if (mVUconstReg[Is].isValid && doConstProp) {
|
|
mVUlow.constJump.isValid = 1;
|
|
mVUlow.constJump.regValue = mVUconstReg[Is].regValue;
|
|
//DevCon.Status("microVU%d: Constant JR/JALR Address Optimization", mVU.index);
|
|
}
|
|
analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
|
|
if (isJALR) {
|
|
analyzeVIreg2(mVU, It, mVUlow.VI_write, 1);
|
|
setConstReg(It, bSaveAddr);
|
|
}
|
|
}
|