mirror of
https://github.com/PCSX2/pcsx2.git
synced 2026-01-31 01:15:24 +01:00
8984e80c24
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3575 96395faa-99c1-11dd-bbfe-3dabce05a288
307 lines
9.0 KiB
C++
307 lines
9.0 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "Hardware.h"
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#include "newVif.h"
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using namespace R5900;
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u8 *psH; // hw mem
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const int rdram_devices = 2; // put 8 for TOOL and 2 for PS2 and PSX
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int rdram_sdevid = 0;
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static bool hwInitialized = false;
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void hwInit()
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{
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// [TODO] / FIXME: PCSX2 no longer works on an Init system. It assumes that the
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// static global vars for the process will be initialized when the process is created, and
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// then issues *resets only* from then on. (reset code for various S2 components should do
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// NULL checks and allocate memory and such if the pointers are NULL only).
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if( hwInitialized ) return;
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VifUnpackSSE_Init();
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gsInit();
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sifInit();
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sprInit();
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ipuInit();
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hwInitialized = true;
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}
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/*void hwShutdown()
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{
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ipuShutdown();
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}*/
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void hwReset()
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{
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hwInit();
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memzero_ptr<Ps2MemSize::Hardware>( PS2MEM_HW );
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//memset(PS2MEM_HW+0x2000, 0, 0x0000e000);
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psHu32(SBUS_F260) = 0x1D000060;
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// i guess this is kinda a version, it's used by some bioses
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psHu32(DMAC_ENABLEW) = 0x1201;
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psHu32(DMAC_ENABLER) = 0x1201;
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SPU2reset();
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sifInit();
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sprInit();
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gsReset();
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ipuReset();
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vif0Reset();
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vif1Reset();
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}
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__forceinline void intcInterrupt()
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{
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if ((psHu32(INTC_STAT)) == 0) {
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//DevCon.Warning("*PCSX2*: intcInterrupt already cleared");
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return;
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}
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if ((psHu32(INTC_STAT) & psHu32(INTC_MASK)) == 0)
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{
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//DevCon.Warning("*PCSX2*: No valid interrupt INTC_MASK: %x INTC_STAT: %x", psHu32(INTC_MASK), psHu32(INTC_STAT));
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return;
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}
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HW_LOG("intcInterrupt %x", psHu32(INTC_STAT) & psHu32(INTC_MASK));
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if(psHu32(INTC_STAT) & 0x2){
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counters[0].hold = rcntRcount(0);
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counters[1].hold = rcntRcount(1);
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}
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cpuException(0x400, cpuRegs.branch);
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}
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__forceinline void dmacInterrupt()
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{
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if( ((psHu16(DMAC_STAT + 2) & psHu16(DMAC_STAT)) == 0 ) &&
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( psHu16(DMAC_STAT) & 0x8000) == 0 )
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{
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//DevCon.Warning("No valid DMAC interrupt MASK %x STAT %x", psHu16(DMAC_STAT+2), psHu16(DMAC_STAT));
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return;
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}
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if (!(dmacRegs->ctrl.DMAE) || psHu8(DMAC_ENABLER+2) == 1)
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{
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//DevCon.Warning("DMAC Suspended or Disabled on interrupt");
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return;
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}
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HW_LOG("dmacInterrupt %x", (psHu16(DMAC_STAT + 2) & psHu16(DMAC_STAT) |
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psHu16(DMAC_STAT) & 0x8000));
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cpuException(0x800, cpuRegs.branch);
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}
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void hwIntcIrq(int n)
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{
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psHu32(INTC_STAT) |= 1<<n;
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if(psHu32(INTC_MASK) & (1<<n))cpuTestINTCInts();
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}
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void hwDmacIrq(int n)
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{
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psHu32(DMAC_STAT) |= 1<<n;
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if(psHu16(DMAC_STAT+2) & (1<<n))cpuTestDMACInts();
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}
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// Write 'size' bytes to memory address 'addr' from 'data'.
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__releaseinline bool hwMFIFOWrite(u32 addr, const u128* data, uint qwc)
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{
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// all FIFO addresses should always be QWC-aligned.
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pxAssume((dmacRegs->rbor.ADDR & 15) == 0);
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pxAssume((addr & 15) == 0);
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// DMAC Address resolution: FIFO can be placed anywhere in the *physical* memory map
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// for the PS2. Its probably a serious error for a PS2 app to have the buffer cross
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// valid/invalid page areas of ram, so realistically we only need to test the base address
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// of the FIFO for address validity.
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if (u128* dst = (u128*)PSM(dmacRegs->rbor.ADDR))
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{
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const u32 ringsize = (dmacRegs->rbsr.RMSK / 16) + 1;
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pxAssertMsg( PSM(dmacRegs->rbor.ADDR+ringsize-1) != NULL, "Scratchpad/MFIFO ringbuffer spans into invalid (unmapped) physical memory!" );
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uint startpos = (addr & dmacRegs->rbsr.RMSK)/16;
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MemCopy_WrappedDest( data, dst, startpos, ringsize, qwc );
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}
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else
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{
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SPR_LOG( "Scratchpad/MFIFO: invalid base physical address: 0x%08x", dmacRegs->rbor.ADDR );
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pxFailDev( wxsFormat( L"Scratchpad/MFIFO: Invalid base physical address: 0x%08x", dmacRegs->rbor.ADDR) );
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return false;
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}
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return true;
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}
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__releaseinline bool hwDmacSrcChainWithStack(DMACh *dma, int id) {
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switch (id) {
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case TAG_REFE: // Refe - Transfer Packet According to ADDR field
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//End Transfer
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return true;
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case TAG_CNT: // CNT - Transfer QWC following the tag.
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// Set MADR to QW afer tag, and set TADR to QW following the data.
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dma->madr = dma->tadr + 16;
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dma->tadr = dma->madr + (dma->qwc << 4);
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return false;
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case TAG_NEXT: // Next - Transfer QWC following tag. TADR = ADDR
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{
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// Set MADR to QW following the tag, and set TADR to the address formerly in MADR.
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u32 temp = dma->madr;
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dma->madr = dma->tadr + 16;
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dma->tadr = temp;
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return false;
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}
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case TAG_REF: // Ref - Transfer QWC from ADDR field
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case TAG_REFS: // Refs - Transfer QWC from ADDR field (Stall Control)
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//Set TADR to next tag
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dma->tadr += 16;
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return false;
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case TAG_CALL: // Call - Transfer QWC following the tag, save succeeding tag
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{
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// Store the address in MADR in temp, and set MADR to the data following the tag.
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u32 temp = dma->madr;
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dma->madr = dma->tadr + 16;
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if(temp == 0)
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{
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DevCon.Warning("DMA Chain CALL next tag error. Tag Addr = 0");
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dma->tadr = dma->madr + (dma->qwc << 4);
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return false;
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}
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// Stash an address on the address stack pointer.
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switch(dma->chcr.ASP)
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{
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case 0: //Check if ASR0 is empty
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// Store the succeeding tag in asr0, and mark chcr as having 1 address.
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dma->asr0 = dma->madr + (dma->qwc << 4);
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dma->chcr.ASP++;
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break;
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case 1:
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// Store the succeeding tag in asr1, and mark chcr as having 2 addresses.
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dma->asr1 = dma->madr + (dma->qwc << 4);
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dma->chcr.ASP++;
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break;
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default:
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Console.Warning("Call Stack Overflow (report if it fixes/breaks anything)");
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return true;
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}
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// Set TADR to the address from MADR we stored in temp.
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dma->tadr = temp;
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return false;
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}
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case TAG_RET: // Ret - Transfer QWC following the tag, load next tag
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//Set MADR to data following the tag.
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dma->madr = dma->tadr + 16;
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// Snag an address from the address stack pointer.
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switch(dma->chcr.ASP)
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{
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case 2:
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// Pull asr1 from the stack, give it to TADR, and decrease the # of addresses.
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dma->tadr = dma->asr1;
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dma->asr1 = 0;
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dma->chcr.ASP--;
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break;
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case 1:
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// Pull asr0 from the stack, give it to TADR, and decrease the # of addresses.
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dma->tadr = dma->asr0;
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dma->asr0 = 0;
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dma->chcr.ASP--;
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break;
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case 0:
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// There aren't any addresses to pull, so end the transfer.
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//dma->tadr += 16; //Clear tag address - Kills Klonoa 2
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return true;
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default:
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// If ASR1 and ASR0 are messed up, end the transfer.
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//Console.Error("TAG_RET: ASR 1 & 0 == 1. This shouldn't happen!");
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//dma->tadr += 16; //Clear tag address - Kills Klonoa 2
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return true;
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}
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return false;
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case TAG_END: // End - Transfer QWC following the tag
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//Set MADR to data following the tag, and end the transfer.
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dma->madr = dma->tadr + 16;
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//Don't Increment tadr; breaks Soul Calibur II and III
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return true;
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}
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return false;
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}
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bool hwDmacSrcChain(DMACh *dma, int id)
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{
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u32 temp;
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switch (id)
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{
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case TAG_REFE: // Refe - Transfer Packet According to ADDR field
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// End the transfer.
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return true;
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case TAG_CNT: // CNT - Transfer QWC following the tag.
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// Set MADR to QW after the tag, and TADR to QW following the data.
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dma->madr = dma->tadr + 16;
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dma->tadr = dma->madr + (dma->qwc << 4);
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return false;
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case TAG_NEXT: // Next - Transfer QWC following tag. TADR = ADDR
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// Set MADR to QW following the tag, and set TADR to the address formerly in MADR.
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temp = dma->madr;
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dma->madr = dma->tadr + 16;
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dma->tadr = temp;
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return false;
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case TAG_REF: // Ref - Transfer QWC from ADDR field
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case TAG_REFS: // Refs - Transfer QWC from ADDR field (Stall Control)
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//Set TADR to next tag
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dma->tadr += 16;
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return false;
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case TAG_END: // End - Transfer QWC following the tag
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//Set MADR to data following the tag, and end the transfer.
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dma->madr = dma->tadr + 16;
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//Don't Increment tadr; breaks Soul Calibur II and III
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return true;
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}
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return false;
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}
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