mirror of
https://github.com/PCSX2/pcsx2.git
synced 2026-01-31 01:15:24 +01:00
c17455c702
* Configuration panels are all modal-less now, so that you can open the config panel and leave it open while running games. * Handful of thread sync improvements. * Fixed on-the-fly interpreter/recompiler configuration. * Fixed plugin hotswapping (mostly works, but still a little funny at times) * All new assertion dialogs and popup message handlers. * RecentIsoList defaults to 12 instead of 6 Dev Notes: * I had to create a new set of assertion functions called pxAssume*. Originally I hoped to avoid that complexity, and just use a single one-assert-fits-all case, but turned out blanketly using __assume() for all assertion cases wasn't reliable. * wxGuiTools: Replaced the operator, with operator& -- the latter has proper order of precedence, the former required () to scope correctly. >_< git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2339 96395faa-99c1-11dd-bbfe-3dabce05a288
805 lines
22 KiB
C++
805 lines
22 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "VifDma.h"
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#include "VifDma_internal.h"
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#include "VUmicro.h"
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__aligned16 u32 g_vif0Masks[64];
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u32 g_vif0HasMask3[4] = {0};
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extern int (__fastcall *Vif0TransTLB[128])(u32 *data);
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extern void (*Vif0CMDTLB[75])();
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vifStruct vif0;
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__forceinline void vif0FLUSH()
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{
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int _cycles = VU0.cycle;
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// fixme: this code should call _vu0WaitMicro instead? I'm not sure if
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// it's purposefully ignoring ee cycles or not (see below for more)
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vu0Finish();
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g_vifCycles += (VU0.cycle - _cycles) * BIAS;
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}
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void vif0Init()
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{
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for (u32 i = 0; i < 256; ++i)
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{
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s_maskwrite[i] = ((i & 3) == 3) || ((i & 0xc) == 0xc) || ((i & 0x30) == 0x30) || ((i & 0xc0) == 0xc0);
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}
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SetNewMask(g_vif0Masks, g_vif0HasMask3, 0, 0xffffffff);
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}
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static __forceinline void vif0UNPACK(u32 *data)
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{
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int vifNum;
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if ((vif0Regs->cycle.wl == 0) && (vif0Regs->cycle.wl < vif0Regs->cycle.cl))
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{
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Console.WriteLn("Vif0 CL %d, WL %d", vif0Regs->cycle.cl, vif0Regs->cycle.wl);
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vif0.cmd &= ~0x7f;
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return;
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}
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vif0FLUSH();
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vif0.tag.addr = (vif0Regs->code & 0xff) << 4;
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vif0.usn = (vif0Regs->code >> 14) & 0x1;
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vifNum = (vif0Regs->code >> 16) & 0xff;
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if (vifNum == 0) vifNum = 256;
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vif0Regs->num = vifNum;
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if (vif0Regs->cycle.wl <= vif0Regs->cycle.cl)
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{
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vif0.tag.size = ((vifNum * VIFfuncTable[ vif0.cmd & 0xf ].gsize) + 3) >> 2;
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}
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else
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{
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int n = vif0Regs->cycle.cl * (vifNum / vif0Regs->cycle.wl) +
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_limit(vifNum % vif0Regs->cycle.wl, vif0Regs->cycle.cl);
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vif0.tag.size = ((n * VIFfuncTable[ vif0.cmd & 0xf ].gsize) + 3) >> 2;
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}
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vif0.cl = 0;
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vif0.tag.cmd = vif0.cmd;
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vif0Regs->offset = 0;
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}
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static __forceinline void vif0mpgTransfer(u32 addr, u32 *data, int size)
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{
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/* Console.WriteLn("vif0mpgTransfer addr=%x; size=%x", addr, size);
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{
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FILE *f = fopen("vu1.raw", "wb");
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fwrite(data, 1, size*4, f);
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fclose(f);
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}*/
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if (memcmp(VU0.Micro + addr, data, size << 2))
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{
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CpuVU0->Clear(addr, size << 2); // Clear before writing! :/ (cottonvibes)
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memcpy_fast(VU0.Micro + addr, data, size << 2);
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}
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}
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Vif0 Data Transfer Commands
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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static int __fastcall Vif0TransNull(u32 *data) // Shouldnt go here
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{
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Console.WriteLn("VIF0 Shouldn't go here CMD = %x", vif0Regs->code);
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vif0.cmd = 0;
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return 0;
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}
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static int __fastcall Vif0TransSTMask(u32 *data) // STMASK
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{
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SetNewMask(g_vif0Masks, g_vif0HasMask3, data[0], vif0Regs->mask);
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vif0Regs->mask = data[0];
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VIF_LOG("STMASK == %x", vif0Regs->mask);
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vif0.tag.size = 0;
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vif0.cmd = 0;
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return 1;
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}
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static int __fastcall Vif0TransSTRow(u32 *data) // STROW
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{
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int ret;
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u32* pmem = &vif0Regs->r0 + (vif0.tag.addr << 2);
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u32* pmem2 = g_vifmask.Row0 + vif0.tag.addr;
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pxAssume(vif0.tag.addr < 4);
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ret = min(4 - vif0.tag.addr, vif0.vifpacketsize);
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pxAssume(ret > 0);
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switch (ret)
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{
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case 4:
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pmem[12] = data[3];
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pmem2[3] = data[3];
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case 3:
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pmem[8] = data[2];
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pmem2[2] = data[2];
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case 2:
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pmem[4] = data[1];
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pmem2[1] = data[1];
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case 1:
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pmem[0] = data[0];
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pmem2[0] = data[0];
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break;
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jNO_DEFAULT
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}
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vif0.tag.addr += ret;
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vif0.tag.size -= ret;
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if (vif0.tag.size == 0) vif0.cmd = 0;
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return ret;
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}
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static int __fastcall Vif0TransSTCol(u32 *data) // STCOL
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{
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int ret;
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u32* pmem = &vif0Regs->c0 + (vif0.tag.addr << 2);
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u32* pmem2 = g_vifmask.Col0 + vif0.tag.addr;
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ret = min(4 - vif0.tag.addr, vif0.vifpacketsize);
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switch (ret)
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{
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case 4:
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pmem[12] = data[3];
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pmem2[3] = data[3];
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case 3:
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pmem[8] = data[2];
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pmem2[2] = data[2];
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case 2:
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pmem[4] = data[1];
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pmem2[1] = data[1];
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case 1:
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pmem[0] = data[0];
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pmem2[0] = data[0];
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break;
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jNO_DEFAULT
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}
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vif0.tag.addr += ret;
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vif0.tag.size -= ret;
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if (vif0.tag.size == 0) vif0.cmd = 0;
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return ret;
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}
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static int __fastcall Vif0TransMPG(u32 *data) // MPG
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{
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if (vif0.vifpacketsize < vif0.tag.size)
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{
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if((vif0.tag.addr + vif0.vifpacketsize) > 0x1000) DevCon.Warning("Vif0 MPG Split Overflow");
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vif0mpgTransfer(vif0.tag.addr, data, vif0.vifpacketsize);
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vif0.tag.addr += vif0.vifpacketsize << 2;
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vif0.tag.size -= vif0.vifpacketsize;
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return vif0.vifpacketsize;
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}
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else
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{
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int ret;
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if((vif0.tag.addr + vif0.tag.size) > 0x1000) DevCon.Warning("Vif0 MPG Overflow");
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vif0mpgTransfer(vif0.tag.addr, data, vif0.tag.size);
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ret = vif0.tag.size;
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vif0.tag.size = 0;
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vif0.cmd = 0;
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return ret;
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}
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}
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static int __fastcall Vif0TransUnpack(u32 *data) // UNPACK
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{
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int ret;
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XMMRegisters::Freeze();
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if (vif0.vifpacketsize < vif0.tag.size)
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{
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if(vif0Regs->offset != 0 || vif0.cl != 0)
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{
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ret = vif0.tag.size;
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vif0.tag.size -= vif0.vifpacketsize - VIFalign<0>(data, &vif0.tag, vif0.vifpacketsize);
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ret = ret - vif0.tag.size;
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data += ret;
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if(vif0.vifpacketsize > 0) VIFunpack<0>(data, &vif0.tag, vif0.vifpacketsize - ret);
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ProcessMemSkip<0>((vif0.vifpacketsize - ret) << 2, (vif0.cmd & 0xf));
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vif0.tag.size -= (vif0.vifpacketsize - ret);
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XMMRegisters::Thaw();
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return vif0.vifpacketsize;
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}
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/* size is less that the total size, transfer is 'in pieces' */
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VIFunpack<0>(data, &vif0.tag, vif0.vifpacketsize);
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ProcessMemSkip<0>(vif0.vifpacketsize << 2, (vif0.cmd & 0xf));
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ret = vif0.vifpacketsize;
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vif0.tag.size -= ret;
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}
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else
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{
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/* we got all the data, transfer it fully */
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ret = vif0.tag.size;
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//Align data after a split transfer first
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if ((vif0Regs->offset != 0) || (vif0.cl != 0))
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{
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vif0.tag.size = VIFalign<0>(data, &vif0.tag, vif0.tag.size);
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data += ret - vif0.tag.size;
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if(vif0.tag.size > 0) VIFunpack<0>(data, &vif0.tag, vif0.tag.size);
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}
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else
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{
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VIFunpack<0>(data, &vif0.tag, vif0.tag.size);
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}
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vif0.tag.size = 0;
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vif0.cmd = 0;
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}
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XMMRegisters::Thaw();
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return ret;
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}
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Vif0 CMD Base Commands
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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static void Vif0CMDNop() // NOP
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{
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vif0.cmd &= ~0x7f;
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}
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static void Vif0CMDSTCycl() // STCYCL
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{
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vif0Regs->cycle.cl = (u8)vif0Regs->code;
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vif0Regs->cycle.wl = (u8)(vif0Regs->code >> 8);
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vif0.cmd &= ~0x7f;
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}
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static void Vif0CMDITop() // ITOP
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{
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vif0Regs->itops = vif0Regs->code & 0x3ff;
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vif0.cmd &= ~0x7f;
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}
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static void Vif0CMDSTMod() // STMOD
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{
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vif0Regs->mode = vif0Regs->code & 0x3;
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vif0.cmd &= ~0x7f;
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}
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static void Vif0CMDMark() // MARK
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{
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vif0Regs->mark = (u16)vif0Regs->code;
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vif0Regs->stat.MRK = true;
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vif0.cmd &= ~0x7f;
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}
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static void Vif0CMDFlushE() // FLUSHE
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{
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vif0FLUSH();
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vif0.cmd &= ~0x7f;
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}
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static void Vif0CMDMSCALF() //MSCAL/F
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{
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vuExecMicro<0>((u16)(vif0Regs->code) << 3);
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vif0.cmd &= ~0x7f;
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}
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static void Vif0CMDMSCNT() // MSCNT
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{
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vuExecMicro<0>(-1);
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vif0.cmd &= ~0x7f;
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}
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static void Vif0CMDSTMask() // STMASK
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{
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vif0.tag.size = 1;
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}
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static void Vif0CMDSTRowCol() // STROW / STCOL
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{
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vif0.tag.addr = 0;
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vif0.tag.size = 4;
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}
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static void Vif0CMDMPGTransfer() // MPG
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{
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int vifNum;
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vif0FLUSH();
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vifNum = (u8)(vif0Regs->code >> 16);
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if (vifNum == 0) vifNum = 256;
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vif0.tag.addr = (u16)((vif0Regs->code) << 3) & 0xfff;
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vif0.tag.size = vifNum * 2;
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}
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static void Vif0CMDNull() // invalid opcode
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{
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// if ME1, then force the vif to interrupt
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if (!(vif0Regs->err.ME1)) //Ignore vifcode and tag mismatch error
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{
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Console.WriteLn("UNKNOWN VifCmd: %x", vif0.cmd);
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vif0Regs->stat.ER1 = true;
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vif0.irq++;
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}
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vif0.cmd &= ~0x7f;
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}
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bool VIF0transfer(u32 *data, int size, bool istag)
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{
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int ret;
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int transferred = vif0.vifstalled ? vif0.irqoffset : 0; // irqoffset necessary to add up the right qws, or else will spin (spiderman)
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VIF_LOG("VIF0transfer: size %x (vif0.cmd %x)", size, vif0.cmd);
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vif0.stallontag = false;
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vif0.vifstalled = false;
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vif0.vifpacketsize = size;
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while (vif0.vifpacketsize > 0)
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{
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if (vif0.cmd)
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{
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vif0Regs->stat.VPS = VPS_TRANSFERRING; //Decompression has started
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ret = Vif0TransTLB[(vif0.cmd & 0x7f)](data);
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data += ret;
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vif0.vifpacketsize -= ret;
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if (vif0.cmd == 0) vif0Regs->stat.VPS = VPS_IDLE; //We are once again waiting for a new vifcode as the command has cleared
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continue;
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}
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if (vif0.tag.size != 0) Console.WriteLn("no vif0 cmd but tag size is left last cmd read %x", vif0Regs->code);
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// if interrupt and new cmd is NOT MARK
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if (vif0.irq) break;
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vif0.cmd = (data[0] >> 24);
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vif0Regs->code = data[0];
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vif0Regs->stat.VPS |= VPS_DECODING; //We need to set these (Onimusha needs it)
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if ((vif0.cmd & 0x60) == 0x60)
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{
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vif0UNPACK(data);
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}
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else
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{
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VIF_LOG("VIFtransfer: cmd %x, num %x, imm %x, size %x", vif0.cmd, (data[0] >> 16) & 0xff, data[0] & 0xffff, size);
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if ((vif0.cmd & 0x7f) > 0x4A)
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{
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if (!(vif0Regs->err.ME1)) //Ignore vifcode and tag mismatch error
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{
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Console.WriteLn("UNKNOWN VifCmd: %x", vif0.cmd);
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vif0Regs->stat.ER1 = true;
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vif0.irq++;
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}
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vif0.cmd = 0;
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}
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else
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{
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Vif0CMDTLB[(vif0.cmd & 0x7f)]();
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}
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}
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++data;
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--vif0.vifpacketsize;
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if ((vif0.cmd & 0x80))
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{
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vif0.cmd &= 0x7f;
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if (!(vif0Regs->err.MII)) //i bit on vifcode and not masked by VIF0_ERR
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{
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VIF_LOG("Interrupt on VIFcmd: %x (INTC_MASK = %x)", vif0.cmd, psHu32(INTC_MASK));
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++vif0.irq;
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if (istag && vif0.tag.size <= vif0.vifpacketsize) vif0.stallontag = true;
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if (vif0.tag.size == 0) break;
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}
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}
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} //End of Transfer loop
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transferred += size - vif0.vifpacketsize;
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g_vifCycles += (transferred >> 2) * BIAS; /* guessing */
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// use tag.size because some game doesn't like .cmd
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if (vif0.irq && (vif0.tag.size == 0))
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{
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vif0.vifstalled = true;
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if (((vif0Regs->code >> 24) & 0x7f) != 0x7) vif0Regs->stat.VIS = true;
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//else Console.WriteLn("VIF0 IRQ on MARK");
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// spiderman doesn't break on qw boundaries
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vif0.irqoffset = transferred % 4; // cannot lose the offset
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if (!istag)
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{
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transferred = transferred >> 2;
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vif0ch->madr += (transferred << 4);
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vif0ch->qwc -= transferred;
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}
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//else Console.WriteLn("Stall on vif0, FromSPR = %x, Vif0MADR = %x Sif0MADR = %x STADR = %x", psHu32(0x1000d010), vif0ch->madr, psHu32(0x1000c010), psHu32(DMAC_STADR));
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return false;
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}
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vif0Regs->stat.VPS = VPS_IDLE; //Vif goes idle as the stall happened between commands;
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if (vif0.cmd) vif0Regs->stat.VPS |= VPS_WAITING; //Otherwise we wait for the data
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if (!istag)
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{
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transferred = transferred >> 2;
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vif0ch->madr += (transferred << 4);
|
|
vif0ch->qwc -= transferred;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool _VIF0chain()
|
|
{
|
|
u32 *pMem;
|
|
|
|
if ((vif0ch->qwc == 0) && !vif0.vifstalled) return true;
|
|
|
|
pMem = (u32*)dmaGetAddr(vif0ch->madr);
|
|
if (pMem == NULL)
|
|
{
|
|
vif0.cmd = 0;
|
|
vif0.tag.size = 0;
|
|
vif0ch->qwc = 0;
|
|
return true;
|
|
}
|
|
|
|
if (vif0.vifstalled)
|
|
return VIF0transfer(pMem + vif0.irqoffset, vif0ch->qwc * 4 - vif0.irqoffset, false);
|
|
else
|
|
return VIF0transfer(pMem, vif0ch->qwc * 4, false);
|
|
}
|
|
|
|
bool _chainVIF0()
|
|
{
|
|
tDMA_TAG *ptag;
|
|
|
|
ptag = dmaGetAddr(vif0ch->tadr); //Set memory pointer to TADR
|
|
|
|
if (!(vif0ch->transfer("Vif0 Tag", ptag))) return false;
|
|
|
|
vif0ch->madr = ptag[1]._u32; // MADR = ADDR field + SPR
|
|
g_vifCycles += 1; // Increase the QW read for the tag
|
|
|
|
VIF_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx",
|
|
ptag[1]._u32, ptag[0]._u32, vif0ch->qwc, ptag->ID, vif0ch->madr, vif0ch->tadr);
|
|
|
|
// Transfer dma tag if tte is set
|
|
if (vif0ch->chcr.TTE)
|
|
{
|
|
bool ret;
|
|
|
|
if (vif0.vifstalled)
|
|
ret = VIF0transfer((u32*)ptag + (2 + vif0.irqoffset), 2 - vif0.irqoffset, true); //Transfer Tag on stall
|
|
else
|
|
ret = VIF0transfer((u32*)ptag + 2, 2, true); //Transfer Tag
|
|
|
|
if (!(ret)) return false; //IRQ set by VIFTransfer
|
|
}
|
|
|
|
vif0.done |= hwDmacSrcChainWithStack(vif0ch, ptag->ID);
|
|
|
|
VIF_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx",
|
|
ptag[1]._u32, ptag[0]._u32, vif0ch->qwc, ptag->ID, vif0ch->madr, vif0ch->tadr);
|
|
|
|
_VIF0chain(); //Transfers the data set by the switch
|
|
|
|
if (vif0ch->chcr.TIE && ptag->IRQ) //Check TIE bit of CHCR and IRQ bit of tag
|
|
{
|
|
VIF_LOG("dmaIrq Set\n");
|
|
vif0.done = true; //End Transfer
|
|
}
|
|
|
|
return vif0.done;
|
|
}
|
|
|
|
void vif0Interrupt()
|
|
{
|
|
g_vifCycles = 0; //Reset the cycle count, Wouldn't reset on stall if put lower down.
|
|
VIF_LOG("vif0Interrupt: %8.8x", cpuRegs.cycle);
|
|
|
|
if (vif0.irq && (vif0.tag.size == 0))
|
|
{
|
|
vif0Regs->stat.INT = true;
|
|
hwIntcIrq(VIF0intc);
|
|
--vif0.irq;
|
|
|
|
if (vif0Regs->stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
|
|
{
|
|
vif0Regs->stat.FQC = 0;
|
|
vif0ch->chcr.STR = false;
|
|
return;
|
|
}
|
|
|
|
if (vif0ch->qwc > 0 || vif0.irqoffset > 0)
|
|
{
|
|
if (vif0.stallontag)
|
|
_chainVIF0();
|
|
else
|
|
_VIF0chain();
|
|
|
|
CPU_INT(0, /*g_vifCycles*/ VifCycleVoodoo);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (!vif0ch->chcr.STR) Console.WriteLn("Vif0 running when CHCR = %x", vif0ch->chcr._u32);
|
|
|
|
if ((vif0ch->chcr.MOD == CHAIN_MODE) && (!vif0.done) && (!vif0.vifstalled))
|
|
{
|
|
|
|
if (!(dmacRegs->ctrl.DMAE))
|
|
{
|
|
Console.WriteLn("vif0 dma masked");
|
|
return;
|
|
}
|
|
|
|
if (vif0ch->qwc > 0)
|
|
_VIF0chain();
|
|
else
|
|
_chainVIF0();
|
|
|
|
CPU_INT(0, /*g_vifCycles*/ VifCycleVoodoo);
|
|
return;
|
|
}
|
|
|
|
if (vif0ch->qwc > 0) Console.WriteLn("VIF0 Ending with QWC left");
|
|
if (vif0.cmd != 0) Console.WriteLn("vif0.cmd still set %x", vif0.cmd);
|
|
|
|
vif0ch->chcr.STR = false;
|
|
hwDmacIrq(DMAC_VIF0);
|
|
vif0Regs->stat.FQC = 0;
|
|
}
|
|
|
|
// Vif0 Data Transfer Table
|
|
int (__fastcall *Vif0TransTLB[128])(u32 *data) =
|
|
{
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x7*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0xF*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x17*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x1F*/
|
|
Vif0TransSTMask , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x27*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x2F*/
|
|
Vif0TransSTRow , Vif0TransSTCol , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x37*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x3F*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x47*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransMPG , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x4F*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x57*/
|
|
Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , Vif0TransNull , /*0x5F*/
|
|
Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransNull , /*0x67*/
|
|
Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , /*0x6F*/
|
|
Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransNull , /*0x77*/
|
|
Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransNull , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack , Vif0TransUnpack /*0x7F*/
|
|
};
|
|
|
|
// Vif0 CMD Table
|
|
void (*Vif0CMDTLB[75])() =
|
|
{
|
|
Vif0CMDNop , Vif0CMDSTCycl , Vif0CMDNull , Vif0CMDNull , Vif0CMDITop , Vif0CMDSTMod , Vif0CMDNull, Vif0CMDMark , /*0x7*/
|
|
Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , /*0xF*/
|
|
Vif0CMDFlushE , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull, Vif0CMDMSCALF, Vif0CMDMSCALF, Vif0CMDNull , Vif0CMDMSCNT, /*0x17*/
|
|
Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , /*0x1F*/
|
|
Vif0CMDSTMask , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , /*0x27*/
|
|
Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , /*0x2F*/
|
|
Vif0CMDSTRowCol, Vif0CMDSTRowCol, Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , /*0x37*/
|
|
Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , /*0x3F*/
|
|
Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , Vif0CMDNull , /*0x47*/
|
|
Vif0CMDNull , Vif0CMDNull , Vif0CMDMPGTransfer
|
|
};
|
|
|
|
void dmaVIF0()
|
|
{
|
|
VIF_LOG("dmaVIF0 chcr = %lx, madr = %lx, qwc = %lx\n"
|
|
" tadr = %lx, asr0 = %lx, asr1 = %lx\n",
|
|
vif0ch->chcr._u32, vif0ch->madr, vif0ch->qwc,
|
|
vif0ch->tadr, vif0ch->asr0, vif0ch->asr1);
|
|
|
|
g_vifCycles = 0;
|
|
|
|
vif0Regs->stat.FQC = 0x8; // FQC=8
|
|
|
|
if (!(vif0ch->chcr.MOD & 0x1) || vif0ch->qwc > 0) // Normal Mode
|
|
{
|
|
if (!_VIF0chain())
|
|
{
|
|
Console.WriteLn(L"Stall on normal vif0 " + vif0Regs->stat.desc());
|
|
|
|
vif0.vifstalled = true;
|
|
return;
|
|
}
|
|
|
|
vif0.done = true;
|
|
CPU_INT(0, /*g_vifCycles*/ VifCycleVoodoo);
|
|
return;
|
|
}
|
|
|
|
// Chain Mode
|
|
vif0.done = false;
|
|
CPU_INT(0, 0);
|
|
}
|
|
|
|
void vif0Write32(u32 mem, u32 value)
|
|
{
|
|
switch (mem)
|
|
{
|
|
case VIF0_MARK:
|
|
VIF_LOG("VIF0_MARK write32 0x%8.8x", value);
|
|
|
|
/* Clear mark flag in VIF0_STAT and set mark with 'value' */
|
|
vif0Regs->stat.MRK = false;
|
|
vif0Regs->mark = value;
|
|
break;
|
|
|
|
case VIF0_FBRST:
|
|
VIF_LOG("VIF0_FBRST write32 0x%8.8x", value);
|
|
|
|
if (value & 0x1) // Reset Vif.
|
|
{
|
|
//Console.WriteLn("Vif0 Reset %x", vif0Regs->stat._u32);
|
|
|
|
memzero(vif0);
|
|
vif0ch->qwc = 0; //?
|
|
cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
|
|
psHu64(VIF0_FIFO) = 0;
|
|
psHu64(VIF0_FIFO + 8) = 0;
|
|
vif0.done = true;
|
|
vif0Regs->err.reset();
|
|
vif0Regs->stat.clear_flags(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
|
|
}
|
|
|
|
if (value & 0x2) // Forcebreak Vif,
|
|
{
|
|
/* I guess we should stop the VIF dma here, but not 100% sure (linuz) */
|
|
cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
|
|
vif0Regs->stat.VFS = true;
|
|
vif0Regs->stat.VPS = VPS_IDLE;
|
|
vif0.vifstalled = true;
|
|
Console.WriteLn("vif0 force break");
|
|
}
|
|
|
|
if (value & 0x4) // Stop Vif.
|
|
{
|
|
// Not completely sure about this, can't remember what game, used this, but 'draining' the VIF helped it, instead of
|
|
// just stoppin the VIF (linuz).
|
|
vif0Regs->stat.VSS = true;
|
|
vif0Regs->stat.VPS = VPS_IDLE;
|
|
vif0.vifstalled = true;
|
|
}
|
|
|
|
if (value & 0x8) // Cancel Vif Stall.
|
|
{
|
|
bool cancel = false;
|
|
|
|
/* Cancel stall, first check if there is a stall to cancel, and then clear VIF0_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
|
|
if (vif0Regs->stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
|
|
cancel = true;
|
|
|
|
vif0Regs->stat.clear_flags(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
|
|
VIF0_STAT_INT | VIF0_STAT_ER0 | VIF0_STAT_ER1);
|
|
if (cancel)
|
|
{
|
|
if (vif0.vifstalled)
|
|
{
|
|
g_vifCycles = 0;
|
|
|
|
// loop necessary for spiderman
|
|
if (vif0.stallontag)
|
|
_chainVIF0();
|
|
else
|
|
_VIF0chain();
|
|
|
|
vif0ch->chcr.STR = true;
|
|
CPU_INT(0, g_vifCycles); // Gets the timing right - Flatout
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case VIF0_ERR:
|
|
// ERR
|
|
VIF_LOG("VIF0_ERR write32 0x%8.8x", value);
|
|
|
|
/* Set VIF0_ERR with 'value' */
|
|
vif0Regs->err.write(value);
|
|
break;
|
|
|
|
case VIF0_R0:
|
|
case VIF0_R1:
|
|
case VIF0_R2:
|
|
case VIF0_R3:
|
|
pxAssume((mem&0xf) == 0);
|
|
g_vifmask.Row0[(mem>>4) & 3] = value;
|
|
break;
|
|
|
|
case VIF0_C0:
|
|
case VIF0_C1:
|
|
case VIF0_C2:
|
|
case VIF0_C3:
|
|
pxAssume((mem&0xf) == 0);
|
|
g_vifmask.Col0[(mem>>4) & 3] = value;
|
|
break;
|
|
|
|
default:
|
|
Console.WriteLn("Unknown Vif0 write to %x", mem);
|
|
psHu32(mem) = value;
|
|
break;
|
|
}
|
|
/* Other registers are read-only so do nothing for them */
|
|
}
|
|
|
|
void vif0Reset()
|
|
{
|
|
/* Reset the whole VIF, meaning the internal pcsx2 vars and all the registers */
|
|
memzero(vif0);
|
|
memzero(*vif0Regs);
|
|
SetNewMask(g_vif0Masks, g_vif0HasMask3, 0, 0xffffffff);
|
|
|
|
psHu64(VIF0_FIFO) = 0;
|
|
psHu64(VIF0_FIFO + 8) = 0;
|
|
|
|
vif0Regs->stat.VPS = VPS_IDLE;
|
|
vif0Regs->stat.FQC = 0;
|
|
|
|
vif0.done = true;
|
|
}
|
|
|
|
void SaveStateBase::vif0Freeze()
|
|
{
|
|
FreezeTag("VIFdma");
|
|
|
|
// Dunno if this one is needed, but whatever, it's small. :)
|
|
Freeze(g_vifCycles);
|
|
|
|
// mask settings for VIF0 and VIF1
|
|
Freeze(g_vifmask);
|
|
|
|
Freeze(vif0);
|
|
Freeze(g_vif0HasMask3);
|
|
Freeze(g_vif0Masks);
|
|
}
|