mirror of
https://github.com/PCSX2/pcsx2.git
synced 2026-01-31 01:15:24 +01:00
ac9bf45f98
Threading VU1 took a lot of rewrites and new code to make possible (MTGS, microVU, gifUnit...), but we finally got to the point where it was feasible, and now we've done it! (so now everyone can stop complaining that pcsx2 only takes advantages of 2 cores :p). The speedups in the games that benefit from it are great if you have a cpu with 3+ cores (generally a 10~45% speedup), however games that are GS limited can be a slowdown (especially on dual core cpu's). The option can be found in the speedhacks section as "MTVU (Multi-Threaded microVU1)". And when enabled it should should show the VU thread-time percentage on the title bar window (Like we currently do for EE/GS/UI threads). It is listed as a speedhack because in order for threading VU1 to have been a speedup, we need to assume that games will not send gif packets containing Signal/Finish/Label commands from path 1 (vu1's xgkick). The good news is very-few games ever do this, so the compatibility of MTVU is very high (a game that does do this will likely hang). Note: vs2010 builds and Linux builds need to be updated to include "MTVU.h" and "MTVU.cpp". git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4865 96395faa-99c1-11dd-bbfe-3dabce05a288
120 lines
3.7 KiB
C++
120 lines
3.7 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "GS.h"
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#include "Gif_Unit.h"
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#include "Vif.h"
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#include "Vif_Dma.h"
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#include "IPU/IPU.h"
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#include "IPU/IPU_Fifo.h"
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//////////////////////////////////////////////////////////////////////////
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/////////////////////////// Quick & dirty FIFO :D ////////////////////////
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//////////////////////////////////////////////////////////////////////////
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// Notes on FIFO implementation
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//
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// The FIFO consists of four separate pages of HW register memory, each mapped to a
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// PS2 device. They are listed as follows:
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//
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// 0x4000 - 0x5000 : VIF0 (all registers map to 0x4000)
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// 0x5000 - 0x6000 : VIF1 (all registers map to 0x5000)
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// 0x6000 - 0x7000 : GS (all registers map to 0x6000)
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// 0x7000 - 0x8000 : IPU (registers map to 0x7000 and 0x7010, respectively)
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void __fastcall ReadFIFO_VIF1(mem128_t* out)
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{
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) )
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DevCon.Warning( "Reading from vif1 fifo when stalled" );
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ZeroQWC(out); // Clear first in case no data gets written...
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pxAssertRel(vif1Regs.stat.FQC != 0, "FQC = 0 on VIF FIFO READ!");
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if (vif1Regs.stat.FDR) {
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if (vif1Regs.stat.FQC > vif1.GSLastDownloadSize) {
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DevCon.Warning("Warning! GS Download size < FIFO count!");
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}
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if (vif1Regs.stat.FQC > 0) {
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GetMTGS().WaitGS();
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GSreadFIFO((u64*)out);
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vif1.GSLastDownloadSize--;
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GUNIT_LOG("ReadFIFO_VIF1");
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if (vif1.GSLastDownloadSize <= 16)
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gifRegs.stat.OPH = false;
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vif1Regs.stat.FQC = min((u32)16, vif1.GSLastDownloadSize);
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}
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}
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VIF_LOG("ReadFIFO/VIF1 -> %ls", out->ToString().c_str());
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}
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//////////////////////////////////////////////////////////////////////////
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// WriteFIFO Pages
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//
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void __fastcall WriteFIFO_VIF0(const mem128_t *value)
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{
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VIF_LOG("WriteFIFO/VIF0 <- %ls", value->ToString().c_str());
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vif0ch.qwc += 1;
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if(vif0.irqoffset != 0 && vif0.vifstalled == true) DevCon.Warning("Offset on VIF0 FIFO start!");
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bool ret = VIF0transfer((u32*)value, 4);
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if (vif0.cmd)
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{
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if(vif0.done && vif0ch.qwc == 0) vif0Regs.stat.VPS = VPS_WAITING;
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}
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else
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{
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vif0Regs.stat.VPS = VPS_IDLE;
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}
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pxAssertDev( ret, "vif stall code not implemented" );
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}
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void __fastcall WriteFIFO_VIF1(const mem128_t *value)
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{
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VIF_LOG("WriteFIFO/VIF1 <- %ls", value->ToString().c_str());
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if (vif1Regs.stat.FDR) {
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DevCon.Warning("writing to fifo when fdr is set!");
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}
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) ) {
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DevCon.Warning("writing to vif1 fifo when stalled");
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}
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if (vif1.irqoffset != 0 && vif1.vifstalled == true) {
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DevCon.Warning("Offset on VIF1 FIFO start!");
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}
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vif1ch.qwc += 1;
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bool ret = VIF1transfer((u32*)value, 4);
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if (vif1.cmd) {
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if (vif1.done && !vif1ch.qwc) vif1Regs.stat.VPS = VPS_WAITING;
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}
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else vif1Regs.stat.VPS = VPS_IDLE;
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pxAssertDev( ret, "vif stall code not implemented" );
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}
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void __fastcall WriteFIFO_GIF(const mem128_t *value)
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{
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GUNIT_LOG("WriteFIFO_GIF()");
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gifUnit.TransferGSPacketData(GIF_TRANS_FIFO, (u8*)value, 16);
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}
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