From 6bb7361fa1fcadb6177da4657a78c44a2fb2c454 Mon Sep 17 00:00:00 2001
From: TheLastRar <TheLastRar@users.noreply.github.com>
Date: Fri, 18 Sep 2026 13:14:55 +0100
Subject: [PATCH] 3rdparty/vixl: Re-add compile fixes

These got removed during an update
---
 .../include/vixl/aarch64/constants-aarch64.h  | 515 +++++++++---------
 1 file changed, 260 insertions(+), 255 deletions(-)

diff --git a/3rdparty/vixl/include/vixl/aarch64/constants-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/constants-aarch64.h
index 279587cf3f..938d7c5196 100644
--- a/3rdparty/vixl/include/vixl/aarch64/constants-aarch64.h
+++ b/3rdparty/vixl/include/vixl/aarch64/constants-aarch64.h
@@ -27,6 +27,11 @@
 #ifndef VIXL_AARCH64_CONSTANTS_AARCH64_H_
 #define VIXL_AARCH64_CONSTANTS_AARCH64_H_
 
+#ifdef __clang__
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wdeprecated-enum-enum-conversion"
+#endif
+
 #include "../globals-vixl.h"
 
 namespace vixl {
@@ -497,7 +502,7 @@ class SystemRegisterEncoder {
 // System/special register names.
 // This information is not encoded as one field but as the concatenation of
 // multiple fields (Op0, Op1, Crn, Crm, Op2).
-enum SystemRegister {
+enum SystemRegister : uint32_t {
   NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value,
   FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value,
   RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value,    // Random number.
@@ -515,11 +520,11 @@ class CacheOpEncoder {
        (op2 << SysOp2_offset)) >> SysOp_offset;
 };
 
-enum InstructionCacheOp {
+enum InstructionCacheOp : uint32_t {
   IVAU = CacheOpEncoder<3, 7, 5, 1>::value
 };
 
-enum DataCacheOp {
+enum DataCacheOp : uint32_t {
   CVAC = CacheOpEncoder<3, 7, 10, 1>::value,
   CVAU = CacheOpEncoder<3, 7, 11, 1>::value,
   CVAP = CacheOpEncoder<3, 7, 12, 1>::value,
@@ -536,7 +541,7 @@ enum DataCacheOp {
   CIGDVAC = CacheOpEncoder<3, 7, 14, 5>::value
 };
 
-enum GCSOp {
+enum GCSOp : uint32_t {
   GCSPUSHM = CacheOpEncoder<3, 7, 7, 0>::value,
   GCSPOPM = CacheOpEncoder<3, 7, 7, 1>::value,
   GCSSS1 = CacheOpEncoder<3, 7, 7, 2>::value,
@@ -594,7 +599,7 @@ enum SVEPredicateConstraint {
 
 
 // Generic fields.
-enum GenericInstrField {
+enum GenericInstrField : uint32_t {
   SixtyFourBits        = 0x80000000,
   ThirtyTwoBits        = 0x00000000,
 
@@ -604,7 +609,7 @@ enum GenericInstrField {
   FP64                 = 0x00400000
 };
 
-enum NEONFormatField {
+enum NEONFormatField : uint32_t {
   NEONFormatFieldMask   = 0x40C00000,
   NEON_Q                = 0x40000000,
   NEON_8B               = 0x00000000,
@@ -617,7 +622,7 @@ enum NEONFormatField {
   NEON_2D               = 0x00C00000 | NEON_Q
 };
 
-enum NEONFPFormatField {
+enum NEONFPFormatField : uint32_t {
   NEONFPFormatFieldMask = 0x40400000,
   NEON_FP_4H            = FP16,
   NEON_FP_2S            = FP32,
@@ -626,7 +631,7 @@ enum NEONFPFormatField {
   NEON_FP_2D            = FP64 | NEON_Q
 };
 
-enum NEONLSFormatField {
+enum NEONLSFormatField : uint32_t {
   NEONLSFormatFieldMask = 0x40000C00,
   LS_NEON_8B            = 0x00000000,
   LS_NEON_16B           = LS_NEON_8B | NEON_Q,
@@ -638,7 +643,7 @@ enum NEONLSFormatField {
   LS_NEON_2D            = LS_NEON_1D | NEON_Q
 };
 
-enum NEONScalarFormatField {
+enum NEONScalarFormatField : uint32_t {
   NEONScalarFormatFieldMask = 0x00C00000,
   NEONScalar                = 0x10000000,
   NEON_B                    = 0x00000000,
@@ -647,7 +652,7 @@ enum NEONScalarFormatField {
   NEON_D                    = 0x00C00000
 };
 
-enum SVESizeField {
+enum SVESizeField : uint32_t {
   SVESizeFieldMask = 0x00C00000,
   SVE_B            = 0x00000000,
   SVE_H            = 0x00400000,
@@ -656,7 +661,7 @@ enum SVESizeField {
 };
 
 // PC relative addressing.
-enum PCRelAddressingOp {
+enum PCRelAddressingOp : uint32_t {
   PCRelAddressingFixed = 0x10000000,
   PCRelAddressingFMask = 0x1F000000,
   PCRelAddressingMask  = 0x9F000000,
@@ -666,7 +671,7 @@ enum PCRelAddressingOp {
 
 // Add/sub (immediate, shifted and extended.)
 const int kSFOffset = 31;
-enum AddSubOp {
+enum AddSubOp : uint32_t {
   AddSubOpMask      = 0x60000000,
   AddSubSetFlagsBit = 0x20000000,
   ADD               = 0x00000000,
@@ -681,7 +686,7 @@ enum AddSubOp {
   V(SUB),                   \
   V(SUBS)
 
-enum AddSubImmediateOp {
+enum AddSubImmediateOp : uint32_t {
   AddSubImmediateFixed = 0x11000000,
   AddSubImmediateFMask = 0x1F800000,
   AddSubImmediateMask  = 0xFF800000,
@@ -692,7 +697,7 @@ enum AddSubImmediateOp {
   #undef ADD_SUB_IMMEDIATE
 };
 
-enum AddSubShiftedOp {
+enum AddSubShiftedOp : uint32_t  {
   AddSubShiftedFixed   = 0x0B000000,
   AddSubShiftedFMask   = 0x1F200000,
   AddSubShiftedMask    = 0xFF200000,
@@ -703,7 +708,7 @@ enum AddSubShiftedOp {
   #undef ADD_SUB_SHIFTED
 };
 
-enum AddSubExtendedOp {
+enum AddSubExtendedOp : uint32_t {
   AddSubExtendedFixed  = 0x0B200000,
   AddSubExtendedFMask  = 0x1F200000,
   AddSubExtendedMask   = 0xFFE00000,
@@ -715,7 +720,7 @@ enum AddSubExtendedOp {
 };
 
 // Add/sub with carry.
-enum AddSubWithCarryOp {
+enum AddSubWithCarryOp : uint32_t {
   AddSubWithCarryFixed = 0x1A000000,
   AddSubWithCarryFMask = 0x1FE00000,
   AddSubWithCarryMask  = 0xFFE0FC00,
@@ -732,7 +737,7 @@ enum AddSubWithCarryOp {
 };
 
 // Rotate right into flags.
-enum RotateRightIntoFlagsOp {
+enum RotateRightIntoFlagsOp : uint32_t {
   RotateRightIntoFlagsFixed = 0x1A000400,
   RotateRightIntoFlagsFMask = 0x1FE07C00,
   RotateRightIntoFlagsMask  = 0xFFE07C10,
@@ -740,7 +745,7 @@ enum RotateRightIntoFlagsOp {
 };
 
 // Evaluate into flags.
-enum EvaluateIntoFlagsOp {
+enum EvaluateIntoFlagsOp : uint32_t {
   EvaluateIntoFlagsFixed = 0x1A000800,
   EvaluateIntoFlagsFMask = 0x1FE03C00,
   EvaluateIntoFlagsMask  = 0xFFE07C1F,
@@ -750,7 +755,7 @@ enum EvaluateIntoFlagsOp {
 
 
 // Logical (immediate and shifted register).
-enum LogicalOp {
+enum LogicalOp : uint32_t {
   LogicalOpMask = 0x60200000,
   NOT   = 0x00200000,
   AND   = 0x00000000,
@@ -764,7 +769,7 @@ enum LogicalOp {
 };
 
 // Logical immediate.
-enum LogicalImmediateOp {
+enum LogicalImmediateOp : uint32_t {
   LogicalImmediateFixed = 0x12000000,
   LogicalImmediateFMask = 0x1F800000,
   LogicalImmediateMask  = 0xFF800000,
@@ -779,7 +784,7 @@ enum LogicalImmediateOp {
 };
 
 // Logical shifted register.
-enum LogicalShiftedOp {
+enum LogicalShiftedOp : uint32_t {
   LogicalShiftedFixed = 0x0A000000,
   LogicalShiftedFMask = 0x1F000000,
   LogicalShiftedMask  = 0xFF200000,
@@ -810,7 +815,7 @@ enum LogicalShiftedOp {
 };
 
 // Move wide immediate.
-enum MoveWideImmediateOp {
+enum MoveWideImmediateOp : uint32_t {
   MoveWideImmediateFixed = 0x12800000,
   MoveWideImmediateFMask = 0x1F800000,
   MoveWideImmediateMask  = 0xFF800000,
@@ -827,7 +832,7 @@ enum MoveWideImmediateOp {
 
 // Bitfield.
 const int kBitfieldNOffset = 22;
-enum BitfieldOp {
+enum BitfieldOp : uint32_t {
   BitfieldFixed = 0x13000000,
   BitfieldFMask = 0x1F800000,
   BitfieldMask  = 0xFF800000,
@@ -844,7 +849,7 @@ enum BitfieldOp {
 };
 
 // Extract.
-enum ExtractOp {
+enum ExtractOp : uint32_t {
   ExtractFixed = 0x13800000,
   ExtractFMask = 0x1F800000,
   ExtractMask  = 0xFFA00000,
@@ -854,7 +859,7 @@ enum ExtractOp {
 };
 
 // Unconditional branch.
-enum UnconditionalBranchOp {
+enum UnconditionalBranchOp : uint32_t {
   UnconditionalBranchFixed = 0x14000000,
   UnconditionalBranchFMask = 0x7C000000,
   UnconditionalBranchMask  = 0xFC000000,
@@ -863,7 +868,7 @@ enum UnconditionalBranchOp {
 };
 
 // Unconditional branch to register.
-enum UnconditionalBranchToRegisterOp {
+enum UnconditionalBranchToRegisterOp : uint32_t {
   UnconditionalBranchToRegisterFixed = 0xD6000000,
   UnconditionalBranchToRegisterFMask = 0xFE000000,
   UnconditionalBranchToRegisterMask  = 0xFFFFFC00,
@@ -884,7 +889,7 @@ enum UnconditionalBranchToRegisterOp {
 };
 
 // Compare and branch.
-enum CompareBranchOp {
+enum CompareBranchOp : uint32_t {
   CompareBranchFixed = 0x34000000,
   CompareBranchFMask = 0x7E000000,
   CompareBranchMask  = 0xFF000000,
@@ -897,7 +902,7 @@ enum CompareBranchOp {
 };
 
 // Test and branch.
-enum TestBranchOp {
+enum TestBranchOp : uint32_t {
   TestBranchFixed = 0x36000000,
   TestBranchFMask = 0x7E000000,
   TestBranchMask  = 0x7F000000,
@@ -906,7 +911,7 @@ enum TestBranchOp {
 };
 
 // Conditional branch.
-enum ConditionalBranchOp {
+enum ConditionalBranchOp : uint32_t {
   ConditionalBranchFixed = 0x54000000,
   ConditionalBranchFMask = 0xFE000000,
   ConditionalBranchMask  = 0xFF000010,
@@ -918,12 +923,12 @@ enum ConditionalBranchOp {
 // and CR fields to encode parameters. To handle this cleanly, the system
 // instructions are split into more than one enum.
 
-enum SystemOp {
+enum SystemOp : uint32_t {
   SystemFixed = 0xD5000000,
   SystemFMask = 0xFFC00000
 };
 
-enum SystemSysRegOp {
+enum SystemSysRegOp : uint32_t {
   SystemSysRegFixed = 0xD5100000,
   SystemSysRegFMask = 0xFFD00000,
   SystemSysRegMask  = 0xFFF00000,
@@ -931,7 +936,7 @@ enum SystemSysRegOp {
   MSR               = SystemSysRegFixed | 0x00000000
 };
 
-enum SystemPStateOp {
+enum SystemPStateOp : uint32_t {
   SystemPStateFixed = 0xD5004000,
   SystemPStateFMask = 0xFFF8F000,
   SystemPStateMask  = 0xFFFFF0FF,
@@ -940,14 +945,14 @@ enum SystemPStateOp {
   AXFLAG            = SystemPStateFixed | 0x0000005F
 };
 
-enum SystemHintOp {
+enum SystemHintOp : uint32_t {
   SystemHintFixed = 0xD503201F,
   SystemHintFMask = 0xFFFFF01F,
   SystemHintMask  = 0xFFFFF01F,
   HINT            = SystemHintFixed | 0x00000000
 };
 
-enum SystemSysOp {
+enum SystemSysOp : uint32_t {
   SystemSysFixed  = 0xD5080000,
   SystemSysFMask  = 0xFFF80000,
   SystemSysMask   = 0xFFF80000,
@@ -956,7 +961,7 @@ enum SystemSysOp {
 };
 
 // Exception.
-enum ExceptionOp {
+enum ExceptionOp : uint32_t {
   ExceptionFixed = 0xD4000000,
   ExceptionFMask = 0xFF000000,
   ExceptionMask  = 0xFFE0001F,
@@ -970,7 +975,7 @@ enum ExceptionOp {
   DCPS3          = ExceptionFixed | 0x00A00003
 };
 
-enum MemBarrierOp {
+enum MemBarrierOp : uint32_t {
   MemBarrierFixed = 0xD503309F,
   MemBarrierFMask = 0xFFFFF09F,
   MemBarrierMask  = 0xFFFFF0FF,
@@ -979,14 +984,14 @@ enum MemBarrierOp {
   ISB             = MemBarrierFixed | 0x00000040
 };
 
-enum SystemExclusiveMonitorOp {
+enum SystemExclusiveMonitorOp : uint32_t {
   SystemExclusiveMonitorFixed = 0xD503305F,
   SystemExclusiveMonitorFMask = 0xFFFFF0FF,
   SystemExclusiveMonitorMask  = 0xFFFFF0FF,
   CLREX                       = SystemExclusiveMonitorFixed
 };
 
-enum SystemPAuthOp {
+enum SystemPAuthOp : uint32_t {
   SystemPAuthFixed = 0xD503211F,
   SystemPAuthFMask = 0xFFFFFD1F,
   SystemPAuthMask  = 0xFFFFFFFF,
@@ -1009,13 +1014,13 @@ enum SystemPAuthOp {
 };
 
 // Any load or store.
-enum LoadStoreAnyOp {
+enum LoadStoreAnyOp : uint32_t {
   LoadStoreAnyFMask = 0x0a000000,
   LoadStoreAnyFixed = 0x08000000
 };
 
 // Any load pair or store pair.
-enum LoadStorePairAnyOp {
+enum LoadStorePairAnyOp : uint32_t {
   LoadStorePairAnyFMask = 0x3a000000,
   LoadStorePairAnyFixed = 0x28000000
 };
@@ -1034,7 +1039,7 @@ enum LoadStorePairAnyOp {
   V(LDP, q,   0x84400000)
 
 // Load/store pair (post, pre and offset.)
-enum LoadStorePairOp {
+enum LoadStorePairOp : uint32_t {
   LoadStorePairMask = 0xC4400000,
   LoadStorePairLBit = 1 << 22,
   #define LOAD_STORE_PAIR(A, B, C) \
@@ -1043,7 +1048,7 @@ enum LoadStorePairOp {
   #undef LOAD_STORE_PAIR
 };
 
-enum LoadStorePairPostIndexOp {
+enum LoadStorePairPostIndexOp : uint32_t {
   LoadStorePairPostIndexFixed = 0x28800000,
   LoadStorePairPostIndexFMask = 0x3B800000,
   LoadStorePairPostIndexMask  = 0xFFC00000,
@@ -1053,7 +1058,7 @@ enum LoadStorePairPostIndexOp {
   #undef LOAD_STORE_PAIR_POST_INDEX
 };
 
-enum LoadStorePairPreIndexOp {
+enum LoadStorePairPreIndexOp : uint32_t {
   LoadStorePairPreIndexFixed = 0x29800000,
   LoadStorePairPreIndexFMask = 0x3B800000,
   LoadStorePairPreIndexMask  = 0xFFC00000,
@@ -1063,7 +1068,7 @@ enum LoadStorePairPreIndexOp {
   #undef LOAD_STORE_PAIR_PRE_INDEX
 };
 
-enum LoadStorePairOffsetOp {
+enum LoadStorePairOffsetOp : uint32_t {
   LoadStorePairOffsetFixed = 0x29000000,
   LoadStorePairOffsetFMask = 0x3B800000,
   LoadStorePairOffsetMask  = 0xFFC00000,
@@ -1073,7 +1078,7 @@ enum LoadStorePairOffsetOp {
   #undef LOAD_STORE_PAIR_OFFSET
 };
 
-enum LoadStorePairNonTemporalOp {
+enum LoadStorePairNonTemporalOp : uint32_t {
   LoadStorePairNonTemporalFixed = 0x28000000,
   LoadStorePairNonTemporalFMask = 0x3B800000,
   LoadStorePairNonTemporalMask  = 0xFFC00000,
@@ -1091,7 +1096,7 @@ enum LoadStorePairNonTemporalOp {
 };
 
 // Load with pointer authentication.
-enum LoadStorePACOp {
+enum LoadStorePACOp : uint32_t {
   LoadStorePACFixed  = 0xF8200400,
   LoadStorePACFMask  = 0xFF200400,
   LoadStorePACMask   = 0xFFA00C00,
@@ -1103,7 +1108,7 @@ enum LoadStorePACOp {
 };
 
 // Load literal.
-enum LoadLiteralOp {
+enum LoadLiteralOp : uint32_t {
   LoadLiteralFixed = 0x18000000,
   LoadLiteralFMask = 0x3B000000,
   LoadLiteralMask  = 0xFF000000,
@@ -1142,7 +1147,7 @@ enum LoadLiteralOp {
   V(LD, R, q,   0x04C00000)
 
 // Load/store (post, pre, offset and unsigned.)
-enum LoadStoreOp {
+enum LoadStoreOp : uint32_t {
   LoadStoreMask = 0xC4C00000,
   LoadStoreVMask = 0x04000000,
   #define LOAD_STORE(A, B, C, D)  \
@@ -1153,7 +1158,7 @@ enum LoadStoreOp {
 };
 
 // Load/store unscaled offset.
-enum LoadStoreUnscaledOffsetOp {
+enum LoadStoreUnscaledOffsetOp : uint32_t {
   LoadStoreUnscaledOffsetFixed = 0x38000000,
   LoadStoreUnscaledOffsetFMask = 0x3B200C00,
   LoadStoreUnscaledOffsetMask  = 0xFFE00C00,
@@ -1165,7 +1170,7 @@ enum LoadStoreUnscaledOffsetOp {
 };
 
 // Load/store post index.
-enum LoadStorePostIndex {
+enum LoadStorePostIndex : uint32_t {
   LoadStorePostIndexFixed = 0x38000400,
   LoadStorePostIndexFMask = 0x3B200C00,
   LoadStorePostIndexMask  = 0xFFE00C00,
@@ -1176,7 +1181,7 @@ enum LoadStorePostIndex {
 };
 
 // Load/store pre index.
-enum LoadStorePreIndex {
+enum LoadStorePreIndex : uint32_t {
   LoadStorePreIndexFixed = 0x38000C00,
   LoadStorePreIndexFMask = 0x3B200C00,
   LoadStorePreIndexMask  = 0xFFE00C00,
@@ -1187,7 +1192,7 @@ enum LoadStorePreIndex {
 };
 
 // Load/store unsigned offset.
-enum LoadStoreUnsignedOffset {
+enum LoadStoreUnsignedOffset : uint32_t {
   LoadStoreUnsignedOffsetFixed = 0x39000000,
   LoadStoreUnsignedOffsetFMask = 0x3B000000,
   LoadStoreUnsignedOffsetMask  = 0xFFC00000,
@@ -1199,7 +1204,7 @@ enum LoadStoreUnsignedOffset {
 };
 
 // Load/store register offset.
-enum LoadStoreRegisterOffset {
+enum LoadStoreRegisterOffset : uint32_t {
   LoadStoreRegisterOffsetFixed = 0x38200800,
   LoadStoreRegisterOffsetFMask = 0x3B200C00,
   LoadStoreRegisterOffsetMask  = 0xFFE00C00,
@@ -1210,7 +1215,7 @@ enum LoadStoreRegisterOffset {
   #undef LOAD_STORE_REGISTER_OFFSET
 };
 
-enum LoadStoreExclusive {
+enum LoadStoreExclusive : uint32_t {
   LoadStoreExclusiveFixed = 0x08000000,
   LoadStoreExclusiveFMask = 0x3F000000,
   LoadStoreExclusiveMask  = 0xFFE08000,
@@ -1292,7 +1297,7 @@ enum LoadStoreExclusive {
 };
 
 // Load/store RCpc unscaled offset.
-enum LoadStoreRCpcUnscaledOffsetOp {
+enum LoadStoreRCpcUnscaledOffsetOp : uint32_t {
   LoadStoreRCpcUnscaledOffsetFixed = 0x19000000,
   LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00,
   LoadStoreRCpcUnscaledOffsetMask  = 0xFFE00C00,
@@ -1322,7 +1327,7 @@ enum LoadStoreRCpcUnscaledOffsetOp {
   V(LDUMIN, 0x00007000)
 
 // Atomic memory.
-enum AtomicMemoryOp {
+enum AtomicMemoryOp : uint32_t {
   AtomicMemoryFixed = 0x38200000,
   AtomicMemoryFMask = 0x3B200C00,
   AtomicMemoryMask = 0xFFE0FC00,
@@ -1373,14 +1378,14 @@ enum AtomicMemoryOp {
 };
 
 // Conditional compare.
-enum ConditionalCompareOp {
+enum ConditionalCompareOp : uint32_t {
   ConditionalCompareMask = 0x60000000,
   CCMN                   = 0x20000000,
   CCMP                   = 0x60000000
 };
 
 // Conditional compare register.
-enum ConditionalCompareRegisterOp {
+enum ConditionalCompareRegisterOp : uint32_t {
   ConditionalCompareRegisterFixed = 0x1A400000,
   ConditionalCompareRegisterFMask = 0x1FE00800,
   ConditionalCompareRegisterMask  = 0xFFE00C10,
@@ -1391,7 +1396,7 @@ enum ConditionalCompareRegisterOp {
 };
 
 // Conditional compare immediate.
-enum ConditionalCompareImmediateOp {
+enum ConditionalCompareImmediateOp : uint32_t {
   ConditionalCompareImmediateFixed = 0x1A400800,
   ConditionalCompareImmediateFMask = 0x1FE00800,
   ConditionalCompareImmediateMask  = 0xFFE00C10,
@@ -1402,7 +1407,7 @@ enum ConditionalCompareImmediateOp {
 };
 
 // Conditional select.
-enum ConditionalSelectOp {
+enum ConditionalSelectOp : uint32_t {
   ConditionalSelectFixed = 0x1A800000,
   ConditionalSelectFMask = 0x1FE00000,
   ConditionalSelectMask  = 0xFFE00C00,
@@ -1421,7 +1426,7 @@ enum ConditionalSelectOp {
 };
 
 // Data processing 1 source.
-enum DataProcessing1SourceOp {
+enum DataProcessing1SourceOp : uint32_t {
   DataProcessing1SourceFixed = 0x5AC00000,
   DataProcessing1SourceFMask = 0x5FE00000,
   DataProcessing1SourceMask  = 0xFFFFFC00,
@@ -1464,7 +1469,7 @@ enum DataProcessing1SourceOp {
 };
 
 // Data processing 2 source.
-enum DataProcessing2SourceOp {
+enum DataProcessing2SourceOp : uint32_t {
   DataProcessing2SourceFixed = 0x1AC00000,
   DataProcessing2SourceFMask = 0x5FE00000,
   DataProcessing2SourceMask  = 0xFFE0FC00,
@@ -1498,7 +1503,7 @@ enum DataProcessing2SourceOp {
 };
 
 // Data processing 3 source.
-enum DataProcessing3SourceOp {
+enum DataProcessing3SourceOp : uint32_t {
   DataProcessing3SourceFixed = 0x1B000000,
   DataProcessing3SourceFMask = 0x1F000000,
   DataProcessing3SourceMask  = 0xFFE08000,
@@ -1517,7 +1522,7 @@ enum DataProcessing3SourceOp {
 };
 
 // Floating point compare.
-enum FPCompareOp {
+enum FPCompareOp : uint32_t {
   FPCompareFixed = 0x1E202000,
   FPCompareFMask = 0x5F203C00,
   FPCompareMask  = 0xFFE0FC1F,
@@ -1540,7 +1545,7 @@ enum FPCompareOp {
 };
 
 // Floating point conditional compare.
-enum FPConditionalCompareOp {
+enum FPConditionalCompareOp : uint32_t {
   FPConditionalCompareFixed = 0x1E200400,
   FPConditionalCompareFMask = 0x5F200C00,
   FPConditionalCompareMask  = 0xFFE00C10,
@@ -1555,7 +1560,7 @@ enum FPConditionalCompareOp {
 };
 
 // Floating point conditional select.
-enum FPConditionalSelectOp {
+enum FPConditionalSelectOp : uint32_t {
   FPConditionalSelectFixed = 0x1E200C00,
   FPConditionalSelectFMask = 0x5F200C00,
   FPConditionalSelectMask  = 0xFFE00C00,
@@ -1566,7 +1571,7 @@ enum FPConditionalSelectOp {
 };
 
 // Floating point immediate.
-enum FPImmediateOp {
+enum FPImmediateOp : uint32_t {
   FPImmediateFixed = 0x1E201000,
   FPImmediateFMask = 0x5F201C00,
   FPImmediateMask  = 0xFFE01C00,
@@ -1576,7 +1581,7 @@ enum FPImmediateOp {
 };
 
 // Floating point data processing 1 source.
-enum FPDataProcessing1SourceOp {
+enum FPDataProcessing1SourceOp : uint32_t {
   FPDataProcessing1SourceFixed = 0x1E204000,
   FPDataProcessing1SourceFMask = 0x5F207C00,
   FPDataProcessing1SourceMask  = 0xFFFFFC00,
@@ -1645,7 +1650,7 @@ enum FPDataProcessing1SourceOp {
 };
 
 // Floating point data processing 2 source.
-enum FPDataProcessing2SourceOp {
+enum FPDataProcessing2SourceOp : uint32_t {
   FPDataProcessing2SourceFixed = 0x1E200800,
   FPDataProcessing2SourceFMask = 0x5F200C00,
   FPDataProcessing2SourceMask  = 0xFFE0FC00,
@@ -1688,7 +1693,7 @@ enum FPDataProcessing2SourceOp {
 };
 
 // Floating point data processing 3 source.
-enum FPDataProcessing3SourceOp {
+enum FPDataProcessing3SourceOp : uint32_t {
   FPDataProcessing3SourceFixed = 0x1F000000,
   FPDataProcessing3SourceFMask = 0x5F000000,
   FPDataProcessing3SourceMask  = 0xFFE08000,
@@ -1707,7 +1712,7 @@ enum FPDataProcessing3SourceOp {
 };
 
 // Conversion between floating point and integer.
-enum FPIntegerConvertOp {
+enum FPIntegerConvertOp : uint32_t {
   FPIntegerConvertFixed = 0x1E200000,
   FPIntegerConvertFMask = 0x5F20FC00,
   FPIntegerConvertMask  = 0xFFFFFC00,
@@ -1809,7 +1814,7 @@ enum FPIntegerConvertOp {
 };
 
 // Conversion between fixed point and floating point.
-enum FPFixedPointConvertOp {
+enum FPFixedPointConvertOp : uint32_t {
   FPFixedPointConvertFixed = 0x1E000000,
   FPFixedPointConvertFMask = 0x5F200000,
   FPFixedPointConvertMask  = 0xFFFF0000,
@@ -1844,25 +1849,25 @@ enum FPFixedPointConvertOp {
 };
 
 // Crypto - two register SHA.
-enum Crypto2RegSHAOp {
+enum Crypto2RegSHAOp : uint32_t {
   Crypto2RegSHAFixed = 0x5E280800,
   Crypto2RegSHAFMask = 0xFF3E0C00
 };
 
 // Crypto - three register SHA.
-enum Crypto3RegSHAOp {
+enum Crypto3RegSHAOp : uint32_t {
   Crypto3RegSHAFixed = 0x5E000000,
   Crypto3RegSHAFMask = 0xFF208C00
 };
 
 // Crypto - AES.
-enum CryptoAESOp {
+enum CryptoAESOp : uint32_t {
   CryptoAESFixed = 0x4E280800,
   CryptoAESFMask = 0xFF3E0C00
 };
 
 // NEON instructions with two register operands.
-enum NEON2RegMiscOp {
+enum NEON2RegMiscOp : uint32_t {
   NEON2RegMiscFixed = 0x0E200800,
   NEON2RegMiscFMask = 0x9F3E0C00,
   NEON2RegMiscMask  = 0xBF3FFC00,
@@ -1948,7 +1953,7 @@ enum NEON2RegMiscOp {
 };
 
 // NEON instructions with two register operands (FP16).
-enum NEON2RegMiscFP16Op {
+enum NEON2RegMiscFP16Op : uint32_t {
   NEON2RegMiscFP16Fixed = 0x0E780800,
   NEON2RegMiscFP16FMask = 0x9F7E0C00,
   NEON2RegMiscFP16Mask  = 0xBFFFFC00,
@@ -1984,7 +1989,7 @@ enum NEON2RegMiscFP16Op {
 };
 
 // NEON instructions with three same-type operands.
-enum NEON3SameOp {
+enum NEON3SameOp : uint32_t {
   NEON3SameFixed = 0x0E200400,
   NEON3SameFMask = 0x9F200400,
   NEON3SameMask =  0xBF20FC00,
@@ -2087,7 +2092,7 @@ enum NEON3SameOp {
 };
 
 
-enum NEON3SameFP16 {
+enum NEON3SameFP16 : uint32_t {
   NEON3SameFP16Fixed = 0x0E400400,
   NEON3SameFP16FMask = 0x9F60C400,
   NEON3SameFP16Mask =  0xBFE0FC00,
@@ -2119,7 +2124,7 @@ enum NEON3SameFP16 {
 
 
 // 'Extra' NEON instructions with three same-type operands.
-enum NEON3SameExtraOp {
+enum NEON3SameExtraOp : uint32_t {
   NEON3SameExtraFixed = 0x0E008400,
   NEON3SameExtraUBit = 0x20000000,
   NEON3SameExtraFMask = 0x9E208400,
@@ -2142,7 +2147,7 @@ enum NEON3SameExtraOp {
 };
 
 // NEON instructions with three different-type operands.
-enum NEON3DifferentOp {
+enum NEON3DifferentOp : uint32_t {
   NEON3DifferentFixed = 0x0E200000,
   NEON3DifferentFMask = 0x9F200C00,
   NEON3DifferentMask  = 0xFF20FC00,
@@ -2201,7 +2206,7 @@ enum NEON3DifferentOp {
 };
 
 // NEON instructions operating across vectors.
-enum NEONAcrossLanesOp {
+enum NEONAcrossLanesOp : uint32_t {
   NEONAcrossLanesFixed = 0x0E300800,
   NEONAcrossLanesFMask = 0x9F3E0C00,
   NEONAcrossLanesMask  = 0xBF3FFC00,
@@ -2233,7 +2238,7 @@ enum NEONAcrossLanesOp {
 };
 
 // NEON instructions with indexed element operand.
-enum NEONByIndexedElementOp {
+enum NEONByIndexedElementOp : uint32_t {
   NEONByIndexedElementFixed = 0x0F000000,
   NEONByIndexedElementFMask = 0x9F000400,
   NEONByIndexedElementMask  = 0xBF00F400,
@@ -2287,7 +2292,7 @@ enum NEONByIndexedElementOp {
 };
 
 // NEON register copy.
-enum NEONCopyOp {
+enum NEONCopyOp : uint32_t {
   NEONCopyFixed = 0x0E000400,
   NEONCopyFMask = 0x9FE08400,
   NEONCopyMask  = 0x3FE08400,
@@ -2306,14 +2311,14 @@ enum NEONCopyOp {
 };
 
 // NEON extract.
-enum NEONExtractOp {
+enum NEONExtractOp : uint32_t {
   NEONExtractFixed = 0x2E000000,
   NEONExtractFMask = 0xBF208400,
   NEONExtractMask =  0xBFE08400,
   NEON_EXT = NEONExtractFixed | 0x00000000
 };
 
-enum NEONLoadStoreMultiOp {
+enum NEONLoadStoreMultiOp : uint32_t {
   NEONLoadStoreMultiL    = 0x00400000,
   NEONLoadStoreMulti1_1v = 0x00007000,
   NEONLoadStoreMulti1_2v = 0x0000A000,
@@ -2325,7 +2330,7 @@ enum NEONLoadStoreMultiOp {
 };
 
 // NEON load/store multiple structures.
-enum NEONLoadStoreMultiStructOp {
+enum NEONLoadStoreMultiStructOp : uint32_t {
   NEONLoadStoreMultiStructFixed = 0x0C000000,
   NEONLoadStoreMultiStructFMask = 0xBFBF0000,
   NEONLoadStoreMultiStructMask  = 0xBFFFF000,
@@ -2349,7 +2354,7 @@ enum NEONLoadStoreMultiStructOp {
 };
 
 // NEON load/store multiple structures with post-index addressing.
-enum NEONLoadStoreMultiStructPostIndexOp {
+enum NEONLoadStoreMultiStructPostIndexOp : uint32_t {
   NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
   NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
   NEONLoadStoreMultiStructPostIndexMask  = 0xBFE0F000,
@@ -2370,7 +2375,7 @@ enum NEONLoadStoreMultiStructPostIndexOp {
   NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
 };
 
-enum NEONLoadStoreSingleOp {
+enum NEONLoadStoreSingleOp : uint32_t {
   NEONLoadStoreSingle1        = 0x00000000,
   NEONLoadStoreSingle2        = 0x00200000,
   NEONLoadStoreSingle3        = 0x00002000,
@@ -2385,7 +2390,7 @@ enum NEONLoadStoreSingleOp {
 };
 
 // NEON load/store single structure.
-enum NEONLoadStoreSingleStructOp {
+enum NEONLoadStoreSingleStructOp : uint32_t {
   NEONLoadStoreSingleStructFixed = 0x0D000000,
   NEONLoadStoreSingleStructFMask = 0xBF9F0000,
   NEONLoadStoreSingleStructMask  = 0xBFFFE000,
@@ -2450,7 +2455,7 @@ enum NEONLoadStoreSingleStructOp {
 };
 
 // NEON load/store single structure with post-index addressing.
-enum NEONLoadStoreSingleStructPostIndexOp {
+enum NEONLoadStoreSingleStructPostIndexOp : uint32_t {
   NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
   NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
   NEONLoadStoreSingleStructPostIndexMask  = 0xBFE0E000,
@@ -2497,7 +2502,7 @@ enum NEONLoadStoreSingleStructPostIndexOp {
 };
 
 // NEON modified immediate.
-enum NEONModifiedImmediateOp {
+enum NEONModifiedImmediateOp : uint32_t {
   NEONModifiedImmediateFixed = 0x0F000400,
   NEONModifiedImmediateFMask = 0x9FF80400,
   NEONModifiedImmediateOpBit = 0x20000000,
@@ -2509,7 +2514,7 @@ enum NEONModifiedImmediateOp {
 };
 
 // NEON shift immediate.
-enum NEONShiftImmediateOp {
+enum NEONShiftImmediateOp : uint32_t {
   NEONShiftImmediateFixed = 0x0F000400,
   NEONShiftImmediateFMask = 0x9F800400,
   NEONShiftImmediateMask  = 0xBF80FC00,
@@ -2545,7 +2550,7 @@ enum NEONShiftImmediateOp {
 };
 
 // NEON table.
-enum NEONTableOp {
+enum NEONTableOp : uint32_t {
   NEONTableFixed = 0x0E000000,
   NEONTableFMask = 0xBF208C00,
   NEONTableExt   = 0x00001000,
@@ -2561,7 +2566,7 @@ enum NEONTableOp {
 };
 
 // NEON perm.
-enum NEONPermOp {
+enum NEONPermOp : uint32_t {
   NEONPermFixed = 0x0E000800,
   NEONPermFMask = 0xBF208C00,
   NEONPermMask  = 0x3F20FC00,
@@ -2574,7 +2579,7 @@ enum NEONPermOp {
 };
 
 // NEON scalar instructions with two register operands.
-enum NEONScalar2RegMiscOp {
+enum NEONScalar2RegMiscOp : uint32_t {
   NEONScalar2RegMiscFixed = 0x5E200800,
   NEONScalar2RegMiscFMask = 0xDF3E0C00,
   NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
@@ -2621,7 +2626,7 @@ enum NEONScalar2RegMiscOp {
 };
 
 // NEON instructions with two register operands (FP16).
-enum NEONScalar2RegMiscFP16Op {
+enum NEONScalar2RegMiscFP16Op : uint32_t {
   NEONScalar2RegMiscFP16Fixed = 0x5E780800,
   NEONScalar2RegMiscFP16FMask = 0xDF7E0C00,
   NEONScalar2RegMiscFP16Mask  = 0xFFFFFC00,
@@ -2648,7 +2653,7 @@ enum NEONScalar2RegMiscFP16Op {
 };
 
 // NEON scalar instructions with three same-type operands.
-enum NEONScalar3SameOp {
+enum NEONScalar3SameOp : uint32_t {
   NEONScalar3SameFixed = 0x5E200400,
   NEONScalar3SameFMask = 0xDF200400,
   NEONScalar3SameMask  = 0xFF20FC00,
@@ -2691,7 +2696,7 @@ enum NEONScalar3SameOp {
 };
 
 // NEON scalar FP16 instructions with three same-type operands.
-enum NEONScalar3SameFP16Op {
+enum NEONScalar3SameFP16Op : uint32_t {
   NEONScalar3SameFP16Fixed = 0x5E400400,
   NEONScalar3SameFP16FMask = 0xDF60C400,
   NEONScalar3SameFP16Mask  = 0xFFE0FC00,
@@ -2707,7 +2712,7 @@ enum NEONScalar3SameFP16Op {
 };
 
 // 'Extra' NEON scalar instructions with three same-type operands.
-enum NEONScalar3SameExtraOp {
+enum NEONScalar3SameExtraOp : uint32_t {
   NEONScalar3SameExtraFixed = 0x5E008400,
   NEONScalar3SameExtraFMask = 0xDF208400,
   NEONScalar3SameExtraMask = 0xFF20FC00,
@@ -2716,7 +2721,7 @@ enum NEONScalar3SameExtraOp {
 };
 
 // NEON scalar instructions with three different-type operands.
-enum NEONScalar3DiffOp {
+enum NEONScalar3DiffOp : uint32_t {
   NEONScalar3DiffFixed = 0x5E200000,
   NEONScalar3DiffFMask = 0xDF200C00,
   NEONScalar3DiffMask  = NEON_Q | NEONScalar | NEON3DifferentMask,
@@ -2726,7 +2731,7 @@ enum NEONScalar3DiffOp {
 };
 
 // NEON scalar instructions with indexed element operand.
-enum NEONScalarByIndexedElementOp {
+enum NEONScalarByIndexedElementOp : uint32_t {
   NEONScalarByIndexedElementFixed = 0x5F000000,
   NEONScalarByIndexedElementFMask = 0xDF000400,
   NEONScalarByIndexedElementMask  = 0xFF00F400,
@@ -2757,7 +2762,7 @@ enum NEONScalarByIndexedElementOp {
 };
 
 // NEON scalar register copy.
-enum NEONScalarCopyOp {
+enum NEONScalarCopyOp : uint32_t {
   NEONScalarCopyFixed = 0x5E000400,
   NEONScalarCopyFMask = 0xDFE08400,
   NEONScalarCopyMask  = 0xFFE0FC00,
@@ -2765,7 +2770,7 @@ enum NEONScalarCopyOp {
 };
 
 // NEON scalar pairwise instructions.
-enum NEONScalarPairwiseOp {
+enum NEONScalarPairwiseOp : uint32_t {
   NEONScalarPairwiseFixed = 0x5E300800,
   NEONScalarPairwiseFMask = 0xDF3E0C00,
   NEONScalarPairwiseMask  = 0xFFB1F800,
@@ -2783,7 +2788,7 @@ enum NEONScalarPairwiseOp {
 };
 
 // NEON scalar shift immediate.
-enum NEONScalarShiftImmediateOp {
+enum NEONScalarShiftImmediateOp : uint32_t {
   NEONScalarShiftImmediateFixed = 0x5F000400,
   NEONScalarShiftImmediateFMask = 0xDF800400,
   NEONScalarShiftImmediateMask  = 0xFF80FC00,
@@ -2813,7 +2818,7 @@ enum NEONScalarShiftImmediateOp {
   NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
 };
 
-enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp {
+enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp : uint32_t {
   SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed = 0x84A00000,
   SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000,
   SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000,
@@ -2823,7 +2828,7 @@ enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp {
   LDFF1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
 };
 
-enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp {
+enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp : uint32_t {
   SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed = 0x85200000,
   SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000,
   SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000,
@@ -2831,7 +2836,7 @@ enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp {
   LDFF1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
 };
 
-enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp {
+enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp : uint32_t {
   SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed = 0x84000000,
   SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE208000,
   SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask = 0xFFA0E000,
@@ -2847,7 +2852,7 @@ enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp {
   LDFF1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01006000
 };
 
-enum SVE32BitGatherLoad_VectorPlusImmOp {
+enum SVE32BitGatherLoad_VectorPlusImmOp : uint32_t {
   SVE32BitGatherLoad_VectorPlusImmFixed = 0x84208000,
   SVE32BitGatherLoad_VectorPlusImmFMask = 0xFE608000,
   SVE32BitGatherLoad_VectorPlusImmMask = 0xFFE0E000,
@@ -2863,7 +2868,7 @@ enum SVE32BitGatherLoad_VectorPlusImmOp {
   LDFF1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01006000
 };
 
-enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp {
+enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp : uint32_t {
   SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed = 0x84200000,
   SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08010,
   SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E010,
@@ -2873,7 +2878,7 @@ enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp {
   PRFD_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
 };
 
-enum SVE32BitGatherPrefetch_VectorPlusImmOp {
+enum SVE32BitGatherPrefetch_VectorPlusImmOp : uint32_t {
   SVE32BitGatherPrefetch_VectorPlusImmFixed = 0x8400E000,
   SVE32BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010,
   SVE32BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010,
@@ -2883,7 +2888,7 @@ enum SVE32BitGatherPrefetch_VectorPlusImmOp {
   PRFD_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01800000
 };
 
-enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp {
+enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp : uint32_t {
   SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed = 0xE4608000,
   SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFMask = 0xFE60A000,
   SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask = 0xFFE0A000,
@@ -2891,7 +2896,7 @@ enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp {
   ST1W_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x01000000
 };
 
-enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp {
+enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp : uint32_t {
   SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed = 0xE4408000,
   SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE60A000,
   SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask = 0xFFE0A000,
@@ -2900,7 +2905,7 @@ enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp {
   ST1W_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x01000000
 };
 
-enum SVE32BitScatterStore_VectorPlusImmOp {
+enum SVE32BitScatterStore_VectorPlusImmOp : uint32_t {
   SVE32BitScatterStore_VectorPlusImmFixed = 0xE460A000,
   SVE32BitScatterStore_VectorPlusImmFMask = 0xFE60E000,
   SVE32BitScatterStore_VectorPlusImmMask = 0xFFE0E000,
@@ -2909,7 +2914,7 @@ enum SVE32BitScatterStore_VectorPlusImmOp {
   ST1W_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x01000000
 };
 
-enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp {
+enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp : uint32_t {
   SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed = 0xC4200000,
   SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFMask = 0xFE208000,
   SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask = 0xFFA0E000,
@@ -2925,7 +2930,7 @@ enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp {
   LDFF1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01806000
 };
 
-enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp {
+enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp : uint32_t {
   SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000,
   SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFMask = 0xFE608000,
   SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000,
@@ -2941,7 +2946,7 @@ enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp {
   LDFF1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01806000
 };
 
-enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp {
+enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp : uint32_t {
   SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed = 0xC4408000,
   SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE608000,
   SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000,
@@ -2961,7 +2966,7 @@ enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp {
   LDFF1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01806000
 };
 
-enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
+enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp : uint32_t {
   SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xC4000000,
   SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE208000,
   SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFA0E000,
@@ -2981,7 +2986,7 @@ enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
   LDFF1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01806000
 };
 
-enum SVE64BitGatherLoad_VectorPlusImmOp {
+enum SVE64BitGatherLoad_VectorPlusImmOp : uint32_t {
   SVE64BitGatherLoad_VectorPlusImmFixed = 0xC4208000,
   SVE64BitGatherLoad_VectorPlusImmFMask = 0xFE608000,
   SVE64BitGatherLoad_VectorPlusImmMask = 0xFFE0E000,
@@ -3001,7 +3006,7 @@ enum SVE64BitGatherLoad_VectorPlusImmOp {
   LDFF1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01806000
 };
 
-enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp {
+enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp : uint32_t {
   SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000,
   SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFMask = 0xFFE08010,
   SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E010,
@@ -3011,7 +3016,7 @@ enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp {
   PRFD_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00006000
 };
 
-enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp {
+enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp : uint32_t {
   SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xC4200000,
   SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFFA08010,
   SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFA0E010,
@@ -3021,7 +3026,7 @@ enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp {
   PRFD_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00006000
 };
 
-enum SVE64BitGatherPrefetch_VectorPlusImmOp {
+enum SVE64BitGatherPrefetch_VectorPlusImmOp : uint32_t {
   SVE64BitGatherPrefetch_VectorPlusImmFixed = 0xC400E000,
   SVE64BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010,
   SVE64BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010,
@@ -3031,7 +3036,7 @@ enum SVE64BitGatherPrefetch_VectorPlusImmOp {
   PRFD_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01800000
 };
 
-enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp {
+enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp : uint32_t {
   SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed = 0xE420A000,
   SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFMask = 0xFE60E000,
   SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000,
@@ -3040,7 +3045,7 @@ enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp {
   ST1D_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01800000
 };
 
-enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp {
+enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp : uint32_t {
   SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed = 0xE400A000,
   SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE60E000,
   SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000,
@@ -3050,7 +3055,7 @@ enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp {
   ST1D_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01800000
 };
 
-enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp {
+enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp : uint32_t {
   SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xE4208000,
   SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFE60A000,
   SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFE0A000,
@@ -3059,7 +3064,7 @@ enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp {
   ST1D_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01800000
 };
 
-enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
+enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp : uint32_t {
   SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xE4008000,
   SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE60A000,
   SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFE0A000,
@@ -3069,7 +3074,7 @@ enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
   ST1D_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01800000
 };
 
-enum SVE64BitScatterStore_VectorPlusImmOp {
+enum SVE64BitScatterStore_VectorPlusImmOp : uint32_t {
   SVE64BitScatterStore_VectorPlusImmFixed = 0xE440A000,
   SVE64BitScatterStore_VectorPlusImmFMask = 0xFE60E000,
   SVE64BitScatterStore_VectorPlusImmMask = 0xFFE0E000,
@@ -3079,7 +3084,7 @@ enum SVE64BitScatterStore_VectorPlusImmOp {
   ST1D_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01800000
 };
 
-enum SVEAddressGenerationOp {
+enum SVEAddressGenerationOp : uint32_t {
   SVEAddressGenerationFixed = 0x0420A000,
   SVEAddressGenerationFMask = 0xFF20F000,
   SVEAddressGenerationMask = 0xFFE0F000,
@@ -3089,7 +3094,7 @@ enum SVEAddressGenerationOp {
   ADR_z_az_d_same_scaled = SVEAddressGenerationFixed | 0x00C00000
 };
 
-enum SVEBitwiseLogicalUnpredicatedOp {
+enum SVEBitwiseLogicalUnpredicatedOp : uint32_t {
   SVEBitwiseLogicalUnpredicatedFixed = 0x04202000,
   SVEBitwiseLogicalUnpredicatedFMask = 0xFF20E000,
   SVEBitwiseLogicalUnpredicatedMask = 0xFFE0FC00,
@@ -3099,7 +3104,7 @@ enum SVEBitwiseLogicalUnpredicatedOp {
   BIC_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00C01000
 };
 
-enum SVEBitwiseLogicalWithImm_UnpredicatedOp {
+enum SVEBitwiseLogicalWithImm_UnpredicatedOp : uint32_t {
   SVEBitwiseLogicalWithImm_UnpredicatedFixed = 0x05000000,
   SVEBitwiseLogicalWithImm_UnpredicatedFMask = 0xFF3C0000,
   SVEBitwiseLogicalWithImm_UnpredicatedMask = 0xFFFC0000,
@@ -3108,7 +3113,7 @@ enum SVEBitwiseLogicalWithImm_UnpredicatedOp {
   AND_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00800000
 };
 
-enum SVEBitwiseLogical_PredicatedOp {
+enum SVEBitwiseLogical_PredicatedOp : uint32_t {
   SVEBitwiseLogical_PredicatedFixed = 0x04180000,
   SVEBitwiseLogical_PredicatedFMask = 0xFF38E000,
   SVEBitwiseLogical_PredicatedMask = 0xFF3FE000,
@@ -3118,7 +3123,7 @@ enum SVEBitwiseLogical_PredicatedOp {
   BIC_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00030000
 };
 
-enum SVEBitwiseShiftByImm_PredicatedOp {
+enum SVEBitwiseShiftByImm_PredicatedOp : uint32_t {
   SVEBitwiseShiftByImm_PredicatedFixed = 0x04008000,
   SVEBitwiseShiftByImm_PredicatedFMask = 0xFF30E000,
   SVEBitwiseShiftByImm_PredicatedMask = 0xFF3FE000,
@@ -3128,7 +3133,7 @@ enum SVEBitwiseShiftByImm_PredicatedOp {
   ASRD_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00040000
 };
 
-enum SVEBitwiseShiftByVector_PredicatedOp {
+enum SVEBitwiseShiftByVector_PredicatedOp : uint32_t {
   SVEBitwiseShiftByVector_PredicatedFixed = 0x04108000,
   SVEBitwiseShiftByVector_PredicatedFMask = 0xFF38E000,
   SVEBitwiseShiftByVector_PredicatedMask = 0xFF3FE000,
@@ -3140,7 +3145,7 @@ enum SVEBitwiseShiftByVector_PredicatedOp {
   LSLR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00070000
 };
 
-enum SVEBitwiseShiftByWideElements_PredicatedOp {
+enum SVEBitwiseShiftByWideElements_PredicatedOp : uint32_t {
   SVEBitwiseShiftByWideElements_PredicatedFixed = 0x04188000,
   SVEBitwiseShiftByWideElements_PredicatedFMask = 0xFF38E000,
   SVEBitwiseShiftByWideElements_PredicatedMask = 0xFF3FE000,
@@ -3149,7 +3154,7 @@ enum SVEBitwiseShiftByWideElements_PredicatedOp {
   LSL_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00030000
 };
 
-enum SVEBitwiseShiftUnpredicatedOp {
+enum SVEBitwiseShiftUnpredicatedOp : uint32_t {
   SVEBitwiseShiftUnpredicatedFixed = 0x04208000,
   SVEBitwiseShiftUnpredicatedFMask = 0xFF20E000,
   SVEBitwiseShiftUnpredicatedMask = 0xFF20FC00,
@@ -3161,49 +3166,49 @@ enum SVEBitwiseShiftUnpredicatedOp {
   LSL_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001C00
 };
 
-enum SVEBroadcastBitmaskImmOp {
+enum SVEBroadcastBitmaskImmOp : uint32_t {
   SVEBroadcastBitmaskImmFixed = 0x05C00000,
   SVEBroadcastBitmaskImmFMask = 0xFFFC0000,
   SVEBroadcastBitmaskImmMask = 0xFFFC0000,
   DUPM_z_i = SVEBroadcastBitmaskImmFixed
 };
 
-enum SVEBroadcastFPImm_UnpredicatedOp {
+enum SVEBroadcastFPImm_UnpredicatedOp : uint32_t {
   SVEBroadcastFPImm_UnpredicatedFixed = 0x2539C000,
   SVEBroadcastFPImm_UnpredicatedFMask = 0xFF39C000,
   SVEBroadcastFPImm_UnpredicatedMask = 0xFF3FE000,
   FDUP_z_i = SVEBroadcastFPImm_UnpredicatedFixed
 };
 
-enum SVEBroadcastGeneralRegisterOp {
+enum SVEBroadcastGeneralRegisterOp : uint32_t {
   SVEBroadcastGeneralRegisterFixed = 0x05203800,
   SVEBroadcastGeneralRegisterFMask = 0xFF3FFC00,
   SVEBroadcastGeneralRegisterMask = 0xFF3FFC00,
   DUP_z_r = SVEBroadcastGeneralRegisterFixed
 };
 
-enum SVEBroadcastIndexElementOp {
+enum SVEBroadcastIndexElementOp : uint32_t {
   SVEBroadcastIndexElementFixed = 0x05202000,
   SVEBroadcastIndexElementFMask = 0xFF20FC00,
   SVEBroadcastIndexElementMask = 0xFF20FC00,
   DUP_z_zi = SVEBroadcastIndexElementFixed
 };
 
-enum SVEBroadcastIntImm_UnpredicatedOp {
+enum SVEBroadcastIntImm_UnpredicatedOp : uint32_t {
   SVEBroadcastIntImm_UnpredicatedFixed = 0x2538C000,
   SVEBroadcastIntImm_UnpredicatedFMask = 0xFF39C000,
   SVEBroadcastIntImm_UnpredicatedMask = 0xFF3FC000,
   DUP_z_i = SVEBroadcastIntImm_UnpredicatedFixed
 };
 
-enum SVECompressActiveElementsOp {
+enum SVECompressActiveElementsOp : uint32_t {
   SVECompressActiveElementsFixed = 0x05A18000,
   SVECompressActiveElementsFMask = 0xFFBFE000,
   SVECompressActiveElementsMask = 0xFFBFE000,
   COMPACT_z_p_z = SVECompressActiveElementsFixed
 };
 
-enum SVEConditionallyBroadcastElementToVectorOp {
+enum SVEConditionallyBroadcastElementToVectorOp : uint32_t {
   SVEConditionallyBroadcastElementToVectorFixed = 0x05288000,
   SVEConditionallyBroadcastElementToVectorFMask = 0xFF3EE000,
   SVEConditionallyBroadcastElementToVectorMask = 0xFF3FE000,
@@ -3211,7 +3216,7 @@ enum SVEConditionallyBroadcastElementToVectorOp {
   CLASTB_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed | 0x00010000
 };
 
-enum SVEConditionallyExtractElementToGeneralRegisterOp {
+enum SVEConditionallyExtractElementToGeneralRegisterOp : uint32_t {
   SVEConditionallyExtractElementToGeneralRegisterFixed = 0x0530A000,
   SVEConditionallyExtractElementToGeneralRegisterFMask = 0xFF3EE000,
   SVEConditionallyExtractElementToGeneralRegisterMask = 0xFF3FE000,
@@ -3219,7 +3224,7 @@ enum SVEConditionallyExtractElementToGeneralRegisterOp {
   CLASTB_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed | 0x00010000
 };
 
-enum SVEConditionallyExtractElementToSIMDFPScalarOp {
+enum SVEConditionallyExtractElementToSIMDFPScalarOp : uint32_t {
   SVEConditionallyExtractElementToSIMDFPScalarFixed = 0x052A8000,
   SVEConditionallyExtractElementToSIMDFPScalarFMask = 0xFF3EE000,
   SVEConditionallyExtractElementToSIMDFPScalarMask = 0xFF3FE000,
@@ -3227,7 +3232,7 @@ enum SVEConditionallyExtractElementToSIMDFPScalarOp {
   CLASTB_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed | 0x00010000
 };
 
-enum SVEConditionallyTerminateScalarsOp {
+enum SVEConditionallyTerminateScalarsOp : uint32_t {
   SVEConditionallyTerminateScalarsFixed = 0x25202000,
   SVEConditionallyTerminateScalarsFMask = 0xFF20FC0F,
   SVEConditionallyTerminateScalarsMask = 0xFFA0FC1F,
@@ -3235,14 +3240,14 @@ enum SVEConditionallyTerminateScalarsOp {
   CTERMNE_rr = SVEConditionallyTerminateScalarsFixed | 0x00800010
 };
 
-enum SVEConstructivePrefix_UnpredicatedOp {
+enum SVEConstructivePrefix_UnpredicatedOp : uint32_t {
   SVEConstructivePrefix_UnpredicatedFixed = 0x0420BC00,
   SVEConstructivePrefix_UnpredicatedFMask = 0xFF20FC00,
   SVEConstructivePrefix_UnpredicatedMask = 0xFFFFFC00,
   MOVPRFX_z_z = SVEConstructivePrefix_UnpredicatedFixed
 };
 
-enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp {
+enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp : uint32_t {
   SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed = 0xA4006000,
   SVEContiguousFirstFaultLoad_ScalarPlusScalarFMask = 0xFE00E000,
   SVEContiguousFirstFaultLoad_ScalarPlusScalarMask = 0xFFE0E000,
@@ -3264,7 +3269,7 @@ enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp {
   LDFF1D_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01E00000
 };
 
-enum SVEContiguousLoad_ScalarPlusImmOp {
+enum SVEContiguousLoad_ScalarPlusImmOp : uint32_t {
   SVEContiguousLoad_ScalarPlusImmFixed = 0xA400A000,
   SVEContiguousLoad_ScalarPlusImmFMask = 0xFE10E000,
   SVEContiguousLoad_ScalarPlusImmMask = 0xFFF0E000,
@@ -3286,7 +3291,7 @@ enum SVEContiguousLoad_ScalarPlusImmOp {
   LD1D_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01E00000
 };
 
-enum SVEContiguousLoad_ScalarPlusScalarOp {
+enum SVEContiguousLoad_ScalarPlusScalarOp : uint32_t {
   SVEContiguousLoad_ScalarPlusScalarFixed = 0xA4004000,
   SVEContiguousLoad_ScalarPlusScalarFMask = 0xFE00E000,
   SVEContiguousLoad_ScalarPlusScalarMask = 0xFFE0E000,
@@ -3308,7 +3313,7 @@ enum SVEContiguousLoad_ScalarPlusScalarOp {
   LD1D_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01E00000
 };
 
-enum SVEContiguousNonFaultLoad_ScalarPlusImmOp {
+enum SVEContiguousNonFaultLoad_ScalarPlusImmOp : uint32_t {
   SVEContiguousNonFaultLoad_ScalarPlusImmFixed = 0xA410A000,
   SVEContiguousNonFaultLoad_ScalarPlusImmFMask = 0xFE10E000,
   SVEContiguousNonFaultLoad_ScalarPlusImmMask = 0xFFF0E000,
@@ -3330,7 +3335,7 @@ enum SVEContiguousNonFaultLoad_ScalarPlusImmOp {
   LDNF1D_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01E00000
 };
 
-enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp {
+enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp : uint32_t {
   SVEContiguousNonTemporalLoad_ScalarPlusImmFixed = 0xA400E000,
   SVEContiguousNonTemporalLoad_ScalarPlusImmFMask = 0xFE70E000,
   SVEContiguousNonTemporalLoad_ScalarPlusImmMask = 0xFFF0E000,
@@ -3340,7 +3345,7 @@ enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp {
   LDNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01800000
 };
 
-enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp {
+enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp : uint32_t {
   SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed = 0xA400C000,
   SVEContiguousNonTemporalLoad_ScalarPlusScalarFMask = 0xFE60E000,
   SVEContiguousNonTemporalLoad_ScalarPlusScalarMask = 0xFFE0E000,
@@ -3350,7 +3355,7 @@ enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp {
   LDNT1D_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01800000
 };
 
-enum SVEContiguousNonTemporalStore_ScalarPlusImmOp {
+enum SVEContiguousNonTemporalStore_ScalarPlusImmOp : uint32_t {
   SVEContiguousNonTemporalStore_ScalarPlusImmFixed = 0xE410E000,
   SVEContiguousNonTemporalStore_ScalarPlusImmFMask = 0xFE70E000,
   SVEContiguousNonTemporalStore_ScalarPlusImmMask = 0xFFF0E000,
@@ -3360,7 +3365,7 @@ enum SVEContiguousNonTemporalStore_ScalarPlusImmOp {
   STNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01800000
 };
 
-enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp {
+enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp : uint32_t {
   SVEContiguousNonTemporalStore_ScalarPlusScalarFixed = 0xE4006000,
   SVEContiguousNonTemporalStore_ScalarPlusScalarFMask = 0xFE60E000,
   SVEContiguousNonTemporalStore_ScalarPlusScalarMask = 0xFFE0E000,
@@ -3370,7 +3375,7 @@ enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp {
   STNT1D_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01800000
 };
 
-enum SVEContiguousPrefetch_ScalarPlusImmOp {
+enum SVEContiguousPrefetch_ScalarPlusImmOp : uint32_t {
   SVEContiguousPrefetch_ScalarPlusImmFixed = 0x85C00000,
   SVEContiguousPrefetch_ScalarPlusImmFMask = 0xFFC08010,
   SVEContiguousPrefetch_ScalarPlusImmMask = 0xFFC0E010,
@@ -3380,7 +3385,7 @@ enum SVEContiguousPrefetch_ScalarPlusImmOp {
   PRFD_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00006000
 };
 
-enum SVEContiguousPrefetch_ScalarPlusScalarOp {
+enum SVEContiguousPrefetch_ScalarPlusScalarOp : uint32_t {
   SVEContiguousPrefetch_ScalarPlusScalarFixed = 0x8400C000,
   SVEContiguousPrefetch_ScalarPlusScalarFMask = 0xFE60E010,
   SVEContiguousPrefetch_ScalarPlusScalarMask = 0xFFE0E010,
@@ -3390,7 +3395,7 @@ enum SVEContiguousPrefetch_ScalarPlusScalarOp {
   PRFD_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01800000
 };
 
-enum SVEContiguousStore_ScalarPlusImmOp {
+enum SVEContiguousStore_ScalarPlusImmOp : uint32_t {
   SVEContiguousStore_ScalarPlusImmFixed = 0xE400E000,
   SVEContiguousStore_ScalarPlusImmFMask = 0xFE10E000,
   SVEContiguousStore_ScalarPlusImmMask = 0xFF90E000,
@@ -3400,7 +3405,7 @@ enum SVEContiguousStore_ScalarPlusImmOp {
   ST1D_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01800000
 };
 
-enum SVEContiguousStore_ScalarPlusScalarOp {
+enum SVEContiguousStore_ScalarPlusScalarOp : uint32_t {
   SVEContiguousStore_ScalarPlusScalarFixed = 0xE4004000,
   SVEContiguousStore_ScalarPlusScalarFMask = 0xFE00E000,
   SVEContiguousStore_ScalarPlusScalarMask = 0xFF80E000,
@@ -3410,35 +3415,35 @@ enum SVEContiguousStore_ScalarPlusScalarOp {
   ST1D_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01800000
 };
 
-enum SVECopyFPImm_PredicatedOp {
+enum SVECopyFPImm_PredicatedOp : uint32_t {
   SVECopyFPImm_PredicatedFixed = 0x0510C000,
   SVECopyFPImm_PredicatedFMask = 0xFF30E000,
   SVECopyFPImm_PredicatedMask = 0xFF30E000,
   FCPY_z_p_i = SVECopyFPImm_PredicatedFixed
 };
 
-enum SVECopyGeneralRegisterToVector_PredicatedOp {
+enum SVECopyGeneralRegisterToVector_PredicatedOp : uint32_t {
   SVECopyGeneralRegisterToVector_PredicatedFixed = 0x0528A000,
   SVECopyGeneralRegisterToVector_PredicatedFMask = 0xFF3FE000,
   SVECopyGeneralRegisterToVector_PredicatedMask = 0xFF3FE000,
   CPY_z_p_r = SVECopyGeneralRegisterToVector_PredicatedFixed
 };
 
-enum SVECopyIntImm_PredicatedOp {
+enum SVECopyIntImm_PredicatedOp : uint32_t {
   SVECopyIntImm_PredicatedFixed = 0x05100000,
   SVECopyIntImm_PredicatedFMask = 0xFF308000,
   SVECopyIntImm_PredicatedMask = 0xFF308000,
   CPY_z_p_i = SVECopyIntImm_PredicatedFixed
 };
 
-enum SVECopySIMDFPScalarRegisterToVector_PredicatedOp {
+enum SVECopySIMDFPScalarRegisterToVector_PredicatedOp : uint32_t {
   SVECopySIMDFPScalarRegisterToVector_PredicatedFixed = 0x05208000,
   SVECopySIMDFPScalarRegisterToVector_PredicatedFMask = 0xFF3FE000,
   SVECopySIMDFPScalarRegisterToVector_PredicatedMask = 0xFF3FE000,
   CPY_z_p_v = SVECopySIMDFPScalarRegisterToVector_PredicatedFixed
 };
 
-enum SVEElementCountOp {
+enum SVEElementCountOp : uint32_t {
   SVEElementCountFixed = 0x0420E000,
   SVEElementCountFMask = 0xFF30F800,
   SVEElementCountMask = 0xFFF0FC00,
@@ -3448,7 +3453,7 @@ enum SVEElementCountOp {
   CNTD_r_s = SVEElementCountFixed | 0x00C00000
 };
 
-enum SVEExtractElementToGeneralRegisterOp {
+enum SVEExtractElementToGeneralRegisterOp : uint32_t {
   SVEExtractElementToGeneralRegisterFixed = 0x0520A000,
   SVEExtractElementToGeneralRegisterFMask = 0xFF3EE000,
   SVEExtractElementToGeneralRegisterMask = 0xFF3FE000,
@@ -3456,7 +3461,7 @@ enum SVEExtractElementToGeneralRegisterOp {
   LASTB_r_p_z = SVEExtractElementToGeneralRegisterFixed | 0x00010000
 };
 
-enum SVEExtractElementToSIMDFPScalarRegisterOp {
+enum SVEExtractElementToSIMDFPScalarRegisterOp : uint32_t {
   SVEExtractElementToSIMDFPScalarRegisterFixed = 0x05228000,
   SVEExtractElementToSIMDFPScalarRegisterFMask = 0xFF3EE000,
   SVEExtractElementToSIMDFPScalarRegisterMask = 0xFF3FE000,
@@ -3464,28 +3469,28 @@ enum SVEExtractElementToSIMDFPScalarRegisterOp {
   LASTB_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed | 0x00010000
 };
 
-enum SVEFFRInitialiseOp {
+enum SVEFFRInitialiseOp : uint32_t {
   SVEFFRInitialiseFixed = 0x252C9000,
   SVEFFRInitialiseFMask = 0xFF3FFFFF,
   SVEFFRInitialiseMask = 0xFFFFFFFF,
   SETFFR_f = SVEFFRInitialiseFixed
 };
 
-enum SVEFFRWriteFromPredicateOp {
+enum SVEFFRWriteFromPredicateOp : uint32_t {
   SVEFFRWriteFromPredicateFixed = 0x25289000,
   SVEFFRWriteFromPredicateFMask = 0xFF3FFE1F,
   SVEFFRWriteFromPredicateMask = 0xFFFFFE1F,
   WRFFR_f_p = SVEFFRWriteFromPredicateFixed
 };
 
-enum SVEFPAccumulatingReductionOp {
+enum SVEFPAccumulatingReductionOp : uint32_t {
   SVEFPAccumulatingReductionFixed = 0x65182000,
   SVEFPAccumulatingReductionFMask = 0xFF38E000,
   SVEFPAccumulatingReductionMask = 0xFF3FE000,
   FADDA_v_p_z = SVEFPAccumulatingReductionFixed
 };
 
-enum SVEFPArithmeticUnpredicatedOp {
+enum SVEFPArithmeticUnpredicatedOp : uint32_t {
   SVEFPArithmeticUnpredicatedFixed = 0x65000000,
   SVEFPArithmeticUnpredicatedFMask = 0xFF20E000,
   SVEFPArithmeticUnpredicatedMask = 0xFF20FC00,
@@ -3497,7 +3502,7 @@ enum SVEFPArithmeticUnpredicatedOp {
   FRSQRTS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001C00
 };
 
-enum SVEFPArithmeticWithImm_PredicatedOp {
+enum SVEFPArithmeticWithImm_PredicatedOp : uint32_t {
   SVEFPArithmeticWithImm_PredicatedFixed = 0x65188000,
   SVEFPArithmeticWithImm_PredicatedFMask = 0xFF38E3C0,
   SVEFPArithmeticWithImm_PredicatedMask = 0xFF3FE3C0,
@@ -3511,7 +3516,7 @@ enum SVEFPArithmeticWithImm_PredicatedOp {
   FMIN_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00070000
 };
 
-enum SVEFPArithmetic_PredicatedOp {
+enum SVEFPArithmetic_PredicatedOp : uint32_t {
   SVEFPArithmetic_PredicatedFixed = 0x65008000,
   SVEFPArithmetic_PredicatedFMask = 0xFF30E000,
   SVEFPArithmetic_PredicatedMask = 0xFF3FE000,
@@ -3530,7 +3535,7 @@ enum SVEFPArithmetic_PredicatedOp {
   FDIV_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000D0000
 };
 
-enum SVEFPCompareVectorsOp {
+enum SVEFPCompareVectorsOp : uint32_t {
   SVEFPCompareVectorsFixed = 0x65004000,
   SVEFPCompareVectorsFMask = 0xFF204000,
   SVEFPCompareVectorsMask = 0xFF20E010,
@@ -3543,7 +3548,7 @@ enum SVEFPCompareVectorsOp {
   FACGT_p_p_zz = SVEFPCompareVectorsFixed | 0x0000A010
 };
 
-enum SVEFPCompareWithZeroOp {
+enum SVEFPCompareWithZeroOp : uint32_t {
   SVEFPCompareWithZeroFixed = 0x65102000,
   SVEFPCompareWithZeroFMask = 0xFF38E000,
   SVEFPCompareWithZeroMask = 0xFF3FE010,
@@ -3555,21 +3560,21 @@ enum SVEFPCompareWithZeroOp {
   FCMNE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00030000
 };
 
-enum SVEFPComplexAdditionOp {
+enum SVEFPComplexAdditionOp : uint32_t {
   SVEFPComplexAdditionFixed = 0x64008000,
   SVEFPComplexAdditionFMask = 0xFF3EE000,
   SVEFPComplexAdditionMask = 0xFF3EE000,
   FCADD_z_p_zz = SVEFPComplexAdditionFixed
 };
 
-enum SVEFPComplexMulAddOp {
+enum SVEFPComplexMulAddOp : uint32_t {
   SVEFPComplexMulAddFixed = 0x64000000,
   SVEFPComplexMulAddFMask = 0xFF208000,
   SVEFPComplexMulAddMask = 0xFF208000,
   FCMLA_z_p_zzz = SVEFPComplexMulAddFixed
 };
 
-enum SVEFPComplexMulAddIndexOp {
+enum SVEFPComplexMulAddIndexOp : uint32_t {
   SVEFPComplexMulAddIndexFixed = 0x64201000,
   SVEFPComplexMulAddIndexFMask = 0xFF20F000,
   SVEFPComplexMulAddIndexMask = 0xFFE0F000,
@@ -3577,7 +3582,7 @@ enum SVEFPComplexMulAddIndexOp {
   FCMLA_z_zzzi_s = SVEFPComplexMulAddIndexFixed | 0x00C00000
 };
 
-enum SVEFPConvertPrecisionOp {
+enum SVEFPConvertPrecisionOp : uint32_t {
   SVEFPConvertPrecisionFixed = 0x6508A000,
   SVEFPConvertPrecisionFMask = 0xFF3CE000,
   SVEFPConvertPrecisionMask = 0xFFFFE000,
@@ -3589,7 +3594,7 @@ enum SVEFPConvertPrecisionOp {
   FCVT_z_p_z_s2d = SVEFPConvertPrecisionFixed | 0x00C30000
 };
 
-enum SVEFPConvertToIntOp {
+enum SVEFPConvertToIntOp : uint32_t {
   SVEFPConvertToIntFixed = 0x6518A000,
   SVEFPConvertToIntFMask = 0xFF38E000,
   SVEFPConvertToIntMask = 0xFFFFE000,
@@ -3609,14 +3614,14 @@ enum SVEFPConvertToIntOp {
   FCVTZU_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C70000
 };
 
-enum SVEFPExponentialAcceleratorOp {
+enum SVEFPExponentialAcceleratorOp : uint32_t {
   SVEFPExponentialAcceleratorFixed = 0x0420B800,
   SVEFPExponentialAcceleratorFMask = 0xFF20FC00,
   SVEFPExponentialAcceleratorMask = 0xFF3FFC00,
   FEXPA_z_z = SVEFPExponentialAcceleratorFixed
 };
 
-enum SVEFPFastReductionOp {
+enum SVEFPFastReductionOp : uint32_t {
   SVEFPFastReductionFixed = 0x65002000,
   SVEFPFastReductionFMask = 0xFF38E000,
   SVEFPFastReductionMask = 0xFF3FE000,
@@ -3627,7 +3632,7 @@ enum SVEFPFastReductionOp {
   FMINV_v_p_z = SVEFPFastReductionFixed | 0x00070000
 };
 
-enum SVEFPMulAddOp {
+enum SVEFPMulAddOp : uint32_t {
   SVEFPMulAddFixed = 0x65200000,
   SVEFPMulAddFMask = 0xFF200000,
   SVEFPMulAddMask = 0xFF20E000,
@@ -3641,7 +3646,7 @@ enum SVEFPMulAddOp {
   FNMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000E000
 };
 
-enum SVEFPMulAddIndexOp {
+enum SVEFPMulAddIndexOp : uint32_t {
   SVEFPMulAddIndexFixed = 0x64200000,
   SVEFPMulAddIndexFMask = 0xFF20F800,
   SVEFPMulAddIndexMask = 0xFFE0FC00,
@@ -3655,7 +3660,7 @@ enum SVEFPMulAddIndexOp {
   FMLS_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00400
 };
 
-enum SVEFPMulIndexOp {
+enum SVEFPMulIndexOp : uint32_t {
   SVEFPMulIndexFixed = 0x64202000,
   SVEFPMulIndexFMask = 0xFF20FC00,
   SVEFPMulIndexMask = 0xFFE0FC00,
@@ -3665,7 +3670,7 @@ enum SVEFPMulIndexOp {
   FMUL_z_zzi_d = SVEFPMulIndexFixed | 0x00C00000
 };
 
-enum SVEFPRoundToIntegralValueOp {
+enum SVEFPRoundToIntegralValueOp : uint32_t {
   SVEFPRoundToIntegralValueFixed = 0x6500A000,
   SVEFPRoundToIntegralValueFMask = 0xFF38E000,
   SVEFPRoundToIntegralValueMask = 0xFF3FE000,
@@ -3678,21 +3683,21 @@ enum SVEFPRoundToIntegralValueOp {
   FRINTI_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00070000
 };
 
-enum SVEFPTrigMulAddCoefficientOp {
+enum SVEFPTrigMulAddCoefficientOp : uint32_t {
   SVEFPTrigMulAddCoefficientFixed = 0x65108000,
   SVEFPTrigMulAddCoefficientFMask = 0xFF38FC00,
   SVEFPTrigMulAddCoefficientMask = 0xFF38FC00,
   FTMAD_z_zzi = SVEFPTrigMulAddCoefficientFixed
 };
 
-enum SVEFPTrigSelectCoefficientOp {
+enum SVEFPTrigSelectCoefficientOp : uint32_t {
   SVEFPTrigSelectCoefficientFixed = 0x0420B000,
   SVEFPTrigSelectCoefficientFMask = 0xFF20F800,
   SVEFPTrigSelectCoefficientMask = 0xFF20FC00,
   FTSSEL_z_zz = SVEFPTrigSelectCoefficientFixed
 };
 
-enum SVEFPUnaryOpOp {
+enum SVEFPUnaryOpOp : uint32_t {
   SVEFPUnaryOpFixed = 0x650CA000,
   SVEFPUnaryOpFMask = 0xFF3CE000,
   SVEFPUnaryOpMask = 0xFF3FE000,
@@ -3700,7 +3705,7 @@ enum SVEFPUnaryOpOp {
   FSQRT_z_p_z = SVEFPUnaryOpFixed | 0x00010000
 };
 
-enum SVEFPUnaryOpUnpredicatedOp {
+enum SVEFPUnaryOpUnpredicatedOp : uint32_t {
   SVEFPUnaryOpUnpredicatedFixed = 0x65083000,
   SVEFPUnaryOpUnpredicatedFMask = 0xFF38F000,
   SVEFPUnaryOpUnpredicatedMask = 0xFF3FFC00,
@@ -3708,7 +3713,7 @@ enum SVEFPUnaryOpUnpredicatedOp {
   FRSQRTE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00070000
 };
 
-enum SVEIncDecByPredicateCountOp {
+enum SVEIncDecByPredicateCountOp : uint32_t {
   SVEIncDecByPredicateCountFixed = 0x25288000,
   SVEIncDecByPredicateCountFMask = 0xFF38F000,
   SVEIncDecByPredicateCountMask = 0xFF3FFE00,
@@ -3730,7 +3735,7 @@ enum SVEIncDecByPredicateCountOp {
   DECP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00050800
 };
 
-enum SVEIncDecRegisterByElementCountOp {
+enum SVEIncDecRegisterByElementCountOp : uint32_t {
   SVEIncDecRegisterByElementCountFixed = 0x0430E000,
   SVEIncDecRegisterByElementCountFMask = 0xFF30F800,
   SVEIncDecRegisterByElementCountMask = 0xFFF0FC00,
@@ -3744,7 +3749,7 @@ enum SVEIncDecRegisterByElementCountOp {
   DECD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00400
 };
 
-enum SVEIncDecVectorByElementCountOp {
+enum SVEIncDecVectorByElementCountOp : uint32_t {
   SVEIncDecVectorByElementCountFixed = 0x0430C000,
   SVEIncDecVectorByElementCountFMask = 0xFF30F800,
   SVEIncDecVectorByElementCountMask = 0xFFF0FC00,
@@ -3756,7 +3761,7 @@ enum SVEIncDecVectorByElementCountOp {
   DECD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00400
 };
 
-enum SVEIndexGenerationOp {
+enum SVEIndexGenerationOp : uint32_t {
   SVEIndexGenerationFixed = 0x04204000,
   SVEIndexGenerationFMask = 0xFF20F000,
   SVEIndexGenerationMask = 0xFF20FC00,
@@ -3766,21 +3771,21 @@ enum SVEIndexGenerationOp {
   INDEX_z_rr = SVEIndexGenerationFixed | 0x00000C00
 };
 
-enum SVEInsertGeneralRegisterOp {
+enum SVEInsertGeneralRegisterOp : uint32_t {
   SVEInsertGeneralRegisterFixed = 0x05243800,
   SVEInsertGeneralRegisterFMask = 0xFF3FFC00,
   SVEInsertGeneralRegisterMask = 0xFF3FFC00,
   INSR_z_r = SVEInsertGeneralRegisterFixed
 };
 
-enum SVEInsertSIMDFPScalarRegisterOp {
+enum SVEInsertSIMDFPScalarRegisterOp : uint32_t {
   SVEInsertSIMDFPScalarRegisterFixed = 0x05343800,
   SVEInsertSIMDFPScalarRegisterFMask = 0xFF3FFC00,
   SVEInsertSIMDFPScalarRegisterMask = 0xFF3FFC00,
   INSR_z_v = SVEInsertSIMDFPScalarRegisterFixed
 };
 
-enum SVEIntAddSubtractImm_UnpredicatedOp {
+enum SVEIntAddSubtractImm_UnpredicatedOp : uint32_t {
   SVEIntAddSubtractImm_UnpredicatedFixed = 0x2520C000,
   SVEIntAddSubtractImm_UnpredicatedFMask = 0xFF38C000,
   SVEIntAddSubtractImm_UnpredicatedMask = 0xFF3FC000,
@@ -3793,7 +3798,7 @@ enum SVEIntAddSubtractImm_UnpredicatedOp {
   UQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00070000
 };
 
-enum SVEIntAddSubtractVectors_PredicatedOp {
+enum SVEIntAddSubtractVectors_PredicatedOp : uint32_t {
   SVEIntAddSubtractVectors_PredicatedFixed = 0x04000000,
   SVEIntAddSubtractVectors_PredicatedFMask = 0xFF38E000,
   SVEIntAddSubtractVectors_PredicatedMask = 0xFF3FE000,
@@ -3802,7 +3807,7 @@ enum SVEIntAddSubtractVectors_PredicatedOp {
   SUBR_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00030000
 };
 
-enum SVEIntArithmeticUnpredicatedOp {
+enum SVEIntArithmeticUnpredicatedOp : uint32_t {
   SVEIntArithmeticUnpredicatedFixed = 0x04200000,
   SVEIntArithmeticUnpredicatedFMask = 0xFF20E000,
   SVEIntArithmeticUnpredicatedMask = 0xFF20FC00,
@@ -3814,7 +3819,7 @@ enum SVEIntArithmeticUnpredicatedOp {
   UQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001C00
 };
 
-enum SVEIntCompareScalarCountAndLimitOp {
+enum SVEIntCompareScalarCountAndLimitOp : uint32_t {
   SVEIntCompareScalarCountAndLimitFixed = 0x25200000,
   SVEIntCompareScalarCountAndLimitFMask = 0xFF20E000,
   SVEIntCompareScalarCountAndLimitMask = 0xFF20EC10,
@@ -3824,7 +3829,7 @@ enum SVEIntCompareScalarCountAndLimitOp {
   WHILELS_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C10
 };
 
-enum SVEIntCompareSignedImmOp {
+enum SVEIntCompareSignedImmOp : uint32_t {
   SVEIntCompareSignedImmFixed = 0x25000000,
   SVEIntCompareSignedImmFMask = 0xFF204000,
   SVEIntCompareSignedImmMask = 0xFF20E010,
@@ -3836,7 +3841,7 @@ enum SVEIntCompareSignedImmOp {
   CMPNE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008010
 };
 
-enum SVEIntCompareUnsignedImmOp {
+enum SVEIntCompareUnsignedImmOp : uint32_t {
   SVEIntCompareUnsignedImmFixed = 0x24200000,
   SVEIntCompareUnsignedImmFMask = 0xFF200000,
   SVEIntCompareUnsignedImmMask = 0xFF202010,
@@ -3846,7 +3851,7 @@ enum SVEIntCompareUnsignedImmOp {
   CMPLS_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002010
 };
 
-enum SVEIntCompareVectorsOp {
+enum SVEIntCompareVectorsOp : uint32_t {
   SVEIntCompareVectorsFixed = 0x24000000,
   SVEIntCompareVectorsFMask = 0xFF200000,
   SVEIntCompareVectorsMask = 0xFF20E010,
@@ -3868,7 +3873,7 @@ enum SVEIntCompareVectorsOp {
   CMPLS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E010
 };
 
-enum SVEIntConvertToFPOp {
+enum SVEIntConvertToFPOp : uint32_t {
   SVEIntConvertToFPFixed = 0x6510A000,
   SVEIntConvertToFPFMask = 0xFF38E000,
   SVEIntConvertToFPMask = 0xFFFFE000,
@@ -3888,7 +3893,7 @@ enum SVEIntConvertToFPOp {
   UCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C70000
 };
 
-enum SVEIntDivideVectors_PredicatedOp {
+enum SVEIntDivideVectors_PredicatedOp : uint32_t {
   SVEIntDivideVectors_PredicatedFixed = 0x04140000,
   SVEIntDivideVectors_PredicatedFMask = 0xFF3CE000,
   SVEIntDivideVectors_PredicatedMask = 0xFF3FE000,
@@ -3898,7 +3903,7 @@ enum SVEIntDivideVectors_PredicatedOp {
   UDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00030000
 };
 
-enum SVEIntMinMaxDifference_PredicatedOp {
+enum SVEIntMinMaxDifference_PredicatedOp : uint32_t {
   SVEIntMinMaxDifference_PredicatedFixed = 0x04080000,
   SVEIntMinMaxDifference_PredicatedFMask = 0xFF38E000,
   SVEIntMinMaxDifference_PredicatedMask = 0xFF3FE000,
@@ -3910,7 +3915,7 @@ enum SVEIntMinMaxDifference_PredicatedOp {
   UABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00050000
 };
 
-enum SVEIntMinMaxImm_UnpredicatedOp {
+enum SVEIntMinMaxImm_UnpredicatedOp : uint32_t {
   SVEIntMinMaxImm_UnpredicatedFixed = 0x2528C000,
   SVEIntMinMaxImm_UnpredicatedFMask = 0xFF38C000,
   SVEIntMinMaxImm_UnpredicatedMask = 0xFF3FE000,
@@ -3920,7 +3925,7 @@ enum SVEIntMinMaxImm_UnpredicatedOp {
   UMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00030000
 };
 
-enum SVEIntMulAddPredicatedOp {
+enum SVEIntMulAddPredicatedOp : uint32_t {
   SVEIntMulAddPredicatedFixed = 0x04004000,
   SVEIntMulAddPredicatedFMask = 0xFF204000,
   SVEIntMulAddPredicatedMask = 0xFF20E000,
@@ -3930,7 +3935,7 @@ enum SVEIntMulAddPredicatedOp {
   MSB_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x0000A000
 };
 
-enum SVEIntMulAddUnpredicatedOp {
+enum SVEIntMulAddUnpredicatedOp : uint32_t {
   SVEIntMulAddUnpredicatedFixed = 0x44000000,
   SVEIntMulAddUnpredicatedFMask = 0xFF208000,
   SVEIntMulAddUnpredicatedMask = 0xFF20FC00,
@@ -3938,14 +3943,14 @@ enum SVEIntMulAddUnpredicatedOp {
   UDOT_z_zzz = SVEIntMulAddUnpredicatedFixed | 0x00000400
 };
 
-enum SVEIntMulImm_UnpredicatedOp {
+enum SVEIntMulImm_UnpredicatedOp : uint32_t {
   SVEIntMulImm_UnpredicatedFixed = 0x2530C000,
   SVEIntMulImm_UnpredicatedFMask = 0xFF38C000,
   SVEIntMulImm_UnpredicatedMask = 0xFF3FE000,
   MUL_z_zi = SVEIntMulImm_UnpredicatedFixed
 };
 
-enum SVEIntMulVectors_PredicatedOp {
+enum SVEIntMulVectors_PredicatedOp : uint32_t {
   SVEIntMulVectors_PredicatedFixed = 0x04100000,
   SVEIntMulVectors_PredicatedFMask = 0xFF3CE000,
   SVEIntMulVectors_PredicatedMask = 0xFF3FE000,
@@ -3954,14 +3959,14 @@ enum SVEIntMulVectors_PredicatedOp {
   UMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00030000
 };
 
-enum SVEMovprfxOp {
+enum SVEMovprfxOp : uint32_t {
   SVEMovprfxFixed = 0x04002000,
   SVEMovprfxFMask = 0xFF20E000,
   SVEMovprfxMask = 0xFF3EE000,
   MOVPRFX_z_p_z = SVEMovprfxFixed | 0x00100000
 };
 
-enum SVEIntReductionOp {
+enum SVEIntReductionOp : uint32_t {
   SVEIntReductionFixed = 0x04002000,
   SVEIntReductionFMask = 0xFF20E000,
   SVEIntReductionMask = 0xFF3FE000,
@@ -3973,7 +3978,7 @@ enum SVEIntReductionOp {
   UMINV_r_p_z = SVEIntReductionFixed | 0x000B0000
 };
 
-enum SVEIntReductionLogicalOp {
+enum SVEIntReductionLogicalOp : uint32_t {
   SVEIntReductionLogicalFixed = 0x04182000,
   SVEIntReductionLogicalFMask = 0xFF38E000,
   SVEIntReductionLogicalMask = 0xFF3FE000,
@@ -3982,7 +3987,7 @@ enum SVEIntReductionLogicalOp {
   ANDV_r_p_z = SVEIntReductionLogicalFixed | 0x001A0000
 };
 
-enum SVEIntUnaryArithmeticPredicatedOp {
+enum SVEIntUnaryArithmeticPredicatedOp : uint32_t {
   SVEIntUnaryArithmeticPredicatedFixed = 0x0400A000,
   SVEIntUnaryArithmeticPredicatedFMask = 0xFF20E000,
   SVEIntUnaryArithmeticPredicatedMask = 0xFF3FE000,
@@ -4003,7 +4008,7 @@ enum SVEIntUnaryArithmeticPredicatedOp {
   NOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001E0000
 };
 
-enum SVELoadAndBroadcastElementOp {
+enum SVELoadAndBroadcastElementOp : uint32_t {
   SVELoadAndBroadcastElementFixed = 0x84408000,
   SVELoadAndBroadcastElementFMask = 0xFE408000,
   SVELoadAndBroadcastElementMask = 0xFFC0E000,
@@ -4025,7 +4030,7 @@ enum SVELoadAndBroadcastElementOp {
   LD1RD_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01806000
 };
 
-enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp {
+enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp : uint32_t {
   SVELoadAndBroadcastQuadword_ScalarPlusImmFixed = 0xA4002000,
   SVELoadAndBroadcastQuadword_ScalarPlusImmFMask = 0xFE10E000,
   SVELoadAndBroadcastQuadword_ScalarPlusImmMask = 0xFFF0E000,
@@ -4035,7 +4040,7 @@ enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp {
   LD1RQD_z_p_bi_u64 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01800000
 };
 
-enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp {
+enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp : uint32_t {
   SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed = 0xA4000000,
   SVELoadAndBroadcastQuadword_ScalarPlusScalarFMask = 0xFE00E000,
   SVELoadAndBroadcastQuadword_ScalarPlusScalarMask = 0xFFE0E000,
@@ -4045,7 +4050,7 @@ enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp {
   LD1RQD_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01800000
 };
 
-enum SVELoadMultipleStructures_ScalarPlusImmOp {
+enum SVELoadMultipleStructures_ScalarPlusImmOp : uint32_t {
   SVELoadMultipleStructures_ScalarPlusImmFixed = 0xA400E000,
   SVELoadMultipleStructures_ScalarPlusImmFMask = 0xFE10E000,
   SVELoadMultipleStructures_ScalarPlusImmMask = 0xFFF0E000,
@@ -4063,7 +4068,7 @@ enum SVELoadMultipleStructures_ScalarPlusImmOp {
   LD4D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01E00000
 };
 
-enum SVELoadMultipleStructures_ScalarPlusScalarOp {
+enum SVELoadMultipleStructures_ScalarPlusScalarOp : uint32_t {
   SVELoadMultipleStructures_ScalarPlusScalarFixed = 0xA400C000,
   SVELoadMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000,
   SVELoadMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000,
@@ -4081,21 +4086,21 @@ enum SVELoadMultipleStructures_ScalarPlusScalarOp {
   LD4D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01E00000
 };
 
-enum SVELoadPredicateRegisterOp {
+enum SVELoadPredicateRegisterOp : uint32_t {
   SVELoadPredicateRegisterFixed = 0x85800000,
   SVELoadPredicateRegisterFMask = 0xFFC0E010,
   SVELoadPredicateRegisterMask = 0xFFC0E010,
   LDR_p_bi = SVELoadPredicateRegisterFixed
 };
 
-enum SVELoadVectorRegisterOp {
+enum SVELoadVectorRegisterOp : uint32_t {
   SVELoadVectorRegisterFixed = 0x85804000,
   SVELoadVectorRegisterFMask = 0xFFC0E000,
   SVELoadVectorRegisterMask = 0xFFC0E000,
   LDR_z_bi = SVELoadVectorRegisterFixed
 };
 
-enum SVEMulIndexOp {
+enum SVEMulIndexOp : uint32_t {
   SVEMulIndexFixed = 0x44200000,
   SVEMulIndexFMask = 0xFF200000,
   SVEMulIndexMask = 0xFFE0FC00,
@@ -4105,7 +4110,7 @@ enum SVEMulIndexOp {
   UDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00400
 };
 
-enum SVEPartitionBreakConditionOp {
+enum SVEPartitionBreakConditionOp : uint32_t {
   SVEPartitionBreakConditionFixed = 0x25104000,
   SVEPartitionBreakConditionFMask = 0xFF3FC200,
   SVEPartitionBreakConditionMask = 0xFFFFC200,
@@ -4115,7 +4120,7 @@ enum SVEPartitionBreakConditionOp {
   BRKBS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00C00000
 };
 
-enum SVEPermutePredicateElementsOp {
+enum SVEPermutePredicateElementsOp : uint32_t {
   SVEPermutePredicateElementsFixed = 0x05204000,
   SVEPermutePredicateElementsFMask = 0xFF30E210,
   SVEPermutePredicateElementsMask = 0xFF30FE10,
@@ -4127,14 +4132,14 @@ enum SVEPermutePredicateElementsOp {
   TRN2_p_pp = SVEPermutePredicateElementsFixed | 0x00001400
 };
 
-enum SVEPermuteVectorExtractOp {
+enum SVEPermuteVectorExtractOp : uint32_t {
   SVEPermuteVectorExtractFixed = 0x05200000,
   SVEPermuteVectorExtractFMask = 0xFF20E000,
   SVEPermuteVectorExtractMask = 0xFFE0E000,
   EXT_z_zi_des = SVEPermuteVectorExtractFixed
 };
 
-enum SVEPermuteVectorInterleavingOp {
+enum SVEPermuteVectorInterleavingOp : uint32_t {
   SVEPermuteVectorInterleavingFixed = 0x05206000,
   SVEPermuteVectorInterleavingFMask = 0xFF20E000,
   SVEPermuteVectorInterleavingMask = 0xFF20FC00,
@@ -4146,21 +4151,21 @@ enum SVEPermuteVectorInterleavingOp {
   TRN2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001400
 };
 
-enum SVEPredicateCountOp {
+enum SVEPredicateCountOp : uint32_t {
   SVEPredicateCountFixed = 0x25208000,
   SVEPredicateCountFMask = 0xFF38C000,
   SVEPredicateCountMask = 0xFF3FC200,
   CNTP_r_p_p = SVEPredicateCountFixed
 };
 
-enum SVEPredicateFirstActiveOp {
+enum SVEPredicateFirstActiveOp : uint32_t {
   SVEPredicateFirstActiveFixed = 0x2518C000,
   SVEPredicateFirstActiveFMask = 0xFF3FFE10,
   SVEPredicateFirstActiveMask = 0xFFFFFE10,
   PFIRST_p_p_p = SVEPredicateFirstActiveFixed | 0x00400000
 };
 
-enum SVEPredicateInitializeOp {
+enum SVEPredicateInitializeOp : uint32_t {
   SVEPredicateInitializeFixed = 0x2518E000,
   SVEPredicateInitializeFMask = 0xFF3EFC10,
   SVEPredicateInitializeMask = 0xFF3FFC10,
@@ -4169,7 +4174,7 @@ enum SVEPredicateInitializeOp {
   PTRUES_p_s = SVEPredicateInitializeFixed | SVEPredicateInitializeSetFlagsBit
 };
 
-enum SVEPredicateLogicalOp {
+enum SVEPredicateLogicalOp : uint32_t {
   SVEPredicateLogicalFixed = 0x25004000,
   SVEPredicateLogicalFMask = 0xFF30C000,
   SVEPredicateLogicalMask = 0xFFF0C210,
@@ -4191,14 +4196,14 @@ enum SVEPredicateLogicalOp {
   SEL_p_p_pp = SVEPredicateLogicalFixed | 0x00000210
 };
 
-enum SVEPredicateNextActiveOp {
+enum SVEPredicateNextActiveOp : uint32_t {
   SVEPredicateNextActiveFixed = 0x2519C400,
   SVEPredicateNextActiveFMask = 0xFF3FFE10,
   SVEPredicateNextActiveMask = 0xFF3FFE10,
   PNEXT_p_p_p = SVEPredicateNextActiveFixed
 };
 
-enum SVEPredicateReadFromFFR_PredicatedOp {
+enum SVEPredicateReadFromFFR_PredicatedOp : uint32_t {
   SVEPredicateReadFromFFR_PredicatedFixed = 0x2518F000,
   SVEPredicateReadFromFFR_PredicatedFMask = 0xFF3FFE10,
   SVEPredicateReadFromFFR_PredicatedMask = 0xFFFFFE10,
@@ -4206,28 +4211,28 @@ enum SVEPredicateReadFromFFR_PredicatedOp {
   RDFFRS_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed | 0x00400000
 };
 
-enum SVEPredicateReadFromFFR_UnpredicatedOp {
+enum SVEPredicateReadFromFFR_UnpredicatedOp : uint32_t {
   SVEPredicateReadFromFFR_UnpredicatedFixed = 0x2519F000,
   SVEPredicateReadFromFFR_UnpredicatedFMask = 0xFF3FFFF0,
   SVEPredicateReadFromFFR_UnpredicatedMask = 0xFFFFFFF0,
   RDFFR_p_f = SVEPredicateReadFromFFR_UnpredicatedFixed
 };
 
-enum SVEPredicateTestOp {
+enum SVEPredicateTestOp : uint32_t {
   SVEPredicateTestFixed = 0x2510C000,
   SVEPredicateTestFMask = 0xFF3FC210,
   SVEPredicateTestMask = 0xFFFFC21F,
   PTEST_p_p = SVEPredicateTestFixed | 0x00400000
 };
 
-enum SVEPredicateZeroOp {
+enum SVEPredicateZeroOp : uint32_t {
   SVEPredicateZeroFixed = 0x2518E400,
   SVEPredicateZeroFMask = 0xFF3FFFF0,
   SVEPredicateZeroMask = 0xFFFFFFF0,
   PFALSE_p = SVEPredicateZeroFixed
 };
 
-enum SVEPropagateBreakOp {
+enum SVEPropagateBreakOp : uint32_t {
   SVEPropagateBreakFixed = 0x2500C000,
   SVEPropagateBreakFMask = 0xFF30C000,
   SVEPropagateBreakMask = 0xFFF0C210,
@@ -4237,7 +4242,7 @@ enum SVEPropagateBreakOp {
   BRKPBS_p_p_pp = SVEPropagateBreakFixed | 0x00400010
 };
 
-enum SVEPropagateBreakToNextPartitionOp {
+enum SVEPropagateBreakToNextPartitionOp : uint32_t {
   SVEPropagateBreakToNextPartitionFixed = 0x25184000,
   SVEPropagateBreakToNextPartitionFMask = 0xFFBFC210,
   SVEPropagateBreakToNextPartitionMask = 0xFFFFC210,
@@ -4245,21 +4250,21 @@ enum SVEPropagateBreakToNextPartitionOp {
   BRKNS_p_p_pp = SVEPropagateBreakToNextPartitionFixed | 0x00400000
 };
 
-enum SVEReversePredicateElementsOp {
+enum SVEReversePredicateElementsOp : uint32_t {
   SVEReversePredicateElementsFixed = 0x05344000,
   SVEReversePredicateElementsFMask = 0xFF3FFE10,
   SVEReversePredicateElementsMask = 0xFF3FFE10,
   REV_p_p = SVEReversePredicateElementsFixed
 };
 
-enum SVEReverseVectorElementsOp {
+enum SVEReverseVectorElementsOp : uint32_t {
   SVEReverseVectorElementsFixed = 0x05383800,
   SVEReverseVectorElementsFMask = 0xFF3FFC00,
   SVEReverseVectorElementsMask = 0xFF3FFC00,
   REV_z_z = SVEReverseVectorElementsFixed
 };
 
-enum SVEReverseWithinElementsOp {
+enum SVEReverseWithinElementsOp : uint32_t {
   SVEReverseWithinElementsFixed = 0x05248000,
   SVEReverseWithinElementsFMask = 0xFF3CE000,
   SVEReverseWithinElementsMask = 0xFF3FE000,
@@ -4269,7 +4274,7 @@ enum SVEReverseWithinElementsOp {
   RBIT_z_p_z = SVEReverseWithinElementsFixed | 0x00030000
 };
 
-enum SVESaturatingIncDecRegisterByElementCountOp {
+enum SVESaturatingIncDecRegisterByElementCountOp : uint32_t {
   SVESaturatingIncDecRegisterByElementCountFixed = 0x0420F000,
   SVESaturatingIncDecRegisterByElementCountFMask = 0xFF20F000,
   SVESaturatingIncDecRegisterByElementCountMask = 0xFFF0FC00,
@@ -4307,7 +4312,7 @@ enum SVESaturatingIncDecRegisterByElementCountOp {
   UQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00C00
 };
 
-enum SVESaturatingIncDecVectorByElementCountOp {
+enum SVESaturatingIncDecVectorByElementCountOp : uint32_t {
   SVESaturatingIncDecVectorByElementCountFixed = 0x0420C000,
   SVESaturatingIncDecVectorByElementCountFMask = 0xFF30F000,
   SVESaturatingIncDecVectorByElementCountMask = 0xFFF0FC00,
@@ -4325,7 +4330,7 @@ enum SVESaturatingIncDecVectorByElementCountOp {
   UQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00C00
 };
 
-enum SVEStackFrameAdjustmentOp {
+enum SVEStackFrameAdjustmentOp : uint32_t {
   SVEStackFrameAdjustmentFixed = 0x04205000,
   SVEStackFrameAdjustmentFMask = 0xFFA0F800,
   SVEStackFrameAdjustmentMask = 0xFFE0F800,
@@ -4333,14 +4338,14 @@ enum SVEStackFrameAdjustmentOp {
   ADDPL_r_ri = SVEStackFrameAdjustmentFixed | 0x00400000
 };
 
-enum SVEStackFrameSizeOp {
+enum SVEStackFrameSizeOp : uint32_t {
   SVEStackFrameSizeFixed = 0x04BF5000,
   SVEStackFrameSizeFMask = 0xFFFFF800,
   SVEStackFrameSizeMask = 0xFFFFF800,
   RDVL_r_i = SVEStackFrameSizeFixed
 };
 
-enum SVEStoreMultipleStructures_ScalarPlusImmOp {
+enum SVEStoreMultipleStructures_ScalarPlusImmOp : uint32_t {
   SVEStoreMultipleStructures_ScalarPlusImmFixed = 0xE410E000,
   SVEStoreMultipleStructures_ScalarPlusImmFMask = 0xFE10E000,
   SVEStoreMultipleStructures_ScalarPlusImmMask = 0xFFF0E000,
@@ -4358,7 +4363,7 @@ enum SVEStoreMultipleStructures_ScalarPlusImmOp {
   ST4D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01E00000
 };
 
-enum SVEStoreMultipleStructures_ScalarPlusScalarOp {
+enum SVEStoreMultipleStructures_ScalarPlusScalarOp : uint32_t {
   SVEStoreMultipleStructures_ScalarPlusScalarFixed = 0xE4006000,
   SVEStoreMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000,
   SVEStoreMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000,
@@ -4376,28 +4381,28 @@ enum SVEStoreMultipleStructures_ScalarPlusScalarOp {
   ST4D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01E00000
 };
 
-enum SVEStorePredicateRegisterOp {
+enum SVEStorePredicateRegisterOp : uint32_t {
   SVEStorePredicateRegisterFixed = 0xE5800000,
   SVEStorePredicateRegisterFMask = 0xFFC0E010,
   SVEStorePredicateRegisterMask = 0xFFC0E010,
   STR_p_bi = SVEStorePredicateRegisterFixed
 };
 
-enum SVEStoreVectorRegisterOp {
+enum SVEStoreVectorRegisterOp : uint32_t {
   SVEStoreVectorRegisterFixed = 0xE5804000,
   SVEStoreVectorRegisterFMask = 0xFFC0E000,
   SVEStoreVectorRegisterMask = 0xFFC0E000,
   STR_z_bi = SVEStoreVectorRegisterFixed
 };
 
-enum SVETableLookupOp {
+enum SVETableLookupOp : uint32_t {
   SVETableLookupFixed = 0x05203000,
   SVETableLookupFMask = 0xFF20FC00,
   SVETableLookupMask = 0xFF20FC00,
   TBL_z_zz_1 = SVETableLookupFixed
 };
 
-enum SVEUnpackPredicateElementsOp {
+enum SVEUnpackPredicateElementsOp : uint32_t {
   SVEUnpackPredicateElementsFixed = 0x05304000,
   SVEUnpackPredicateElementsFMask = 0xFFFEFE10,
   SVEUnpackPredicateElementsMask = 0xFFFFFE10,
@@ -4405,7 +4410,7 @@ enum SVEUnpackPredicateElementsOp {
   PUNPKHI_p_p = SVEUnpackPredicateElementsFixed | 0x00010000
 };
 
-enum SVEUnpackVectorElementsOp {
+enum SVEUnpackVectorElementsOp : uint32_t {
   SVEUnpackVectorElementsFixed = 0x05303800,
   SVEUnpackVectorElementsFMask = 0xFF3CFC00,
   SVEUnpackVectorElementsMask = 0xFF3FFC00,
@@ -4415,21 +4420,21 @@ enum SVEUnpackVectorElementsOp {
   UUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00030000
 };
 
-enum SVEVectorSelectOp {
+enum SVEVectorSelectOp : uint32_t {
   SVEVectorSelectFixed = 0x0520C000,
   SVEVectorSelectFMask = 0xFF20C000,
   SVEVectorSelectMask = 0xFF20C000,
   SEL_z_p_zz = SVEVectorSelectFixed
 };
 
-enum SVEVectorSpliceOp {
+enum SVEVectorSpliceOp : uint32_t {
   SVEVectorSpliceFixed = 0x052C8000,
   SVEVectorSpliceFMask = 0xFF3FE000,
   SVEVectorSpliceMask = 0xFF3FE000,
   SPLICE_z_p_zz_des = SVEVectorSpliceFixed
 };
 
-enum ReservedOp {
+enum ReservedOp : uint32_t {
   ReservedFixed = 0x00000000,
   ReservedFMask = 0x1E000000,
   ReservedMask = 0xFFFF0000,
@@ -4438,12 +4443,12 @@ enum ReservedOp {
 
 // Unimplemented and unallocated instructions. These are defined to make fixed
 // bit assertion easier.
-enum UnimplementedOp {
+enum UnimplementedOp : uint32_t {
   UnimplementedFixed = 0x00000000,
   UnimplementedFMask = 0x00000000
 };
 
-enum UnallocatedOp {
+enum UnallocatedOp : uint32_t {
   UnallocatedFixed = 0x00000000,
   UnallocatedFMask = 0x00000000
 };