mirror of
https://github.com/PCSX2/pcsx2.git
synced 2024-10-06 23:13:25 +00:00
microVU: T/D Bit cleanup, slightly better code, makes much more sense to how the PS2 does it. Fixed ICO's graphics.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5594 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
refraction@gmail.com
parent
31221a29bd
commit
6d456b8a69
@ -38,8 +38,8 @@ void mVUDTendProgram(mV, microFlagCycles* mFC, int isEbit) {
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mVU.regAlloc->TDwritebackAll(); //Writing back ok, invalidating early kills the rec, so don't do it :P
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if (isEbit) {
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memzero(mVUinfo);
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memzero(mVUregsTemp);
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/*memzero(mVUinfo);
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memzero(mVUregsTemp);*/
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mVUincCycles(mVU, 100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
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mVUcycles -= 100;
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qInst = mVU.q;
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@ -74,7 +74,7 @@ void mVUDTendProgram(mV, microFlagCycles* mFC, int isEbit) {
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if (isEbit || isVU1) { // Clear 'is busy' Flags
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if (!mVU.index || !THREAD_VU1) {
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xAND(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? ~0x100 : ~0x001)); // VBS0/VBS1 flag
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//xAND(ptr32[&mVU.getVifRegs().stat], ~VIF1_STAT_VEW); // Clear VU 'is busy' signal for vif
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xAND(ptr32[&mVU.getVifRegs().stat], ~VIF1_STAT_VEW); // Clear VU 'is busy' signal for vif
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}
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}
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@ -181,7 +181,31 @@ void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump) {
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void normBranch(mV, microFlagCycles& mFC) {
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// E-bit Branch
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// E-bit or T-Bit or D-Bit Branch
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if (mVUup.dBit)
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{
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u32 tempPC = iPC;
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xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x400 : 0x4));
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x200 : 0x2));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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iPC = branchAddr/4;
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mVUDTendProgram(mVU, &mFC, 1);
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eJMP.SetTarget();
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iPC = tempPC;
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}
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if (mVUup.tBit)
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{
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u32 tempPC = iPC;
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xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x800 : 0x8));
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x400 : 0x4));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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iPC = branchAddr/4;
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mVUDTendProgram(mVU, &mFC, 1);
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eJMP.SetTarget();
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iPC = tempPC;
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}
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if (mVUup.eBit) { if(mVUlow.badBranch) DevCon.Warning("End on evil Unconditional branch! - Not implemented! - If game broken report to PCSX2 Team"); iPC = branchAddr/4; mVUendProgram(mVU, &mFC, 1); return; }
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if(mVUlow.badBranch)
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@ -247,6 +271,49 @@ void condJumpProcessingEvil(mV, microFlagCycles& mFC, int JMPcc) {
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}
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void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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mVUsetupBranch(mVU, mFC);
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if (mVUup.tBit)
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{
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u32 tempPC = iPC;
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xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x800 : 0x8));
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x400 : 0x4));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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mVUDTendProgram(mVU, &mFC, 2);
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xCMP(ptr16[&mVU.branch], 0);
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xForwardJump8 tJMP((JccComparisonType)JMPcc);
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incPC(4); // Set PC to First instruction of Non-Taken Side
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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eJMP.SetTarget();
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incPC(-4); // Go Back to Branch Opcode to get branchAddr
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iPC = branchAddr/4;
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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tJMP.SetTarget();
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iPC = tempPC;
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}
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if (mVUup.dBit)
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{
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u32 tempPC = iPC;
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xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x400 : 0x4));
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x200 : 0x2));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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mVUDTendProgram(mVU, &mFC, 2);
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xCMP(ptr16[&mVU.branch], 0);
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xForwardJump8 dJMP((JccComparisonType)JMPcc);
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incPC(4); // Set PC to First instruction of Non-Taken Side
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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dJMP.SetTarget();
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incPC(-4); // Go Back to Branch Opcode to get branchAddr
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iPC = branchAddr/4;
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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eJMP.SetTarget();
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iPC = tempPC;
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}
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xCMP(ptr16[&mVU.branch], 0);
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incPC(3);
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if (mVUup.eBit) { // Conditional Branch With E-Bit Set
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@ -331,6 +398,30 @@ void normJump(mV, microFlagCycles& mFC) {
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}
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incPC(-3);
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}
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if (mVUup.dBit)
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{
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xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x400 : 0x4));
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x200 : 0x2));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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mVUDTendProgram(mVU, &mFC, 2);
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xMOV(gprT1, ptr32[&mVU.branch]);
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], gprT1);
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xJMP(mVU.exitFunct);
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eJMP.SetTarget();
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}
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if (mVUup.tBit)
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{
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xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x800 : 0x8));
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x400 : 0x4));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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mVUDTendProgram(mVU, &mFC, 2);
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xMOV(gprT1, ptr32[&mVU.branch]);
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], gprT1);
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xJMP(mVU.exitFunct);
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eJMP.SetTarget();
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}
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if (mVUup.eBit) { // E-bit Jump
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mVUendProgram(mVU, &mFC, 2);
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xMOV(gprT1, ptr32[&mVU.branch]);
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@ -480,116 +480,27 @@ void* mVUcompileSingleInstruction(microVU& mVU, u32 startPC, uptr pState, microF
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void mVUDoDBit(microVU& mVU, microFlagCycles* mFC)
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{
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bool isBranch = false;
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JccComparisonType Jcc;
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u32 savedPC = 0;
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incPC(2); //Check next slot for branch delay, if not, that's where the VU will resume anyway.
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savedPC = iPC; //Save PC as it's about to get modified if it's a branch!
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if(mVUinfo.isBdelay) isBranch = true;
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xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x400 : 0x4));
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x200 : 0x2));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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if(isBranch)
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{
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incPC(-2); // Go back to branch opcode
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DevCon.Warning("microVU%d: D-Bit on branch [%04x]", getIndex, xPC);
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mVUDTendProgram(mVU, mFC, 2);
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xCMP(ptr16[&mVU.branch], 0);
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switch (mVUlow.branch) {
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case 1: case 2: Jcc = Jcc_Unconditional; DevCon.Warning("microVU%d: D Bit on B/BAL, might be buggy", getIndex); break; // B/BAL
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case 9: case 10: DevCon.Warning("microVU%d: JR/JALR probably not supported on D Bit!", getIndex); break; // JR/JALR
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case 3: Jcc = Jcc_Equal; break; // IBEQ
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case 4: Jcc = Jcc_GreaterOrEqual; break; // IBGEZ
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case 5: Jcc = Jcc_Greater; break; // IBGTZ
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case 6: Jcc = Jcc_LessOrEqual; break; // IBLEQ
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case 7: Jcc = Jcc_Less; break; // IBLTZ
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case 8: Jcc = Jcc_NotEqual; break; // IBNEQ
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}
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if(mVUlow.branch < 9)
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{
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incPC(1);
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xForwardJump8 bJMP((JccComparisonType)Jcc);
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incPC(1); // Set PC to First instruction of Non-Taken Side
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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bJMP.SetTarget();
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incPC(-4); // Go Back to Branch Opcode to get branchAddr
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iPC = branchAddr/4;
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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}
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else
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{
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xMOV(gprT1, ptr32[&mVU.branch]);
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], gprT1);
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}
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xJMP(mVU.exitFunct);
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}
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else
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mVUDTendProgram(mVU, mFC, 1);
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incPC(1);
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mVUDTendProgram(mVU, mFC, 1);
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incPC(-1);
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eJMP.SetTarget();
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iPC = savedPC;
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}
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void mVUDoTBit(microVU& mVU, microFlagCycles* mFC)
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{
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bool isBranch = false;
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JccComparisonType Jcc;
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u32 savedPC = 0;
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incPC(2); //Check next slot for branch delay, if not, that's where the VU will resume anyway.
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savedPC = iPC; //Save PC as it's about to get modified if it's a branch!
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if(mVUinfo.isBdelay) isBranch = true;
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xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x800 : 0x8));
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x400 : 0x4));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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if(isBranch)
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{
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incPC(-2); // Go back to branch opcode
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DevCon.Warning("microVU%d: T-Bit on branch [%04x]", getIndex, xPC);
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mVUDTendProgram(mVU, mFC, 2);
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xCMP(ptr16[&mVU.branch], 0);
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switch (mVUlow.branch) {
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case 1: case 2: Jcc = Jcc_Unconditional; DevCon.Warning("microVU%d: T Bit on B/BAL, might be buggy", getIndex); break; // B/BAL
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case 9: case 10: DevCon.Warning("microVU%d: JR/JALR probably not supported on T Bit!", getIndex); break; // JR/JALR
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case 3: Jcc = Jcc_Equal; break; // IBEQ
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case 4: Jcc = Jcc_GreaterOrEqual; break; // IBGEZ
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case 5: Jcc = Jcc_Greater; break; // IBGTZ
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case 6: Jcc = Jcc_LessOrEqual; break; // IBLEQ
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case 7: Jcc = Jcc_Less; break; // IBLTZ
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case 8: Jcc = Jcc_NotEqual; break; // IBNEQ
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}
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if(mVUlow.branch < 9)
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{
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incPC(1);
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xForwardJump8 bJMP((JccComparisonType)Jcc);
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incPC(1); // Set PC to First instruction of Non-Taken Side
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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bJMP.SetTarget();
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incPC(-4); // Go Back to Branch Opcode to get branchAddr
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iPC = branchAddr/4;
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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}
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else
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{
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xMOV(gprT1, ptr32[&mVU.branch]);
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], gprT1);
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}
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xJMP(mVU.exitFunct);
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}
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else
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mVUDTendProgram(mVU, mFC, 1);
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incPC(1);
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mVUDTendProgram(mVU, mFC, 1);
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incPC(-1);
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eJMP.SetTarget();
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iPC = savedPC;
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}
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void mVUSaveFlags(microVU& mVU,microFlagCycles &mFC, microFlagCycles &mFCBackup)
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@ -600,7 +511,6 @@ void mVUSaveFlags(microVU& mVU,microFlagCycles &mFC, microFlagCycles &mFCBackup)
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void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) {
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microFlagCycles mFC;
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microFlagCycles mFCBackup;
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u8* thisPtr = x86Ptr;
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const u32 endCount = (((microRegInfo*)pState)->blockType) ? 1 : (mVU.microMemSize / 8);
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@ -617,11 +527,13 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) {
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mVUopU(mVU, 0);
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mVUcheckBadOp(mVU);
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if (curI & _Ebit_) { eBitPass1(mVU, branch); }
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if (curI & _Dbit_) { mVUup.dBit = 1; mVUsetFlagInfo(mVU); mVUSaveFlags(mVU, mFC, mFCBackup); }
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if (curI & _Mbit_) { mVUup.mBit = 1; }
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if (curI & _Tbit_) { mVUup.tBit = 1; mVUsetFlagInfo(mVU); mVUSaveFlags(mVU, mFC, mFCBackup); }
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if (curI & _Ibit_) { mVUlow.isNOP = 1; mVUup.iBit = 1; }
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else { incPC(-1); mVUopL(mVU, 0); incPC(1); }
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if (curI & _Dbit_) { mVUup.dBit = 1; }
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if (curI & _Tbit_) { mVUup.tBit = 1; }
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mVUsetCycles(mVU);
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mVUinfo.readQ = mVU.q;
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mVUinfo.writeQ = !mVU.q;
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@ -653,6 +565,11 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) {
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if (mVUinfo.isEOB) { handleBadOp(mVU, x); x = 0xffff; }
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if (mVUup.mBit) { xOR(ptr32[&mVU.regs().flags], VUFLAG_MFLAGSET); }
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mVUexecuteInstruction(mVU);
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if(!mVUinfo.isBdelay && !mVUlow.branch) //T/D Bit on branch is handled after the branch, branch delay slots are executed.
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{
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if(mVUup.tBit) { mVUDoTBit(mVU, &mFC); }
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else if(mVUup.dBit) { mVUDoDBit(mVU, &mFC); }
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}
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if (mVUinfo.doXGKICK) { mVU_XGKICK_DELAY(mVU, 1); }
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if (isEvilBlock) { mVUsetupRange(mVU, xPC, 0); normJumpCompile(mVU, mFC, 1); return thisPtr; }
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else if (!mVUinfo.isBdelay) { incPC(1); }
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@ -671,13 +588,8 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) {
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case 7: condBranch(mVU, mFC, Jcc_Less); return thisPtr; // IBLTZ
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case 8: condBranch(mVU, mFC, Jcc_NotEqual); return thisPtr; // IBNEQ
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}
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}
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incPC(-2);
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if(mVUup.tBit) { mVUDoTBit(mVU, &mFC); }
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else if(mVUup.dBit) { mVUDoDBit(mVU, &mFC); }
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else incPC(2);
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}
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if ((x == endCount) && (x!=1)) { Console.Error("microVU%d: Possible infinite compiling loop!", mVU.index); }
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