mirror of
https://github.com/PCSX2/pcsx2.git
synced 2026-10-12 02:08:45 +00:00
Jake.Stine
377830b3a9
* Fixed the IOP's recExecute so that it correctly preserves X86 registers (EDI and EBX were not preserved!) * Optimized the recExecute procedure, seems like a nice speedup in FMVs and some games that are IOP intensive. * Renamed psxMemRead to iopMemRead, added new Virt/Phys functions, and fixed several instances of DMAs using translated addresses (DMAs are always physical maps). Our IOP doesn't really emulate the tlb so it won't fix anything, but it's more correct in cas stuff is better supported in the future. * Removed unneeded FreezeMMXRegs, since the IOPrec doesn't use any mmx/xmm regs anyway. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@628 96395faa-99c1-11dd-bbfe-3dabce05a288
447 lines
16 KiB
C++
447 lines
16 KiB
C++
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2009 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "PrecompiledHeader.h"
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#include "PsxCommon.h"
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#include "Common.h"
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using namespace R3000A;
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// Used to flag delay slot instructions when throwig exceptions.
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bool iopIsDelaySlot = false;
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static bool branch2 = 0;
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static u32 branchPC;
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static void doBranch(s32 tar); // forward declared prototype
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struct irxlib {
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char name[16];
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char names[64][64];
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int maxn;
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};
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#define IRXLIBS 14
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irxlib irxlibs[32] = {
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/*00*/ { { "sysmem" } ,
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{ "start", "init_memory", "retonly", "return_addr_of_memsize",
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"AllocSysMemory", "FreeSysMemory", "QueryMemSize", "QueryMaxFreeMemSize",
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"QueryTotalFreeMemSize", "QueryBlockTopAddress", "QueryBlockSize", "retonly",
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"retonly", "retonly", "Kprintf", "set_Kprintf" } ,
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16 },
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/*01*/ { { "loadcore" } ,
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{ "start", "retonly", "retonly_", "return_LibraryEntryTable",
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"FlushIcache", "FlushDcache", "RegisterLibraryEntries", "ReleaseLibraryEntries",
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"findFixImports", "restoreImports", "RegisterNonAutoLinkEntries", "QueryLibraryEntryTable",
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"QueryBootMode", "RegisterBootMode", "setFlag", "resetFlag",
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"linkModule", "unlinkModule", "retonly_", "retonly_",
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"registerFunc", "jumpA0001B34", "read_header", "load_module",
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"findImageInfo" },
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25 },
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/*02*/ { { "excepman" } ,
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{ "start", "reinit", "deinit", "getcommon",
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"RegisterExceptionHandler", "RegisterPriorityExceptionHandler",
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"RegisterDefaultExceptionHandler", "ReleaseExceptionHandler",
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"ReleaseDefaultExceptionHandler" } ,
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9 },
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/*03_4*/{ { "intrman" } ,
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{ "start", "return_0", "deinit", "call3",
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"RegisterIntrHandler", "ReleaseIntrHandler", "EnableIntr", "DisableIntr",
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"CpuDisableIntr", "CpuEnableIntr", "syscall04", "syscall08",
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"resetICTRL", "setICTRL", "syscall0C", "call15",
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"call16", "CpuSuspendIntr", "CpuResumeIntr", "CpuSuspendIntr",
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"CpuResumeIntr", "syscall10", "syscall14", "QueryIntrContext",
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"QueryIntrStack", "iCatchMultiIntr", "retonly", "call27",
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"set_h1", "reset_h1", "set_h2", "reset_h2" } ,
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0x20 },
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/*05*/ { { "ssbusc" } ,
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{ "start", "retonly", "return_0", "retonly",
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"setTable1", "getTable1", "setTable2", "getTable2",
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"setCOM_DELAY_1st", "getCOM_DELAY_1st", "setCOM_DELAY_2nd", "getCOM_DELAY_2nd",
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"setCOM_DELAY_3rd", "getCOM_DELAY_3rd", "setCOM_DELAY_4th", "getCOM_DELAY_4th",
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"setCOM_DELAY", "getCOM_DELAY" } ,
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18 },
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/*06*/ { { "dmacman" } ,
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{ "start", "retonly", "deinit", "retonly",
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"SetD_MADR", "GetD_MADR", "SetD_BCR", "GetD_BCR",
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"SetD_CHCR", "GetD_CHCR", "SetD_TADR", "GetD_TADR",
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"Set_4_9_A", "Get_4_9_A", "SetDPCR", "GetDPCR",
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"SetDPCR2", "GetDPCR2", "SetDPCR3", "GetDPCR3",
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"SetDICR", "GetDICR", "SetDICR2", "GetDICR2",
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"SetBF80157C", "GetBF80157C", "SetBF801578", "GetBF801578",
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"SetDMA", "SetDMA_chainedSPU_SIF0", "SetDMA_SIF0", "SetDMA_SIF1",
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"StartTransfer", "SetVal", "EnableDMAch", "DisableDMAch" } ,
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36 },
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/*07_8*/{ { "timrman" } ,
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{ "start", "retonly", "retonly", "call3",
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"AllocHardTimer", "ReferHardTimer", "FreeHardTimer", "SetTimerMode",
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"GetTimerStatus", "SetTimerCounter", "GetTimerCounter", "SetTimerCompare",
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"GetTimerCompare", "SetHoldMode", "GetHoldMode", "GetHoldReg",
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"GetHardTimerIntrCode" } ,
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17 },
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/*09*/ { { "sysclib" } ,
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{ "start", "reinit", "retonly", "retonly",
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"setjmp", "longjmp", "toupper", "tolower",
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"look_ctype_table", "get_ctype_table", "memchr", "memcmp",
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"memcpy", "memmove", "memset", "bcmp",
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"bcopy", "bzero", "prnt", "sprintf",
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"strcat", "strchr", "strcmp", "strcpy",
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"strcspn", "index", "rindex", "strlen",
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"strncat", "strncmp", "strncpy", "strpbrk",
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"strrchr", "strspn", "strstr", "strtok",
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"strtol", "atob", "strtoul", "wmemcopy",
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"wmemset", "vsprintf" } ,
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0x2b },
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/*0A*/ { { "heaplib" } ,
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{ "start", "retonly", "retonly", "retonly",
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"CreateHeap", "DestroyHeap", "HeapMalloc", "HeapFree",
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"HeapSize", "retonly", "retonly", "call11",
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"call12", "call13", "call14", "call15",
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"retonly", "retonly" } ,
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18 },
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/*13*/ { { "stdio" } ,
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{ "start", "unknown", "unknown", "unknown",
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"printf" } ,
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5 },
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/*14*/ { { "sifman" } ,
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{ "start", "retonly", "deinit", "retonly",
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"sceSif2Init", "sceSifInit", "sceSifSetDChain", "sceSifSetDma",
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"sceSifDmaStat", "sceSifSend", "sceSifSendSync", "sceSifIsSending",
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"sceSifSetSIF0DMA", "sceSifSendSync0", "sceSifIsSending0", "sceSifSetSIF1DMA",
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"sceSifSendSync1", "sceSifIsSending1", "sceSifSetSIF2DMA", "sceSifSendSync2",
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"sceSifIsSending2", "getEEIOPflags", "setEEIOPflags", "getIOPEEflags",
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"setIOPEEflags", "getEErcvaddr", "getIOPrcvaddr", "setIOPrcvaddr",
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"call28", "sceSifCheckInit", "setSif0CB", "resetSif0CB",
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"retonly", "retonly", "retonly", "retonly" } ,
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36 },
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/*16*/ { { "sifcmd" } ,
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{ "start", "retonly", "deinit", "retonly",
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"sceSifInitCmd", "sceSifExitCmd", "sceSifGetSreg", "sceSifSetSreg",
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"sceSifSetCmdBuffer", "sceSifSetSysCmdBuffer",
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"sceSifAddCmdHandler", "sceSifRemoveCmdHandler",
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"sceSifSendCmd", "isceSifSendCmd", "sceSifInitRpc", "sceSifBindRpc",
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"sceSifCallRpc", "sceSifRegisterRpc",
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"sceSifCheckStatRpc", "sceSifSetRpcQueue",
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"sceSifGetNextRequest", "sceSifExecRequest",
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"sceSifRpcLoop", "sceSifGetOtherData",
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"sceSifRemoveRpc", "sceSifRemoveRpcQueue",
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"setSif1CB", "resetSif1CB",
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"retonly", "retonly", "retonly", "retonly" } ,
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32 },
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/*19*/ { { "cdvdman" } ,
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{ "start", "retonly", "retonly", "retonly",
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"sceCdInit", "sceCdStandby", "sceCdRead", "sceCdSeek",
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"sceCdGetError", "sceCdGetToc", "sceCdSearchFile", "sceCdSync",
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"sceCdGetDiskType", "sceCdDiskReady", "sceCdTrayReq", "sceCdStop",
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"sceCdPosToInt", "sceCdIntToPos", "retonly", "call19",
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"sceDvdRead", "sceCdCheckCmd", "_sceCdRI", "sceCdWriteILinkID",
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"sceCdReadClock", "sceCdWriteRTC", "sceCdReadNVM", "sceCdWriteNVM",
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"sceCdStatus", "sceCdApplySCmd", "setHDmode", "sceCdOpenConfig",
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"sceCdCloseConfig", "sceCdReadConfig", "sceCdWriteConfig", "sceCdReadKey",
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"sceCdDecSet", "sceCdCallback", "sceCdPause", "sceCdBreak",
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"call40", "sceCdReadConsoleID", "sceCdWriteConsoleID", "sceCdGetMecaconVersion",
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"sceCdGetReadPos", "AudioDigitalOut", "sceCdNop", "_sceGetFsvRbuf",
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"_sceCdstm0Cb", "_sceCdstm1Cb", "_sceCdSC", "_sceCdRC",
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"sceCdForbidDVDP", "sceCdReadSubQ", "sceCdApplyNCmd", "AutoAdjustCtrl",
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"sceCdStInit", "sceCdStRead", "sceCdStSeek", "sceCdStStart",
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"sceCdStStat", "sceCdStStop" } ,
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62 },
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/*??*/ { { "sio2man" } ,
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{ "start", "retonly", "deinit", "retonly",
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"set8268_ctrl", "get8268_ctrl", "get826C_recv1", "call7_send1",
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"call8_send1", "call9_send2", "call10_send2", "get8270_recv2",
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"call12_set_params", "call13_get_params", "get8274_recv3", "set8278",
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"get8278", "set827C", "get827C", "set8260_datain",
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"get8264_dataout", "set8280_intr", "get8280_intr", "signalExchange1",
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"signalExchange2", "packetExchange" } ,
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26 }
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};
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#define Ra0 (iopVirtMemR<char>(psxRegs.GPR.n.a0))
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#define Ra1 (iopVirtMemR<char>(psxRegs.GPR.n.a1))
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#define Ra2 (iopVirtMemR<char>(psxRegs.GPR.n.a2))
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#define Ra3 (iopVirtMemR<char>(psxRegs.GPR.n.a3))
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const char* intrname[]={
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"INT_VBLANK", "INT_GM", "INT_CDROM", "INT_DMA", //00
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"INT_RTC0", "INT_RTC1", "INT_RTC2", "INT_SIO0", //04
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"INT_SIO1", "INT_SPU", "INT_PIO", "INT_EVBLANK", //08
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"INT_DVD", "INT_PCMCIA", "INT_RTC3", "INT_RTC4", //0C
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"INT_RTC5", "INT_SIO2", "INT_HTR0", "INT_HTR1", //10
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"INT_HTR2", "INT_HTR3", "INT_USB", "INT_EXTR", //14
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"INT_FWRE", "INT_FDMA", "INT_1A", "INT_1B", //18
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"INT_1C", "INT_1D", "INT_1E", "INT_1F", //1C
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"INT_dmaMDECi", "INT_dmaMDECo", "INT_dmaGPU", "INT_dmaCD", //20
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"INT_dmaSPU", "INT_dmaPIO", "INT_dmaOTC", "INT_dmaBERR", //24
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"INT_dmaSPU2", "INT_dma8", "INT_dmaSIF0", "INT_dmaSIF1", //28
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"INT_dmaSIO2i", "INT_dmaSIO2o", "INT_2E", "INT_2F", //2C
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"INT_30", "INT_31", "INT_32", "INT_33", //30
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"INT_34", "INT_35", "INT_36", "INT_37", //34
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"INT_38", "INT_39", "INT_3A", "INT_3B", //38
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"INT_3C", "INT_3D", "INT_3E", "INT_3F", //3C
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"INT_MAX" //40
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};
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void zeroEx()
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{
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#ifdef PCSX2_DEVBUILD
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u32 pc;
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u32 code;
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const char *lib;
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char *fname = NULL;
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int i;
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if (!Config.PsxOut) return;
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pc = psxRegs.pc;
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while (iopMemRead32(pc) != 0x41e00000) pc-=4;
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lib = iopVirtMemR<char>(pc+12);
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code = iopMemRead32(psxRegs.pc - 4) & 0xffff;
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for (i=0; i<IRXLIBS; i++) {
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if (!strncmp(lib, irxlibs[i].name, 8)) {
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if (code >= (u32)irxlibs[i].maxn) break;
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fname = irxlibs[i].names[code];
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//if( strcmp(fname, "setIOPrcvaddr") == 0 ) {
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// SysPrintf("yo\n");
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// varLog |= 0x100000;
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// Log = 1;
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// }
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break;
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}
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}
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{char libz[9]; memcpy(libz, lib, 8); libz[8]=0;
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PSXBIOS_LOG("%s: %s (%x)"
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" (%x, %x, %x, %x)" //comment this line to disable param showing
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, libz, fname == NULL ? "unknown" : fname, code,
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psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
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}
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// Log=0;
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// if (!strcmp(lib, "intrman") && code == 0x11) Log=1;
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// if (!strcmp(lib, "sifman") && code == 0x5) Log=1;
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// if (!strcmp(lib, "sifcmd") && code == 0x4) Log=1;
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// if (!strcmp(lib, "thbase") && code == 0x6) Log=1;
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/*
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if (!strcmp(lib, "sifcmd") && code == 0xe) {
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branchPC = psxRegs.GPR.n.ra;
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psxRegs.GPR.n.v0 = 0;
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return;
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}
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*/
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if (!strncmp(lib, "ioman", 5) && code == 7) {
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if (psxRegs.GPR.n.a0 == 1) {
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pc = psxRegs.pc;
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bios_write();
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psxRegs.pc = pc;
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}
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}
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if (!strncmp(lib, "sysmem", 6) && code == 0xe) {
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bios_printf();
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psxRegs.pc = psxRegs.GPR.n.ra;
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}
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if (!strncmp(lib, "loadcore", 8) && code == 6) {
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DevCon::WriteLn("loadcore RegisterLibraryEntries (%x): %8.8s", params psxRegs.pc, iopVirtMemR<char>(psxRegs.GPR.n.a0+12));
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}
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if (!strncmp(lib, "intrman", 7) && code == 4) {
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DevCon::WriteLn("intrman RegisterIntrHandler (%x): intr %s, handler %x", params psxRegs.pc, intrname[psxRegs.GPR.n.a0], psxRegs.GPR.n.a2);
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}
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if (!strncmp(lib, "sifcmd", 6) && code == 17) {
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DevCon::WriteLn("sifcmd sceSifRegisterRpc (%x): rpc_id %x", params psxRegs.pc, psxRegs.GPR.n.a1);
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}
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if (!strncmp(lib, "sysclib", 8))
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{
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switch (code)
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{
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case 0x16: // strcmp
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PSXBIOS_LOG(" \"%s\": \"%s\"", Ra0, Ra1);
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break;
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case 0x1e: // strncpy
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PSXBIOS_LOG(" \"%s\"", Ra1);
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break;
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}
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}
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/* psxRegs.pc = branchPC;
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pc = psxRegs.GPR.n.ra;
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while (psxRegs.pc != pc) psxCpu->ExecuteBlock();
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PSXBIOS_LOG("%s: %s (%x) END\n", lib, fname == NULL ? "unknown" : fname, code);*/
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#endif
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}
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/*/==========================================CALL LOG
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char* getName(char *file, u32 addr){
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FILE *f; u32 a;
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static char name[100];
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f=fopen(file, "r");
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if (!f)
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name[0]=0;
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else{
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while (!feof(f)){
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fscanf(f, "%08X %s\n", &a, name);
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if (a==addr)break;
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}
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fclose(f);
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}
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return name;
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}
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void spyFunctions(){
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register irxImageInfo *iii;
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if (psxRegs.pc >= 0x200000) return;
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for (iii=(irxImageInfo*)PSXM(0x800); iii && iii->text_size;
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iii=iii->next ? (irxImageInfo*)PSXM(iii->next) : NULL)
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if (iii->vaddr<=psxRegs.pc && psxRegs.pc<iii->vaddr+iii->text_size+iii->data_size+iii->bss_size){
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if (strcmp("secrman_for_cex", PSXM(iii->name))==0){
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char *name=getName("secrman.fun", psxRegs.pc-iii->vaddr);
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if (strncmp("__push_params", name, 13)==0){
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PAD_LOG(PSXM(psxRegs.GPR.n.a0), psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
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}else{
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PAD_LOG("secrman: %s (ra=%06X cycle=%d)\n", name, psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}}else
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if (strcmp("mcman", PSXM(iii->name))==0){
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PAD_LOG("mcman: %s (ra=%06X cycle=%d)\n", getName("mcman.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}else
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if (strcmp("padman", PSXM(iii->name))==0){
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PAD_LOG("padman: %s (ra=%06X cycle=%d)\n", getName("padman.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}else
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if (strcmp("sio2man", PSXM(iii->name))==0){
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PAD_LOG("sio2man: %s (ra=%06X cycle=%d)\n", getName("sio2man.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}
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break;
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}
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}
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*/
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/*********************************************************
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* Register branch logic *
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* Format: OP rs, offset *
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*********************************************************/
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#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_);
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#define RepZBranchLinki32(op) if(_i32(_rRs_) op 0) { _SetLink(31); doBranch(_BranchTarget_); }
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void psxBGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0
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void psxBGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link
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void psxBGTZ() { RepZBranchi32(>) } // Branch if Rs > 0
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void psxBLEZ() { RepZBranchi32(<=) } // Branch if Rs <= 0
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|
void psxBLTZ() { RepZBranchi32(<) } // Branch if Rs < 0
|
|
void psxBLTZAL() { RepZBranchLinki32(<) } // Branch if Rs < 0 and link
|
|
|
|
/*********************************************************
|
|
* Register branch logic *
|
|
* Format: OP rs, rt, offset *
|
|
*********************************************************/
|
|
#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_);
|
|
|
|
void psxBEQ() { RepBranchi32(==) } // Branch if Rs == Rt
|
|
void psxBNE() { RepBranchi32(!=) } // Branch if Rs != Rt
|
|
|
|
/*********************************************************
|
|
* Jump to target *
|
|
* Format: OP target *
|
|
*********************************************************/
|
|
void psxJ() { doBranch(_JumpTarget_); }
|
|
void psxJAL() { _SetLink(31); doBranch(_JumpTarget_); /*spyFunctions();*/ }
|
|
|
|
/*********************************************************
|
|
* Register jump *
|
|
* Format: OP rs, rd *
|
|
*********************************************************/
|
|
void psxJR() { doBranch(_u32(_rRs_)); }
|
|
void psxJALR() { if (_Rd_) { _SetLink(_Rd_); } doBranch(_u32(_rRs_)); }
|
|
|
|
///////////////////////////////////////////
|
|
// These macros are used to assemble the repassembler functions
|
|
|
|
static __forceinline void execI()
|
|
{
|
|
psxRegs.code = iopMemRead32(psxRegs.pc);
|
|
|
|
PSXCPU_LOG("%s\n", disR3000AF(psxRegs.code, psxRegs.pc));
|
|
|
|
psxRegs.pc+= 4;
|
|
psxRegs.cycle++;
|
|
psxCycleEE-=8;
|
|
|
|
psxBSC[psxRegs.code >> 26]();
|
|
}
|
|
|
|
|
|
static void doBranch(s32 tar) {
|
|
branch2 = iopIsDelaySlot = true;
|
|
branchPC = tar;
|
|
execI();
|
|
iopIsDelaySlot = false;
|
|
psxRegs.pc = branchPC;
|
|
|
|
psxBranchTest();
|
|
}
|
|
|
|
static void intAlloc() {
|
|
}
|
|
|
|
static void intReset() {
|
|
}
|
|
|
|
static void intExecute() {
|
|
for (;;) execI();
|
|
}
|
|
|
|
#ifdef _DEBUG
|
|
extern u32 psxdump;
|
|
extern void iDumpPsxRegisters(u32,u32);
|
|
#endif
|
|
|
|
static s32 intExecuteBlock( s32 eeCycles )
|
|
{
|
|
psxBreak = 0;
|
|
psxCycleEE = eeCycles;
|
|
|
|
while (psxCycleEE > 0){
|
|
branch2 = 0;
|
|
while (!branch2) {
|
|
execI();
|
|
}
|
|
}
|
|
return psxBreak + psxCycleEE;
|
|
}
|
|
|
|
static void intClear(u32 Addr, u32 Size) {
|
|
}
|
|
|
|
static void intShutdown() {
|
|
}
|
|
|
|
R3000Acpu psxInt = {
|
|
intAlloc,
|
|
intReset,
|
|
intExecute,
|
|
intExecuteBlock,
|
|
intClear,
|
|
intShutdown
|
|
};
|