6 Commits

Author	SHA1	Message	Date
QingShan Zhang	4b87ceb34d	[NFC] fix test case issue that with wrong label check. ... llvm-svn: 349439	2018-12-18 04:25:41 +00:00
Stefan Pintilie	edd36f6e4c	[PowerPC] Make no-PIC default to match GCC - LLVM ... Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298	2018-12-04 20:14:57 +00:00
Stefan Pintilie	36931cd8d0	Revert "[PowerPC] Make no-PIC default to match GCC - LLVM" ... This reverts commit r347069 llvm-svn: 347076	2018-11-16 19:24:23 +00:00
Stefan Pintilie	e3d9879744	[PowerPC] Make no-PIC default to match GCC - LLVM ... Set -fno-PIC as the default option. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 347069	2018-11-16 18:36:21 +00:00
QingShan Zhang	46d19bc0c7	[PowerPC] Add a peephole post RA to transform the inst that fed by add ... If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 llvm-svn: 340149	2018-08-20 02:52:55 +00:00
QingShan Zhang	495146cd04	If the arch is P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction when we are loading a floating, ... and expand it post RA basing on the register pressure. However, we miss to do the add-imm peephole for these pseudo instruction. Differential Revision: https://reviews.llvm.org/D47568 Reviewed By: Nemanjai llvm-svn: 335024	2018-06-19 06:54:51 +00:00