Commit Graph

276 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
5fdcc970a2 Don't fold insufficiently aligned ldr/str into ldm/stm instructions.
An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.

This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.

Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.

llvm-svn: 93393
2010-01-14 00:54:10 +00:00
Jakob Stoklund Olesen
e82ce92826 Move kill flags when the same register occurs more than once in a sequence.
llvm-svn: 92058
2009-12-23 21:34:03 +00:00
Jakob Stoklund Olesen
17a89f1f8a Handle undef operands properly.
llvm-svn: 92054
2009-12-23 21:28:42 +00:00
Jakob Stoklund Olesen
f18e89a0bf Make insert position available to MergeOpsUpdate.
Rearrange arguments.
No functional changes

llvm-svn: 92053
2009-12-23 21:28:37 +00:00
Jakob Stoklund Olesen
55c03c7cef Perform kill flag calculations in new method. No functional changes.
llvm-svn: 92052
2009-12-23 21:28:31 +00:00
Jakob Stoklund Olesen
423f1e70e6 Move repeated code to a new method. No functional change.
llvm-svn: 92051
2009-12-23 21:28:23 +00:00
Douglas Gregor
f39dd74a3f Fix a bunch of little errors that Clang complains about when its being pedantic
llvm-svn: 91764
2009-12-19 07:05:23 +00:00
Chris Lattner
9ce833945e improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!

llvm-svn: 90365
2009-12-03 00:50:42 +00:00
Evan Cheng
e43198c166 When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
llvm-svn: 88734
2009-11-14 01:50:00 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend.
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
Nick Lewycky
2b8400628d Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
2009-10-25 06:57:41 +00:00
Nick Lewycky
711c726c97 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
2009-10-25 06:33:48 +00:00
Evan Cheng
d411ac1267 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
llvm-svn: 84842
2009-10-22 06:47:35 +00:00
Evan Cheng
4dd7d7156e Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
Evan Cheng
d2bf81c7af Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
llvm-svn: 83058
2009-09-29 07:07:30 +00:00
Evan Cheng
ffe6da0734 Enable pre-regalloc load / store multiple pass for Thumb2.
llvm-svn: 82893
2009-09-27 09:46:04 +00:00
Evan Cheng
c4e3168b65 Add comment.
llvm-svn: 82836
2009-09-26 02:43:36 +00:00
Evan Cheng
c0edc5ee28 Code clean up and prepare for Thumb2 support. No functionality changes.
llvm-svn: 82805
2009-09-25 21:44:53 +00:00
Dan Gohman
0ac693a89e Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794
2009-09-25 20:36:54 +00:00
Jim Grosbach
6293edbcbf Update register class references to use the global constant ARM::*RegisterClass names.
llvm-svn: 81556
2009-09-11 19:49:06 +00:00
Jakob Stoklund Olesen
9496240bbf Simplify RegScavenger::FindUnusedReg.
- Drop the Candidates argument and fix all callers. Now that RegScavenger
  tracks available registers accurately, there is no need to restict the
  search.
- Make sure that no aliases of the found register are in use. This was a potential bug.

llvm-svn: 79369
2009-08-18 21:14:54 +00:00
Owen Anderson
9df206d02d Push LLVMContexts through the IntegerType APIs.
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
Jim Grosbach
3c898a99bd Whitespace cleanup. Remove trailing whitespace.
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
Evan Cheng
4046c75e96 Code refactoring. No functionality change.
llvm-svn: 78455
2009-08-08 03:20:32 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
2009-08-07 00:34:42 +00:00
Evan Cheng
2ec9ab08d8 Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
llvm-svn: 78104
2009-08-04 21:12:13 +00:00
Evan Cheng
04035adc46 Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
llvm-svn: 78057
2009-08-04 08:34:18 +00:00
Evan Cheng
5711586a17 Load / store multiple pass fixes for Thumb2. Not enabled yet.
llvm-svn: 78031
2009-08-04 01:43:45 +00:00
Torok Edwin
f955a6ef49 llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Evan Cheng
268b47b1fb Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
2009-07-11 06:43:01 +00:00
Evan Cheng
4249ad4c00 Remove a bogus assertion.
llvm-svn: 75206
2009-07-10 00:23:48 +00:00
Evan Cheng
5bde39cb50 Initial support for load / store multiple opt pass Thumb2 support (post-allocation only). It's kind of there, but not quite. I'll return to this later.
llvm-svn: 75190
2009-07-09 23:11:34 +00:00
Evan Cheng
ef49d9c75b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
Torok Edwin
358888da3a Implement changes from Chris's feedback.
Finish converting lib/Target.

llvm-svn: 75043
2009-07-08 20:53:28 +00:00
Torok Edwin
ad3be984b7 Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)

llvm-svn: 75018
2009-07-08 18:01:40 +00:00
Evan Cheng
f18de63563 Enable arm pre-allocation load / store multiple optimization pass.
llvm-svn: 73791
2009-06-19 23:17:27 +00:00
Evan Cheng
667924dc46 Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.
llvm-svn: 73749
2009-06-19 01:59:04 +00:00
Evan Cheng
82a8ab8a8e - Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.

llvm-svn: 73671
2009-06-18 02:04:01 +00:00
Evan Cheng
c007d30aad Typo.
llvm-svn: 73422
2009-06-15 21:18:20 +00:00
Evan Cheng
659d2536b8 Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
llvm-svn: 73413
2009-06-15 20:54:56 +00:00
Evan Cheng
9c5f793659 Silence a warning.
llvm-svn: 73406
2009-06-15 19:36:32 +00:00
Evan Cheng
3219c7fbe5 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381
2009-06-15 08:28:29 +00:00
Evan Cheng
d0a66e438f Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291
2009-06-13 09:12:55 +00:00
Evan Cheng
ea31ec569b Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
llvm-svn: 72955
2009-06-05 19:08:58 +00:00
Evan Cheng
35a504c6e9 When merging multiple load / store instructions. Use the DebugLoc of the first one.
llvm-svn: 72952
2009-06-05 18:19:23 +00:00
Evan Cheng
d240854a82 Code clean up: return vector by reference rather than by value. No functionality changes.
llvm-svn: 72950
2009-06-05 17:56:14 +00:00
Evan Cheng
e3a05e6690 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
llvm-svn: 72826
2009-06-04 01:15:28 +00:00
Evan Cheng
82f8fa333e Temporarily revert 72756 for now.
llvm-svn: 72757
2009-06-03 07:40:47 +00:00
Evan Cheng
5afbef29fa Fold preceding / trailing base inc / dec into the single load / store as well.
llvm-svn: 72756
2009-06-03 06:14:58 +00:00
Bill Wendling
e421c8f63d Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).

llvm-svn: 71722
2009-05-13 21:33:08 +00:00