Commit Graph

14442 Commits

Author SHA1 Message Date
Evan Cheng
a1d639a0ea Fix a bug in DAGCombiner::MatchBSwapHWord. Make sure the node has operands before referencing them. rdar://12868039
llvm-svn: 170078
2012-12-13 01:34:32 +00:00
Pedro Artigas
0e3841e00e Make the MCStreamer have a reset method and call that after finalization of the asm printer,
also changed MCContext to a single reset only method for simplicity as requested on the list

llvm-svn: 170041
2012-12-12 22:59:46 +00:00
Evan Cheng
e2dde0e860 Fix a logic bug in inline expansion of memcpy / memset with an overlapping
load / store pair. It's not legal to use a wider load than the size of
the remaining bytes if it's the first pair of load / store.

llvm-svn: 170018
2012-12-12 20:43:23 +00:00
Evan Cheng
e42df0ea81 Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?

This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.

llvm-svn: 169959
2012-12-12 02:34:41 +00:00
Evan Cheng
d1c2821678 - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.

llvm-svn: 169954
2012-12-12 01:32:07 +00:00
Manman Ren
d29a3f8737 DAGCombine: clamp hi bit in APInt::getBitsSet to avoid assertion
rdar://12838504

llvm-svn: 169951
2012-12-12 01:13:50 +00:00
Evan Cheng
0e6ff04636 Avoid using lossy load / stores for memcpy / memset expansion. e.g.
f64 load / store on non-SSE2 x86 targets.

llvm-svn: 169944
2012-12-12 00:42:09 +00:00
Evan Cheng
b9b90d7aed Replace TargetLowering::isIntImmLegal() with
ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined
term for something like integer immediate materialization. It is always possible
to materialize an integer immediate. Whether to use it for memcpy expansion is
more a "cost" conceern.

llvm-svn: 169929
2012-12-11 23:26:14 +00:00
Eric Christopher
1a93fc9d67 Update some comments.
llvm-svn: 169907
2012-12-11 19:42:09 +00:00
Joel Jones
0038ea3653 Add comment for load folding
llvm-svn: 169880
2012-12-11 16:10:25 +00:00
Patrik Hagglund
caaedc6ade Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
llvm-svn: 169854
2012-12-11 11:14:33 +00:00
Patrik Hagglund
d09c604a20 Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,
instead of EVTs.

llvm-svn: 169851
2012-12-11 10:24:48 +00:00
Patrik Hagglund
f45125a118 Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.

Accordingly, add bitsLT (and similar) to MVT.

llvm-svn: 169850
2012-12-11 10:20:51 +00:00
Patrik Hagglund
4dc66d3907 Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,
from EVT.

llvm-svn: 169849
2012-12-11 10:16:19 +00:00
Patrik Hagglund
19b28301f3 Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs.

llvm-svn: 169848
2012-12-11 10:09:23 +00:00
Patrik Hagglund
48f063d9a8 Change TargetLowering::TransformToType to contain MVTs, instead of
EVTs.

llvm-svn: 169847
2012-12-11 10:05:04 +00:00
Patrik Hagglund
9597517d65 Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.

llvm-svn: 169845
2012-12-11 09:57:18 +00:00
Patrik Hagglund
4ab6c88920 Change TargetLowering::getTypeToPromoteTo to take and return MVTs,
instead of EVTs.

llvm-svn: 169844
2012-12-11 09:54:23 +00:00
Patrik Hagglund
7692ba3a13 Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.
llvm-svn: 169843
2012-12-11 09:51:27 +00:00
Patrik Hagglund
cfd4d97792 Change TargetLowering::getCondCodeAction to take an MVT, instead of
EVT.

llvm-svn: 169842
2012-12-11 09:48:14 +00:00
Patrik Hagglund
dec1aa5bc5 Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.
llvm-svn: 169841
2012-12-11 09:42:24 +00:00
Patrik Hagglund
6c9d0f4058 Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.
llvm-svn: 169840
2012-12-11 09:39:09 +00:00
Patrik Hagglund
8fcc9acaaa Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.
llvm-svn: 169839
2012-12-11 09:32:56 +00:00
Patrik Hagglund
0b24527a59 Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.

Accordingly, change RegDefIter to contain MVTs instead of EVTs.

llvm-svn: 169838
2012-12-11 09:31:43 +00:00
Patrik Hagglund
758f9c5011 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

llvm-svn: 169837
2012-12-11 09:10:33 +00:00
Chandler Carruth
ac8f03ddc1 Fix a miscompile in the DAG combiner. Previously, we would incorrectly
try to reduce the width of this load, and would end up transforming:

  (truncate (lshr (sextload i48 <ptr> as i64), 32) to i32)
to
  (truncate (zextload i32 <ptr+4> as i64) to i32)

We lost the sext attached to the load while building the narrower i32
load, and replaced it with a zext because lshr always zext's the
results. Instead, bail out of this combine when there is a conflict
between a sextload and a zext narrowing. The rest of the DAG combiner
still optimize the code down to the proper single instruction:

  movswl 6(...),%eax

Which is exactly what we wanted. Previously we read past the end *and*
missed the sign extension:

  movl 6(...), %eax

llvm-svn: 169802
2012-12-11 00:36:57 +00:00
Chad Rosier
0b2e4a1ba8 Fall back to the selection dag isel to select tail calls.
This shouldn't affect codegen for -O0 compiles as tail call markers are not
emitted in unoptimized compiles.  Testing with the external/internal nightly
test suite reveals no change in compile time performance.  Testing with -O1,
-O2 and -O3 with fast-isel enabled did not cause any compile-time or
execution-time failures.  All tests were performed on my x86 machine.
I'll monitor our arm testers to ensure no regressions occur there.

In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue
and objc_retainAutoreleaseReturnValue as tail calls unconditionally.  While
it's theoretically true that this is just an optimization, it's an
optimization that we very much want to happen even at -O0, or else ARC
applications become substantially harder to debug.

Part of rdar://12553082

llvm-svn: 169796
2012-12-11 00:18:02 +00:00
Eric Christopher
2d11b002bc Refactor out the abbreviation handling into a separate class that
controls each of the abbreviation sets (only a single one at the
moment) and computes offsets separately as well for each set
of DIEs.

No real function change, ordering of abbreviations for the skeleton
CU changed but only because we're computing in a separate order. Fix
the testcase not to care.

llvm-svn: 169793
2012-12-10 23:34:43 +00:00
Evan Cheng
86dd733bc8 Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
   bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
   x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
   if it's not possible to materialize an integer immediate with a single
   instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
   are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
   Also increase the threshold to something reasonable (8 for memset, 4 pairs
   for memcpy).

This significantly improves Dhrystone, up to 50% on ARM iOS devices.

rdar://12760078

llvm-svn: 169791
2012-12-10 23:21:26 +00:00
Lang Hames
313bb2d202 Defer call to InitSections until after MCContext has been initialized. If
InitSections is called before the MCContext is initialized it could cause
duplicate temporary symbols to be emitted later (after context initialization
resets the temporary label counter).

llvm-svn: 169785
2012-12-10 22:49:11 +00:00
Eric Christopher
b3b9b702cb Rearrange vars and make comments more obvious.
llvm-svn: 169780
2012-12-10 22:25:41 +00:00
Eric Christopher
5b2c77f097 Remove blank line at top of file.
llvm-svn: 169779
2012-12-10 22:25:38 +00:00
Eric Christopher
9fed81d6be Fix a coding style nit.
llvm-svn: 169776
2012-12-10 22:00:20 +00:00
Tom Stellard
3801f0fed5 LegalizeDAG: Allow type promotion of scalar loads
llvm-svn: 169773
2012-12-10 21:41:58 +00:00
Tom Stellard
c8da3bd0a1 LegalizeDAG: Allow type promotion for scalar stores
llvm-svn: 169772
2012-12-10 21:41:54 +00:00
Eric Christopher
c67794597d Use the somewhat semantic term "split dwarf" it more matches what's
going on and makes a lot of the terminology in comments make more sense.

llvm-svn: 169758
2012-12-10 19:51:21 +00:00
Eric Christopher
2bf7bdcd23 Delete the FissionCU.
llvm-svn: 169757
2012-12-10 19:51:18 +00:00
Eric Christopher
67243c354a Reorder fission variables.
llvm-svn: 169756
2012-12-10 19:51:13 +00:00
Hal Finkel
3b65689ab9 Use GetUnderlyingObjects in misched
misched used GetUnderlyingObject in order to break false load/store
dependencies, and the -enable-aa-sched-mi feature similarly relied on
GetUnderlyingObject in order to ensure it is safe to use the aliasing analysis.
Unfortunately, GetUnderlyingObject does not recurse through phi nodes, and so
(especially due to LSR) all of these mechanisms failed for
induction-variable-dependent loads and stores inside loops.

This change replaces uses of GetUnderlyingObject with GetUnderlyingObjects
(which will recurse through phi and select instructions) in misched.

Andy reviewed, tested and simplified this patch; Thanks!

llvm-svn: 169744
2012-12-10 18:49:16 +00:00
Craig Topper
0f4945c76d Teach DAG combine to handle vector add/sub with vectors of all 0s.
llvm-svn: 169727
2012-12-10 08:12:29 +00:00
Craig Topper
c03f63d739 Remove extra blank line.
llvm-svn: 169692
2012-12-09 08:20:52 +00:00
Craig Topper
a6f44fb06b Teach DAG combine to handle vector logical operations with vectors of all 1s or all 0s. These cases can show up when vectors are split for legalizing. Fix some tests that were dependent on these cases not being combined.
llvm-svn: 169684
2012-12-08 22:49:19 +00:00
Jakob Stoklund Olesen
1386769d53 Add higher-level API for dealing with bundled MachineInstrs.
This is still a work in progress. The purpose is to make bundling and
unbundling operations explicit, and to catch errors where bundles are
broken or created inadvertently.

The old IsInsideBundle flag is replaced by two MI flags: BundledPred
which has the same meaning as IsInsideBundle, and BundledSucc which is
set on instructions that are bundled with a successor. Having two flags
provdes redundancy to detect when a bundle is inadvertently torn by a
splice() or insert(), and it makes it possible to write bundle iterators
that don't need to peek at adjacent instructions.

The new flags can't be manipulated directly (once setIsInsideBundle is
gone). Instead there are MI functions to make and break bundle bonds.

The setIsInsideBundle function will be removed in a future commit. It
should be replaced by bundleWithPred().

llvm-svn: 169583
2012-12-07 04:23:29 +00:00
Pedro Artigas
8e61717b97 fixed valgrind issues of prior commit, this change applies r169456 changes back to the tree with fixes. on darwin no valgrind issues exist in the tests that used to fail.
original change description:

change MCContext to work on the doInitialization/doFinalization model

reviewed by Evan Cheng <evan.cheng@apple.com>

llvm-svn: 169553
2012-12-06 22:12:44 +00:00
Evan Cheng
4cdc6c4eef Replace r169459 with something safer. Rather than having computeMaskedBits to
understand target implementation of any_extend / extload, just generate
zero_extend in place of any_extend for liveouts when the target knows the
zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz).

rdar://12771555

llvm-svn: 169536
2012-12-06 19:13:27 +00:00
Nadav Rotem
5b43aa0b29 Fix a bug in the code that merges consecutive stores. Previously we did not
check if loads that happen in between stores alias with the first store in the
chain, only with the second store onwards.

llvm-svn: 169516
2012-12-06 17:34:13 +00:00
Bill Wendling
9cb80ecabb s/getLowerBoundDefault/getDefaultLowerBound/ for consistency. Also put the more natural check first in the if-then statement.
llvm-svn: 169486
2012-12-06 07:55:19 +00:00
Bill Wendling
979b24c6ec Handle non-default array bounds.
Some languages, e.g. Ada and Pascal, allow you to specify that the array bounds
are different from the default (1 in these cases). If we have a lower bound
that's non-default, then we emit the lower bound. We also calculate the correct
upper bound in those cases.

llvm-svn: 169484
2012-12-06 07:38:10 +00:00
NAKAMURA Takumi
79cb136d31 Revert r169456, "change MCContext to work on the doInitialization/doFinalization model"
It broke many builders.

llvm-svn: 169462
2012-12-06 02:00:13 +00:00
Evan Cheng
c1db873871 Let targets provide hooks that compute known zero and ones for any_extend
and extload's. If they are implemented as zero-extend, or implicitly
zero-extend, then this can enable more demanded bits optimizations. e.g.

define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
  %tmp1 = icmp ult i32 %a, 100
  br i1 %tmp1, label %bb1, label %bb2
bb1:
  %tmp2 = load i16* %ptr, align 2
  br label %bb2
bb2:
  %tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
  %cmp = icmp ult i16 %tmp3, 24
  br i1 %cmp, label %bb3, label %exit
bb3:
  call void @bar() nounwind
  br label %exit
exit:
  ret void
}

This compiles to the followings before:
        push    {lr}
        mov     r2, #0
        cmp     r1, #99
        bhi     LBB0_2
@ BB#1:                                 @ %bb1
        ldrh    r2, [r0]
LBB0_2:                                 @ %bb2
        uxth    r0, r2
        cmp     r0, #23
        bhi     LBB0_4
@ BB#3:                                 @ %bb3
        bl      _bar
LBB0_4:                                 @ %exit
        pop     {lr}
        bx      lr

The uxth is not needed since ldrh implicitly zero-extend the high bits. With
this change it's eliminated.

rdar://12771555

llvm-svn: 169459
2012-12-06 01:28:01 +00:00