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215 Commits

Author SHA1 Message Date
Jason W Kim
1a423a93dc ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .o 
llvm-svn: 125025
 2011-02-07 19:07:11 +00:00
Jason W Kim
b0d4492aa1 Rework some .ARM.attribute work for improved gcc compatibility. 
Unified EmitTextAttribute for both Asm and Obj emission (.cpu only)
Added necessary cortex-A8 related attrs for codegen compat tests.

llvm-svn: 124995
 2011-02-07 00:49:53 +00:00
Evan Cheng
0dfe28a9b5 Last round of fixes for movw + movt global address codegen. 
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991
 2011-01-21 18:55:51 +00:00
Evan Cheng
53ec6fc591 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. 
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
 2011-01-17 08:03:18 +00:00
Jason W Kim
6464be5b92 JimG sez: "The value-kinds look like masks, but they're not consistently used 
that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.

llvm-svn: 123340
 2011-01-12 23:21:49 +00:00
Jason W Kim
ae183f9862 1. Support ELF pcrel relocations for movw/movt: 
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294
 2011-01-12 00:19:25 +00:00
Evan Cheng
05ef00f4dc Clean up ARM subtarget code by using Triple ADT. 
llvm-svn: 123276
 2011-01-11 21:46:47 +00:00
Anton Korobeynikov
d37cb4cd1c Model operand restrictions of mul-like instructions on ARMv5 via 
earlyclobber stuff. This should fix PRs 2313 and 8157.

Unfortunately, no testcase, since it'd be dependent on register
assignments.

llvm-svn: 122663
 2011-01-01 20:38:38 +00:00
Bill Wendling
9b2ef1c9be r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to 
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.

There is a test case, but unfortunately it's sensitive to random code changes.

<rdar://problem/8782223>

llvm-svn: 122131
 2010-12-18 02:13:59 +00:00
Bob Wilson
12f2b81599 Avoid report_fatal_error in ARM's PrintAsmOperand method. 
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

llvm-svn: 122100
 2010-12-17 23:06:42 +00:00
Jim Grosbach
ce773319e4 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974 
llvm-svn: 121990
 2010-12-16 19:11:16 +00:00
Jim Grosbach
1e943cc60d Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Jim Grosbach
e84e95e6d2 Refactor a bit for legibility. 
llvm-svn: 121790
 2010-12-14 21:10:47 +00:00
Jim Grosbach
13d82ea2b1 Make sure to propagate the predicate operands for LEApcrel to ADR. 
llvm-svn: 121788
 2010-12-14 20:45:47 +00:00
Bill Wendling
61720b79f9 The tLDR et al instructions were emitting either a reg/reg or reg/imm 
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
 2010-12-14 03:36:38 +00:00
Owen Anderson
c84f8c23b3 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire 
process cleaner.

llvm-svn: 121735
 2010-12-14 00:36:49 +00:00
Jim Grosbach
5658d982b4 Add a textual message to the assert. 
llvm-svn: 121349
 2010-12-09 01:23:51 +00:00
Jim Grosbach
da9353523f Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are 
referencing the stack pointer as they say they are.

llvm-svn: 121347
 2010-12-09 01:22:19 +00:00
Jim Grosbach
0e71db6919 Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

llvm-svn: 120635
 2010-12-02 00:28:45 +00:00
Jim Grosbach
b2a12afa5f Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594
 2010-12-01 19:47:31 +00:00
Jim Grosbach
b2044fcba1 Move the ARMAsmPrinter class defintiion into a header file. 
llvm-svn: 120551
 2010-12-01 03:45:07 +00:00
Jim Grosbach
aa96c057be Pseudo-ize ARM MOVPCRX 
llvm-svn: 120442
 2010-11-30 18:56:36 +00:00
Jim Grosbach
cb8193b99e Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. 
rdar://8685712

llvm-svn: 120438
 2010-11-30 18:30:19 +00:00
Bill Wendling
5030f8359b s/ARM::BRIND/ARM::BX/g to coincide with r120366. 
llvm-svn: 120371
 2010-11-30 00:48:15 +00:00
Jim Grosbach
89e90b7310 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00
Jim Grosbach
71042b51a1 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

llvm-svn: 120320
 2010-11-29 21:28:32 +00:00
Jim Grosbach
3e84f9d6cb ARM Pseudo-ize tBR_JTr. 
llvm-svn: 120310
 2010-11-29 19:32:47 +00:00
Jim Grosbach
9e2ed21ad0 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
llvm-svn: 120303
 2010-11-29 18:37:44 +00:00
Jim Grosbach
37233d0ea6 Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly 
in the MC lowering process.

llvm-svn: 119559
 2010-11-17 21:05:55 +00:00
Jim Grosbach
e0122f5d54 Add FIXMEs. 
llvm-svn: 119167
 2010-11-15 18:36:48 +00:00
Chris Lattner
b2daeac125 add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
 2010-11-15 05:19:05 +00:00
Chris Lattner
3a01d37b66 rename LowerToMCInst -> LowerARMMachineInstrToMCInst. 
llvm-svn: 119071
 2010-11-14 21:00:02 +00:00
Chris Lattner
4dac1b2742 even more simplifications. ARM MCInstLowering is now just 
a single function instead of a class.  It doesn't need the
complexity that X86 does.

llvm-svn: 119070
 2010-11-14 20:58:38 +00:00
Chris Lattner
2393da7c40 simplify and tidy up 
llvm-svn: 119066
 2010-11-14 20:31:06 +00:00
Jim Grosbach
c5001c0f1d Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes 
double quoting of ObjC symbol names in constant pool entries.

rdar://8652107

llvm-svn: 118688
 2010-11-10 17:59:10 +00:00
Jim Grosbach
4e3653e4e1 Update ARMConstantPoolValue to not use a modifier string. Use an explicit 
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623

llvm-svn: 118671
 2010-11-10 03:26:07 +00:00
Jim Grosbach
be0d795478 Change the ARMConstantPoolValue modifier string to an enumeration. This will 
help in MC'izing the references that use them.

llvm-svn: 118633
 2010-11-09 21:36:17 +00:00
Jim Grosbach
d98cc456d2 Handle ARM constant pool values that need an explicit reference to the '.' 
pseudo-label. (TLS stuff).

llvm-svn: 118609
 2010-11-09 19:40:22 +00:00
Jim Grosbach
2c60dfb555 Further MCize ARM constant pool values. This allows basic PIC references for 
object file emission.

llvm-svn: 118601
 2010-11-09 18:45:04 +00:00
Dale Johannesen
f16acd1325 Revert 118422 in search of bot verdancy. 
llvm-svn: 118429
 2010-11-08 19:17:22 +00:00
Jason W Kim
a253ed4e26 Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified. 
llvm-svn: 118422
 2010-11-08 17:58:07 +00:00
Jim Grosbach
bbef2c5fcc MC'ize the '.code 16' and '.thumb_func' ARM directives. 
llvm-svn: 118301
 2010-11-05 22:08:08 +00:00
Jim Grosbach
55b250bb64 MC'ize simple ARMConstantValue entry emission (with a FIXME). 
llvm-svn: 118295
 2010-11-05 20:34:24 +00:00
Jim Grosbach
49dd16ea6f Add FIXME. 
llvm-svn: 118280
 2010-11-05 17:37:13 +00:00
Jim Grosbach
fcfc42b7bb Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
 2010-10-29 21:35:25 +00:00
Jim Grosbach
93fbda05ee ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to 
handle it in the asm lowering.

llvm-svn: 117707
 2010-10-29 20:37:06 +00:00
Jim Grosbach
86ecfda983 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Jim Grosbach
4d4caf1384 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Rafael Espindola
5fecad6a27 Produce the headers directly in the Finish method. This allows us to use 
the existing streamer methods that are endian safe.

llvm-svn: 117323
 2010-10-25 22:26:55 +00:00