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3224 Commits

Author SHA1 Message Date
Craig Topper
ade780fb82 [C++11] Add 'override' keywords to tablegen code. 
llvm-svn: 202937
 2014-03-05 05:17:42 +00:00
Chandler Carruth
cd48c56575 [cleanup] Re-sort all the includes with utils/sort_includes.py. 
llvm-svn: 202811
 2014-03-04 10:07:28 +00:00
Benjamin Kramer
6b03dd4034 [C++11] Use std::tie to simplify compare operators. 
No functionality change.

llvm-svn: 202751
 2014-03-03 19:58:30 +00:00
Benjamin Kramer
b77301145f Unbreak the C++11 build. 
llvm-svn: 202714
 2014-03-03 13:59:41 +00:00
Benjamin Kramer
e4eb1b495f [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 
Remove the old functions.

llvm-svn: 202636
 2014-03-02 12:27:27 +00:00
Benjamin Kramer
803ba41365 Now that we have C++11, turn simple functors into lambdas and remove a ton of boilerplate. 
No intended functionality change.

llvm-svn: 202588
 2014-03-01 11:47:00 +00:00
Hal Finkel
593fc5537a Add an OutPatFrag TableGen class 
Unfortunately, it is currently impossible to use a PatFrag as part of an output
pattern (the part of the pattern that has instructions in it) in TableGen.
Looking at the current implementation, this was clearly intended to work (there
is already code in place to expand patterns in the output DAG), but is
currently broken by the baked-in type-checking assumption and the order in which
the pattern fragments are processed (output pattern fragments need to be
processed after the instruction definitions are processed).

Fixing this is fairly simple, but requires some way of differentiating output
patterns from the existing input patterns. The simplest way to handle this
seems to be to create a subclass of PatFrag, and so that's what I've done here.

As a simple example, this allows us to write:

def crnot : OutPatFrag<(ops node:$in),
                       (CRNOR $in, $in)>;

def       : Pat<(not i1:$in),
                (crnot $in)>;

which captures the core use case: handling of repeated subexpressions inside
of complicated output patterns.

This will be used by an upcoming commit to the PowerPC backend.

llvm-svn: 202450
 2014-02-28 00:26:56 +00:00
Craig Topper
3ce461ca66 Fix indentation. 
llvm-svn: 202344
 2014-02-27 03:30:36 +00:00
Craig Topper
0fa9073645 [x86] Simplify disassembler code slightly. 
llvm-svn: 202233
 2014-02-26 06:01:21 +00:00
Filip Pizlo
5803608763 Stackmaps are used for OSR exits, which is a custom kind of unwinding. Hence, they 
should not be marked nounwind.

Marking them nounwind caused crashes in the WebKit FTL JIT, because if we enable 
sufficient optimizations, LLVM starts eliding compact_unwind sections (or any unwind 
data for that matter), making deoptimization via stackmaps impossible.

This changes the stackmap intrinsic to be may-throw, adds a test for exactly the 
sympton that WebKit saw, and fixes TableGen to handle un-attributed intrinsics.

Thanks to atrick and philipreames for reviewing this.

llvm-svn: 201826
 2014-02-20 23:57:31 +00:00
Craig Topper
80c9d78b97 [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. 
llvm-svn: 201767
 2014-02-20 07:59:43 +00:00
Craig Topper
de3c74571e Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. 
llvm-svn: 201649
 2014-02-19 08:25:02 +00:00
Craig Topper
7d159c5e98 Put some of the X86 formats in a more logical order. 
llvm-svn: 201645
 2014-02-19 06:59:13 +00:00
Craig Topper
5b20c52fcc Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 
llvm-svn: 201641
 2014-02-19 05:34:21 +00:00
Rafael Espindola
c898de3245 Rename a DebugLoc variable to DbgLoc and a DataLayout to DL. 
This is quiet a bit less confusing now that TargetData was renamed DataLayout.

llvm-svn: 201606
 2014-02-18 22:05:46 +00:00
Craig Topper
de78f4304d Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. 
llvm-svn: 201538
 2014-02-18 00:21:49 +00:00
Craig Topper
e48bd43a34 Remove unused method declaration. 
llvm-svn: 201301
 2014-02-13 07:12:40 +00:00
Craig Topper
882df7af18 Remove filtering concept from X86 disassembler table generation. It's no longer necessary. 
llvm-svn: 201299
 2014-02-13 07:07:16 +00:00
Craig Topper
f39f3fd69a Remove special case filtering for instructions with lock prefix as they are all marked with isCodeGenOnly already. 
llvm-svn: 201216
 2014-02-12 08:09:20 +00:00
Craig Topper
8189467f87 Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear from the disassembler table build without custom filtering code. 
llvm-svn: 201215
 2014-02-12 08:02:29 +00:00
Craig Topper
5f3cd9c3a9 Recommit r201059 and r201060 with hopefully a fix for its original failure. 
Original commits messages:

Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.

Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.

llvm-svn: 201065
 2014-02-10 06:55:41 +00:00
Bob Wilson
3e54e44d03 Revert r201059 and r201060. 
r201059 appears to cause a crash in a bootstrapped build of clang. Craig
isn't available to look at it right now, so I'm reverting it while he
investigates.

llvm-svn: 201064
 2014-02-10 05:28:30 +00:00
Craig Topper
4940698ac0 Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. 
llvm-svn: 201060
 2014-02-10 01:58:12 +00:00
Craig Topper
c4ecc4bda5 Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. 
llvm-svn: 201059
 2014-02-10 00:50:34 +00:00
Craig Topper
66d9ce27f7 Remove unnecessary include. 
llvm-svn: 201041
 2014-02-09 07:55:19 +00:00
Craig Topper
8585eaa0e4 Remove some unnecessary code. The conditions it was checking had already been ruled out by the caller. 
llvm-svn: 201039
 2014-02-09 07:13:41 +00:00
Oliver Stannard
690aee262c LLVM-1163: AAPCS-VFP violation when CPRC allocated to stack 
According to the AAPCS, when a CPRC is allocated to the stack, all other
VFP registers should be marked as unavailable.

I have also modified the rules for allocating non-CPRCs to the stack, to make
it more explicit that all GPRs must be made unavailable. I cannot think of a
case where the old version would produce incorrect answers, so there is no test
for this.

llvm-svn: 200970
 2014-02-07 11:19:53 +00:00
Craig Topper
53fbc4f3ca Delete all of the CodeGenInstructions from CodeGenTarget destructor. 
llvm-svn: 200906
 2014-02-06 06:27:59 +00:00
Craig Topper
01f5825e7e Shrink the size of CodeGenInstruction a little bit by using bitfields. 32 bools seemed excessive. 
llvm-svn: 200829
 2014-02-05 09:10:40 +00:00
Craig Topper
314fbecdbd Get rid of a vector copy by just making a pointer out of the reference returned by getInstructionsByEnumValue instead of assigning it to a new vector. 
llvm-svn: 200828
 2014-02-05 07:56:49 +00:00
Craig Topper
81266b8d90 Fix a vector that was passed by value instead of reference. 
llvm-svn: 200827
 2014-02-05 07:27:49 +00:00
Craig Topper
229a74634b Fix a doxygen comment referencing the wrong method name. 
llvm-svn: 200825
 2014-02-05 07:21:07 +00:00
Craig Topper
792771e814 Add CheckChildInteger to ISelMatcher operations. Removes nearly 2000 bytes from X86 matcher table. 
llvm-svn: 200821
 2014-02-05 05:44:28 +00:00
NAKAMURA Takumi
4d643c03f2 TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". [-Wdocumentation] 
llvm-svn: 200628
 2014-02-02 10:53:36 +00:00
Craig Topper
e916566881 Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. 
llvm-svn: 200626
 2014-02-02 09:25:09 +00:00
Craig Topper
d19193392f Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix. 
llvm-svn: 200625
 2014-02-02 07:46:05 +00:00
Craig Topper
75deac3bc2 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. 
llvm-svn: 200624
 2014-02-02 07:08:01 +00:00
Craig Topper
e33ac72bdf Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. 
llvm-svn: 200522
 2014-01-31 08:47:06 +00:00
Craig Topper
0754fb95c1 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch. 
llvm-svn: 200520
 2014-01-31 07:00:55 +00:00
Craig Topper
974822902d Couple minor formatting fixes to the XXXGenDAGISel.inc files. 
llvm-svn: 200459
 2014-01-30 06:42:52 +00:00
Craig Topper
237e63c6ee Delete the Matchers stored in the SmallVectors in SwitchOpcodeMatcher/SwitchTypeMatcher. 
llvm-svn: 200377
 2014-01-29 07:06:07 +00:00
David Woodhouse
a79a37b435 Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr() 
llvm-svn: 200349
 2014-01-28 23:13:18 +00:00
David Woodhouse
5d0b529d58 Change MCStreamer EmitInstruction interface to take subtarget info 
llvm-svn: 200345
 2014-01-28 23:12:42 +00:00
Craig Topper
a2ca508d75 Improve handling of EnforceSmallerThan. Remove all types that are smaller from the larger set not just the smallest type from the smaller set. Ensure 'smaller' vectors have the same or fewer total bits. Similar for 'larger' vectors. 
llvm-svn: 200287
 2014-01-28 04:49:01 +00:00
Craig Topper
5f6416d4b7 Don't use EnforceSmallerThan for EnforceVectorSubVectorTypeIs. EnforceSmallerThan doesn't handle vectors quite right and should really enforce that vectors have the same number of elements. Add explicit checks for vector element count differing in EnforceVectorSubVectorTypeIs instead. This removes some unnecessary type checks in X86GenDAGISel.inc. 
llvm-svn: 200091
 2014-01-25 17:40:33 +00:00
Craig Topper
3884bbbe44 Fix typo in commment tyep->type. 
llvm-svn: 200089
 2014-01-25 17:34:23 +00:00
Craig Topper
343ee04fc5 Use isConcrete and getConcrete instead of using TypeVec directly. 
llvm-svn: 200071
 2014-01-25 05:33:48 +00:00
Craig Topper
94cd919358 Fix EnforceSmallerThan to check !hasVectorTypes on the other type instead of this type to force this type to be scalar. 
llvm-svn: 200070
 2014-01-25 05:17:38 +00:00
Craig Topper
f3ad4cb858 Remove TGValueTypes.cpp from CMakeLists.txt which I forgot to do in r200036. 
llvm-svn: 200037
 2014-01-24 20:51:32 +00:00
Craig Topper
5d7d0716d7 Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before). 
llvm-svn: 200036
 2014-01-24 20:50:47 +00:00