Commit Graph

6 Commits

Author SHA1 Message Date
Quentin Colombet
c960359680 [RegBankSelect] Use reverse post order traversal.
When assigning the register banks of an instruction, it is best to know
all the constraints of the input to have a good idea of how this will
impact the cost of the whole function.

llvm-svn: 265812
2016-04-08 17:19:10 +00:00
Quentin Colombet
d32719b8ce [RegBankSelect] Improve debug output.
Add verbose information when checking if the current and the desired
register banks match.
Detail what happens when we assign a register bank.

llvm-svn: 265804
2016-04-08 16:48:16 +00:00
Quentin Colombet
5210e6758e [RegBankSelect] Add a few debug statements.
llvm-svn: 265749
2016-04-07 23:53:55 +00:00
Quentin Colombet
482efb39c3 [RegBankSelect] Reuse RegisterBankInfo logic to get to the register bank
from a register.
On top of duplicating the logic, it was buggy! It would assert on
physical registers, since MachineRegisterInfo does not have any
information regarding register classes/banks for them.

llvm-svn: 265727
2016-04-07 21:32:23 +00:00
Quentin Colombet
4383f68318 [RegBankSelect] Initial implementation for non-optimized output.
The pass walk through the machine function and assign the register banks
using the default mapping. In other words, there is no attempt to reduce
cross register copies.

llvm-svn: 265707
2016-04-07 18:19:27 +00:00
Quentin Colombet
e9637f2bc7 [GlobalISel] Add the skeleton of the RegBankSelect pass.
This pass is reponsible for assigning the generic virtual registers to register
banks.

llvm-svn: 265440
2016-04-05 19:06:01 +00:00