Guozhi Wei 3025ed18e5 [TargetTransformInfo] Detect 0 latency instructions ...

For instructions that unlikely generate machine instructions, they should also have 0 latency.

Differential Revision: https://reviews.llvm.org/D37833

llvm-svn: 313288

2017-09-14 19:20:02 +00:00

..

AArch64

Revert r291254: [AArch64] Reduce vector insert/extract cost for Falkor

2017-05-24 16:48:39 +00:00

AMDGPU

AMDGPU: Don't assert in TTI with fp32 denorms enabled

2017-08-31 05:47:00 +00:00

ARM

[TTI/CostModel] Correct the way getGEPCost() calls isLegalAddressingMode()

2016-12-03 01:57:24 +00:00

PowerPC

[PPC] Give unaligned memory access lower cost on processor that supports it

2017-02-17 22:29:39 +00:00

SystemZ

[SystemZ] Add support for IBM z14 processor (2/3)

2017-07-17 17:42:48 +00:00

X86

[TargetTransformInfo] Detect 0 latency instructions

2017-09-14 19:20:02 +00:00

no_info.ll

Roll forward r243250

2015-07-26 19:10:03 +00:00