mirror of
https://github.com/RPCS3/llvm-mirror.git
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5dfc642fbd
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. llvm-svn: 310258
336 lines
11 KiB
LLVM
336 lines
11 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}select_f16:
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
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; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
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; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
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; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
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; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @select_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b,
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half addrspace(1)* %c,
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half addrspace(1)* %d) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%c.val = load half, half addrspace(1)* %c
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%d.val = load half, half addrspace(1)* %d
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%fcmp = fcmp olt half %a.val, %b.val
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%r.val = select i1 %fcmp, half %c.val, half %d.val
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_f16_imm_a:
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cmp_lt_f32_e32 vcc, 0.5, v[[B_F32]]
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; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
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; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
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; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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; VI: v_cmp_lt_f16_e32 vcc, 0.5, v[[B_F16]]
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; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @select_f16_imm_a(
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half addrspace(1)* %r,
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half addrspace(1)* %b,
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half addrspace(1)* %c,
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half addrspace(1)* %d) {
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entry:
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%b.val = load half, half addrspace(1)* %b
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%c.val = load half, half addrspace(1)* %c
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%d.val = load half, half addrspace(1)* %d
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%fcmp = fcmp olt half 0xH3800, %b.val
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%r.val = select i1 %fcmp, half %c.val, half %d.val
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_f16_imm_b:
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cmp_gt_f32_e32 vcc, 0.5, v[[A_F32]]
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; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
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; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
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; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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; VI: v_cmp_gt_f16_e32 vcc, 0.5, v[[A_F16]]
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; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @select_f16_imm_b(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %c,
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half addrspace(1)* %d) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%c.val = load half, half addrspace(1)* %c
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%d.val = load half, half addrspace(1)* %d
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%fcmp = fcmp olt half %a.val, 0xH3800
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%r.val = select i1 %fcmp, half %c.val, half %d.val
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_f16_imm_c:
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
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; SI: v_cmp_nlt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
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; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], 0.5, v[[D_F32]], vcc
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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; VI: v_mov_b32_e32 v[[C_F16:[0-9]+]], 0x3800{{$}}
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; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
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; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[C_F16]], v[[D_F16]], vcc
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @select_f16_imm_c(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b,
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half addrspace(1)* %d) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%d.val = load half, half addrspace(1)* %d
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%fcmp = fcmp olt half %a.val, %b.val
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%r.val = select i1 %fcmp, half 0xH3800, half %d.val
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_f16_imm_d:
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
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; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
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; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], 0.5, v[[C_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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; VI: v_mov_b32_e32 v[[D_F16:[0-9]+]], 0x3800{{$}}
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; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
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; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @select_f16_imm_d(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b,
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half addrspace(1)* %c) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%c.val = load half, half addrspace(1)* %c
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%fcmp = fcmp olt half %a.val, %b.val
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%r.val = select i1 %fcmp, half %c.val, half 0xH3800
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_v2f16:
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cmp_lt_f32_e32
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; SI: v_cndmask_b32_e32
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; SI: v_cmp_lt_f32_e32
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; SI: v_cndmask_b32_e32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; VI: v_cmp_lt_f16_e32
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; VI: v_cndmask_b32_e32
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; VI: v_cmp_lt_f16_e32
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; VI: v_cndmask_b32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @select_v2f16(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a,
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<2 x half> addrspace(1)* %b,
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<2 x half> addrspace(1)* %c,
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<2 x half> addrspace(1)* %d) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
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%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
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%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
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%fcmp = fcmp olt <2 x half> %a.val, %b.val
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%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_v2f16_imm_a:
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cmp_lt_f32_e32 vcc, 0.5
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; SI: v_cndmask_b32_e32
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; SI: v_cmp_gt_f32_e32
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; SI: v_cndmask_b32_e32
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; VI: v_cmp_lt_f16_e32
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; VI: v_cndmask_b32_e32
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; VI: v_cmp_gt_f16_e32
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; VI: v_cndmask_b32_e32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @select_v2f16_imm_a(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %b,
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<2 x half> addrspace(1)* %c,
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<2 x half> addrspace(1)* %d) {
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entry:
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%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
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%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
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%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
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%fcmp = fcmp olt <2 x half> <half 0xH3800, half 0xH3900>, %b.val
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%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_v2f16_imm_b:
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cmp_gt_f32_e32 vcc, 0.5
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; SI: v_cndmask_b32_e32
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; SI: v_cmp_lt_f32_e32
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; SI: v_cndmask_b32_e32
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; VI: v_cmp_gt_f16_e32
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; VI: v_cndmask_b32_e32
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; VI: v_cmp_lt_f16_e32
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; VI: v_cndmask_b32_e32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @select_v2f16_imm_b(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a,
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<2 x half> addrspace(1)* %c,
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<2 x half> addrspace(1)* %d) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
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%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
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%fcmp = fcmp olt <2 x half> %a.val, <half 0xH3800, half 0xH3900>
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%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_v2f16_imm_c:
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cmp_nlt_f32_e32
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; SI: v_cndmask_b32_e32
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; SI: v_cmp_nlt_f32_e32
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; SI: v_cndmask_b32_e32
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; VI: v_cmp_nlt_f16_e32
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; VI: v_cndmask_b32_e32
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; VI: v_cmp_nlt_f16_e32
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; VI: v_cndmask_b32_e32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @select_v2f16_imm_c(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a,
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<2 x half> addrspace(1)* %b,
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<2 x half> addrspace(1)* %d) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
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%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
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%fcmp = fcmp olt <2 x half> %a.val, %b.val
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%r.val = select <2 x i1> %fcmp, <2 x half> <half 0xH3800, half 0xH3900>, <2 x half> %d.val
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}select_v2f16_imm_d:
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; SI: v_cmp_lt_f32_e32
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; SI: v_cndmask_b32
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; SI: v_cmp_lt_f32_e32
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; SI: v_cndmask_b32
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; VI: v_cmp_lt_f16_e32
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; VI: v_cndmask_b32
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; VI: v_cmp_lt_f16_e32
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; VI: v_cndmask_b32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @select_v2f16_imm_d(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a,
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<2 x half> addrspace(1)* %b,
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<2 x half> addrspace(1)* %c) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
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%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
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%fcmp = fcmp olt <2 x half> %a.val, %b.val
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%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> <half 0xH3800, half 0xH3900>
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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