Dmitry Preobrazhensky 5a0fe39d12 [AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16 ...

This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322

Reviewers: SamWot, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D36694

llvm-svn: 311011

2017-08-16 15:16:32 +00:00

..

aperture-regs.ll

AMDGPU: Fix disassembly of aperture registers

2017-02-18 18:41:41 +00:00

dpp_vi.txt

[AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa

2016-12-22 11:30:48 +00:00

ds_vi.txt

[AMDGPU][MC] Fix for Bug 28211 + LIT tests

2017-04-07 13:07:13 +00:00

exp_vi.txt

[AMDGPU][MC] Fixed bugs in export instruction

2017-05-19 13:36:09 +00:00

flat_vi.txt

AMDGPU: Remove tfe bit from flat instruction definitions

2017-05-11 17:38:33 +00:00

gfx8_dasm_all.txt

[AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests.

2017-06-19 15:55:02 +00:00

gfx9_dasm_all.txt

[AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier

2017-07-21 13:54:11 +00:00

lit.local.cfg

…

literal16_vi.txt

[AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler output

2017-05-10 13:00:28 +00:00

mac.txt

AMDGPU: Fix crash when disassembling VOP3 mac

2017-04-10 17:58:06 +00:00

mov.txt

…

mtbuf_vi.txt

[AMDGPU] Add intrinsics for tbuffer load and store

2017-06-22 16:29:22 +00:00

mubuf_vi.txt

[AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.

2016-10-07 15:53:16 +00:00

nop.txt

…

sdwa_gfx9.txt

[AMDGPU] SDWA: add disassembler support for GFX9

2017-05-26 15:52:00 +00:00

sdwa_vi.txt

[AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa

2016-12-22 11:30:48 +00:00

si-support.txt

AMDGPU: Replace assert with report_fatal_error

2017-02-15 21:50:34 +00:00

smem_vi.txt

[AMDGPU] Disassembler: fix s_buffer_store_dword instructions

2016-12-05 09:58:51 +00:00

smrd_vi.txt

[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.

2016-10-31 16:07:39 +00:00

sop1_vi.txt

[AMDGPU][MC] Corrected src0 size for s_cbranch_join

2017-04-12 12:40:19 +00:00

sop2_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00

sopc_vi.txt

[AMDGPU][MC] Corrected disassembler to decode instructions with 2 literals

2017-05-19 14:27:52 +00:00

sopk_vi.txt

[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.

2016-04-27 15:17:03 +00:00

sopp_vi.txt

[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.

2016-05-06 17:48:48 +00:00

trap_vi.txt

[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.

2016-05-24 12:05:16 +00:00

vintrp.txt

AMDGPU: Change vintrp printing

2016-12-14 16:36:12 +00:00

vop1_gfx9.txt

AMDGPU: Add definition for v_swap_b32

2017-02-28 21:09:04 +00:00

vop1_vi.txt

[AMDGPU] Add some VI disassembler tests missing from previous autogeneration due to different filecheck prefix. NFC.

2016-04-08 05:42:20 +00:00

vop1.txt

AMDGPU: Fix handling of 16-bit immediates

2016-12-10 00:39:12 +00:00

vop2_vi.txt

[AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64

2017-05-15 14:28:23 +00:00

vop3_gfx9.txt

[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16

2017-08-16 15:16:32 +00:00

vop3_vi.txt

[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes

2017-08-16 13:51:56 +00:00

vopc_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00