Elliot Saba a967752a95 [X86] Don't clobber EBX in stackprobes ...

On X86, the stackprobe emission code chooses the `R11D` register, which
is illegal on i686.  This ends up wrapping around to `EBX`, which does
not get properly callee-saved within the stack probing prologue,
clobbering the register for the callers.

We fix this by explicitly using `EAX` as the stack probe register.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D109203

(cherry picked from commit ae8507b0df738205a6b9e3795ad34672b7499381)

2021-09-10 09:30:52 -07:00

..

AArch64

Workaround incorrect types when lowering fixed length gather/scatter

2021-09-09 09:05:58 -07:00

AMDGPU

AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9

2021-07-27 15:56:42 -04:00

ARC

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ARM

[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert

2021-08-18 12:14:24 -07:00

AVR

[AVR] Only support sp, r0 and r1 in llvm.read_register

2021-07-24 14:03:27 +02:00

BPF

BPF: avoid NE/EQ loop exit condition

2021-08-06 12:45:53 -07:00

Generic

[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX

2021-07-26 23:21:38 +00:00

Hexagon

[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs

2021-07-27 18:36:28 -05:00

Inputs

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Lanai

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

M68k

[M68k][GloballSel] LegalizerInfo implementation

2021-07-15 13:00:43 -06:00

Mips

[llvm][sve] Lowering for VLS truncating stores

2021-07-23 14:04:55 +01:00

MIR

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

MSP430

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NVPTX

[NVPTX] Add select(cc,binop(),binop()) fast-math tests

2021-07-18 15:30:24 +01:00

PowerPC

Revert "[HardwareLoops] Change order of SCEV expression construction for InitLoopCount."

2021-09-08 20:46:17 -07:00

RISCV

[RISCV] Fix reporting of incorrect commutable operand indices

2021-09-03 15:48:26 -07:00

SPARC

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

SystemZ

[SystemZ][z/OS] Initial code to generate assembly files on z/OS

2021-07-27 11:29:15 -04:00

Thumb

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

Thumb2

[SimplifyCFG] performBranchToCommonDestFolding(): require block-closed SSA form for bonus instructions (PR51125)

2021-09-10 09:02:26 -07:00

VE

[LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization.

2021-06-29 11:00:11 -07:00

WebAssembly

[WebAssembly] Fix FastISel of condition in different block (PR51651)

2021-08-31 20:58:25 -07:00

WinCFGuard

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WinEH

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X86

[X86] Don't clobber EBX in stackprobes

2021-09-10 09:30:52 -07:00

XCore

Update @llvm.powi to handle different int sizes for the exponent

2021-06-17 09:38:28 +02:00