Files
archived-llvm-mirror/test/CodeGen/AArch64
Tim Northover aebb01e004 GlobalISel: implement low-level type with just size & vector lanes.
This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).

llvm-svn: 276158
2016-07-20 19:09:30 +00:00
..
2015-02-13 10:48:30 +00:00
2016-05-31 18:31:14 +00:00
2015-08-11 14:35:29 +00:00
2016-05-03 05:21:53 +00:00
2016-05-26 12:42:55 +00:00
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