Jessica Paquette 5e7f539f83 [GlobalISel][AArch64] Add support for @llvm.ceil ...

This adds a G_FCEIL generic instruction and uses it in AArch64. This adds
selection for floating point ceil where it has a supported, dedicated
instruction. Other cases aren't handled here.

It updates the relevant gisel tests and adds a select-ceil test. It also adds a
check to arm64-vcvt.ll which ensures that we don't fall back when we run into
one of the relevant cases.

llvm-svn: 349664

2018-12-19 19:01:36 +00:00

..

GlobalISel

[GlobalISel][AArch64] Add support for @llvm.ceil

2018-12-19 19:01:36 +00:00

CodeGenCWrappers.h

[AArch64] Add Tiny Code Model for AArch64

2018-08-22 11:31:39 +00:00

GenericOpcodes.td

[GlobalISel][AArch64] Add support for @llvm.ceil

2018-12-19 19:01:36 +00:00

Target.td

[ARM][MC] Move information about variadic register defs into tablegen

2018-12-03 10:32:42 +00:00

TargetCallingConv.td

Remove trailing space

2018-07-30 19:41:25 +00:00

TargetInstrPredicate.td

[AArch64] Refactor the Exynos scheduling predicates

2018-12-10 17:17:26 +00:00

TargetIntrinsicInfo.h

GlobalISel: support translation of intrinsic calls.

2016-07-29 22:32:36 +00:00

TargetItinerary.td

[NFC] Fix comment of class InstrStage

2018-02-12 15:02:49 +00:00

TargetLoweringObjectFile.h

Implement -frecord-command-line (-frecord-gcc-switches)

2018-12-14 15:38:15 +00:00

TargetMachine.h

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00

TargetOptions.h

[GlobalISel] Make EnableGlobalISel always set when GISel is enabled

2018-11-29 12:56:32 +00:00

TargetPfmCounters.td

[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.

2018-11-09 13:15:32 +00:00

TargetSchedule.td

[llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).

2018-11-29 12:15:56 +00:00

TargetSelectionDAG.td

[Intrinsic] Signed Fixed Point Multiplication Intrinsic

2018-12-12 06:29:14 +00:00