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2 Commits

Author SHA1 Message Date
Matt Arsenault
41cd9eb045 AMDGPU: Don't fold copies to physregs 
In a future patch, this will help cleanup m0 handling.

The register coalescer handles copies from a register that
materializes an immediate, but doesn't handle move immediates
itself. The virtual register uses will often be allocated to the same
register, so there end up being no real copy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374257 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-10-09 22:51:42 +00:00
Changpeng Fang
5165c118c2 AMDGPU: Fix an out of date assert in addressing FrameIndex 
Reviewers:
  arsenm

Differential Revision:
  https://reviews.llvm.org/D67574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373404 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-10-01 23:07:14 +00:00