12 Commits

Author SHA1 Message Date
Zoran Jovanovic
76b46df975 [mips][microMIPS] Extending size reduction pass with LWP and SWP
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.
Differential Revision: https://reviews.llvm.org/D39115


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334595 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-13 12:51:37 +00:00
Simon Dardis
55b76bc78d [mips] Select the correct instruction for computing frameindexes
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47582


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333736 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 10:07:10 +00:00
Nicola Zaghen
0818e789cb Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects.
The renaming was done as follows:
- git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g'
- git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
- Manual change to APInt
- Manually chage DOCS as regex doesn't match it.

In the transition period the DEBUG() macro is still present and aliased
to the LLVM_DEBUG() one.

Differential Revision: https://reviews.llvm.org/D43624



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332240 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-14 12:53:11 +00:00
Aleksandar Beserminji
9d32402369 [mips] Removal of microMIPS64R6
All files and parts of files related to microMIPS4R6 are removed.
When target is microMIPS4R6, errors are printed.

This is LLVM part of patch.

Differential Revision: https://reviews.llvm.org/D35625



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320350 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-11 11:21:40 +00:00
Zoran Jovanovic
aec1f2aefd [mips][microMIPS] Extending size reduction pass with XOR16
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
XOR instruction is transformed into 16-bit instruction XOR16, if possible.
Differential Revision: https://reviews.llvm.org/D34239


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310579 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-10 10:27:29 +00:00
Zoran Jovanovic
9f96341372 [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP
Author: milena.vujosevic.janicic
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
ADDIU instruction is transformed into 16-bit instruction ADDIUSP
ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP
Usage of u_int64_t replaced by uint64_t to avoid issues because of which previous patch version was reverted:
Differential Revision: https://reviews.llvm.org/D34511



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310044 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-04 10:18:44 +00:00
Zoran Jovanovic
8f691f1275 Reverting commit 308011.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308017 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-14 10:52:22 +00:00
Zoran Jovanovic
3a788ca0f4 [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
ADDIU instruction is transformed into 16-bit instruction ADDIUSP
ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP
Function InRange is changed to avoid left shifting of negative values, since 
that caused some sanitizer tests to fail (so the previous patch 
Differential Revision: https://reviews.llvm.org/D34511


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308011 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-14 10:13:11 +00:00
Simon Dardis
7810ae7481 Revert "[mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP"
This reverts commit r305455. This commit was reported as breaking one of
the sanitizer buildbots. Reverting until lab.llvm.org comes back online.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305557 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-16 14:00:33 +00:00
Zoran Jovanovic
952d4e50f5 [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
ADDIU instruction is transformed into 16-bit instruction ADDIUSP
ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP
Differential Revision: https://reviews.llvm.org/D33887


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305455 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-15 09:14:33 +00:00
Zoran Jovanovic
9c2941a24c [mips][microMIPS] Extending size reduction pass with LBU16, LHU16, SB16 and SH16
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
LBU instruction is transformed into 16-bit instruction LBU16
LHU instruction is transformed into 16-bit instruction LHU16
SB instruction is transformed into 16-bit instruction SB16
SH instruction is transformed into 16-bit instruction SH16
Differential Revision: https://reviews.llvm.org/D33091


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304550 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:14:21 +00:00
Zoran Jovanovic
d2333e0a15 [mips][microMIPS] Adding code size reduction pass for MicroMIPS
Author: milena.vujosevic.janicic
Reviewers: sdardis
The code implements size reduction pass for MicroMIPS.
Load and store instructions are examined and transformed, if possible.
lw32 instruction is transformed into 16-bit instruction lwsp
sw32 instruction is transformed into 16-bit instruction swsp
Arithmetic instrcutions are examined and transformed, if possible.
addu32 instruction is transformed into 16-bit instruction addu16
subu32 instruction is transformed into 16-bit instruction subu16
Differential Revision: https://reviews.llvm.org/D15144


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301540 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-27 13:10:48 +00:00