3 Commits

Author SHA1 Message Date
Andrea Di Biagio
3ac65c443f [Tablegen][PredicateExpander] Add the ability to define checks for invalid registers.
This was discussed in review D49436.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337378 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-18 11:03:22 +00:00
Andrea Di Biagio
1885077d4c [Tablegen][PredicateExpander] Fix a bug in expandCheckImmOperand.
Function `expandCheckImmOperand` should always check if the input machine
instruction is passed by reference before calling method `getOperand()` on it.

Found while working on a patch that relies on `expandCheckImmOperand` to expand
a scheduling predicate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337294 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 16:11:37 +00:00
Andrea Di Biagio
e68d92b387 [RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.
This patch is the first of a sequence of three patches described by the LLVM-dev
RFC "MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html

The goal of this patch is to introduce a new class of scheduling predicates for
SchedReadVariant and SchedWriteVariant.

An MCSchedPredicate can be used instead of a normal SchedPredicate to model
checks on the instruction (either a MachineInstr or a MCInst).
Internally, an MCSchedPredicate encapsulates an MCInstPredicate definition.
MCInstPredicate allows the definition of expressions with a well-known semantic,
that can be used to generate code for both MachineInstr and MCInst.

This is the first step toward teaching to tools like lllvm-mca how to resolve
variant scheduling classes.

Differential Revision: https://reviews.llvm.org/D46695


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333282 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-25 15:55:37 +00:00