5 Commits

Author SHA1 Message Date
Sanjay Patel
74ff3cc8bd [AMDGPU] fix test to survive more FP undef constant folding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327066 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-08 21:30:56 +00:00
Sanjay Patel
a6a4aed947 [AMDGPU] fix test to survive the most basic undef constant folding
This will likely need to be changed again for anything more than:
fmul undef, undef -> undef


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327034 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-08 17:34:25 +00:00
Yaxun Liu
06d39e2dc8 Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
The regression on ppc64 was not due to this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320788 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 03:56:57 +00:00
Yaxun Liu
92d81a8d46 Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
This commit might have caused regression on ppc64. Revert it to verify that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320712 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 16:12:04 +00:00
Yaxun Liu
084f87947f CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
Two issues were found about machine inst scheduler when compiling ProRender
with -g for amdgcn target:

GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it
should not since DBG_VALUE is not mapped in LiveIntervals.

when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and
ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D41132


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320650 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 22:38:09 +00:00