23856 Commits

Author SHA1 Message Date
Craig Topper
3f6f6c2f6d [PowerPC] Add an ISD::TRUNCATE to the legalization for ppc_is_decremented_ctr_nonzero
Summary:
I believe legalization is really expecting that ReplaceNodeResults will return something with the same type as the thing that's being legalized. Ultimately, it uses the output to replace the uses in the DAG so the type should match to make that work.

There are two relevant cases here. When crbits are enabled, then i1 is a legal type and getSetCCResultType should return i1. In this case, the truncate will be between i1 and i1 and should be removed (SelectionDAG::getNode does this). Otherwise, getSetCCResultType will be i32 and the legalizer will promote the truncate to be i32 -> i32 which will be similarly removed.

With this fixed we can remove some code from PromoteIntRes_SETCC that seemed to only exist to deal with the intrinsic being replaced with a larger type without changing the other operand. With the truncate being used for connectivity this doesn't happen anymore.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: nemanjai, llvm-commits, kbarton

Differential Revision: https://reviews.llvm.org/D41654

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321959 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-07 07:51:36 +00:00
Sanjay Patel
df87029dcf [x86, MemCmpExpansion] allow 2 pairs of loads per block (PR33325)
This is the last step needed to fix PR33325:
https://bugs.llvm.org/show_bug.cgi?id=33325

We're trading branch and compares for loads and logic ops. 
This makes the code smaller and hopefully faster in most cases.

The 24-byte test shows an interesting construct: we load the trailing scalar 
elements into vector registers and generate the same pcmpeq+movmsk code that 
we expected for a pair of full vector elements (see the 32- and 64-byte tests).

Differential Revision: https://reviews.llvm.org/D41714


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321934 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-06 16:16:04 +00:00
Adrian McCarthy
ced21a6948 Re-land "Fix faulty assertion in debug info"
This had been reverted because the new test failed on non-X86 bots.  I moved
the new test to the appropriate subdirectory to correct this.

Differential Revision: https://reviews.llvm.org/D41264
Original submission:  r321122 (which was reverted by r321125)

This reverts commit 3c1639b5703c387a0d8cba2862803b4e68dff436.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321911 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-05 23:01:04 +00:00
Bjorn Pettersson
39ebb68152 [DebugInfo] Align comments in debug_loc section
Summary:
This commit updates the BufferByteStreamer, used by DebugLocStream
to buffer bytes/comments to put in the debug_loc section, to
make sure that the Buffer and Comments vectors are synced.
Previously, when an SLEB128 or ULEB128 was emitted together with
a comment, the vectors could be out-of-sync if the LEB encoding
added several entries to the Buffer vectors, while we only added
a single entry to the Comments vector.

The goal with this is to get the comments in the debug_loc
section in the .s file correctly aligned.

Example (using ARM as target):
Instead of

  .byte 144                     @ sub-register DW_OP_regx
  .byte 128                     @ 256
  .byte 2                       @ DW_OP_piece
  .byte 147                     @ 8
  .byte 8                       @ sub-register DW_OP_regx
  .byte 144                     @ 257
  .byte 129                     @ DW_OP_piece
  .byte 2                       @ 8
  .byte 147                     @
  .byte 8                       @

we now get

  .byte 144                     @ sub-register DW_OP_regx
  .byte 128                     @ 256
  .byte 2                       @
  .byte 147                     @ DW_OP_piece
  .byte 8                       @ 8
  .byte 144                     @ sub-register DW_OP_regx
  .byte 129                     @ 257
  .byte 2                       @
  .byte 147                     @ DW_OP_piece
  .byte 8                       @ 8

Reviewers: JDevlieghere, rnk, aprantl

Reviewed By: aprantl

Subscribers: davide, Ka-Ka, uabelho, aemerson, javed.absar, kristof.beyls, llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D41763

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321907 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-05 22:20:30 +00:00
Sam Parker
8681051b9e [DAGCombine] Fix for PR37563
While searching for loads to be narrowed, equal sized loads were not
added to the list, resulting in anyext loads not being converted to
zext loads.

https://bugs.llvm.org/show_bug.cgi?id=35763

Differential Revision: https://reviews.llvm.org/D41628


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321862 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-05 08:47:23 +00:00
Aditya Nandakumar
09d2d44675 [GISel]: Don't create G_MUL with 1 during translation of GEP
When element size is 1, it's just wasteful to create MUL with 1.
https://reviews.llvm.org/D41738

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321857 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-05 02:56:28 +00:00
Adrian Prantl
bfdde98123 Debug Info: Support DW_AT_calling_convention on composite types.
This implements the DWARF 5 feature described at
http://www.dwarfstd.org/ShowIssue.php?issue=141215.1

This allows a consumer to understand whether a composite data type is
trivially copyable and thus should be passed by value instead of by
reference. The canonical example is being able to distinguish the
following two types:

  // S is not trivially copyable because of the explicit destructor.
  struct S {
     ~S() {}
  };

  // T is a POD type.
  struct T {
     ~T() = default;
  };

This patch adds two new (DI)flags to LLVM metadata: TypePassByValue
and TypePassByReference.

<rdar://problem/36034922>
Differential Revision: https://reviews.llvm.org/D41743

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321844 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-05 01:13:37 +00:00
Amara Emerson
e5c4445c2d [DAGCombine] Ensure SDNode use iterator is incremented properly.
Fixes an ASAN bug found by oss-fuzz.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321813 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-04 18:38:45 +00:00
Elena Demikhovsky
cc82acde14 Changes in the branch relaxation algorithm.
The existing version worked incorrectly when inversion of a branch condintion is impossible.
Changed the "fixupConditionalBranch()" function - a new BB (a trampoline) is created to keep the original branch condition.

Differential Revision: https://reviews.llvm.org/D41634



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321785 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-04 07:08:45 +00:00
Bob Wilson
ce3ee9dbde support phi ranges for machine-level IR
Add iterator ranges for machine instruction phis, similar to the IR-level
phi ranges added in r303964. I updated a few places to use this. Besides
general code simplification, this change will allow removing a non-upstream
change from Swift's copy of LLVM (in a better way than my previous attempt
in http://reviews.llvm.org/D19080).

https://reviews.llvm.org/D41672

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321783 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-04 02:58:15 +00:00
Simon Pilgrim
fed8082832 [DAGCombine] Handle out of range EXTRACT_VECTOR_ELT indices
Handle this in DAGCombiner::visitEXTRACT_VECTOR_ELT the same as we already do in SelectionDAG::getNode and use APInt instead of getZExtValue.

This should also fix oss-fuzz #4910

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321767 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03 22:42:33 +00:00
Sanjay Patel
668a58d36b [ExpandMemcmp] rename variables and add hook to override pref for number of loads per block; NFC
The preference only applies to 'memcmp() == 0' expansion, so try to make that clearer.
x86 will likely benefit by increasing the default value from '1' to '2' as seen in PR33325:
https://bugs.llvm.org/show_bug.cgi?id=33325
...so that is the planned follow-up to this clean-up step.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321756 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03 20:02:39 +00:00
Alex Bradbury
d32868dc00 Thread MCSubtargetInfo through Target::createMCAsmBackend
Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. 
D20830 threaded an MCSubtargetInfo reference through 
MCAsmBackend::relaxInstruction, but this isn't the only function that would 
benefit from access. This patch removes the Triple and CPUString arguments 
from createMCAsmBackend and replaces them with MCSubtargetInfo.

This patch just changes the interface without making any intentional 
functional changes. Once in, several cleanups are possible:
* Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend
* Support 16-bit instructions when valid in MipsAsmBackend::writeNopData
* Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl
* Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221)

This change initially exposed PR35686, which has since been resolved in r321026.

Differential Revision: https://reviews.llvm.org/D41349


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321692 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03 08:53:05 +00:00
Amara Emerson
caeab26ff8 [GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflow
Previously the code for handling G_SMULO didn't properly check for the signed
multiply overflow, instead treating it the same as the unsigned G_UMULO.

Fixes PR35800.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321690 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03 04:56:56 +00:00
Amara Emerson
7b20f91f4d [AArch64][GlobalISel] Fix assert fail with unknown intrinsic.
A call may have an intrinsic name but not have a valid intrinsic ID,
for example with llvm.invariant.group.barrier. If so, treat it as a
normal call like FastISel does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321662 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 18:56:39 +00:00
Amara Emerson
d8de4cebd9 [AArch64][GlobalISel] Enable GlobalISel at -O0 by default
Tests updated to explicitly use fast-isel at -O0 instead of implicitly.

This change also allows an explicit -fast-isel option to override an
implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0.

Differential Revision: https://reviews.llvm.org/D41362

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321655 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 16:30:47 +00:00
Daniel Jasper
7f55be51ae Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)
Our internal testing has revealed has discovered bugs in PPC builds.
I have forward reproduction instructions to the original author (Nirav).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321649 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 14:38:52 +00:00
Sam Parker
2714c01fbb [DAGCombine] Fix for PR35765
Remove the acceptance of ANY_EXTEND nodes while trying to move and
nodes back to loads.

Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=35765

Differential Revision: https://reviews.llvm.org/D41625


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321641 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 10:19:01 +00:00
Craig Topper
6bc4edc1ec [SelectionDAG] Teach WidenVecOp_Convert to widen the operation if a widened result type would still be legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321638 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 07:30:53 +00:00
Craig Topper
beeba032a1 [SelectionDAG] Remove ifs on getTypeAction being TypeWidenVector from some of the WideVecOp handlers.
We should only be in the handler if the tyep action is TypeWidenVector. There's no reason to try to do anything else.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321635 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 01:55:07 +00:00
Craig Topper
4663cc0847 [SelectionDAG][X86][AArch64] Require targets to specify the promotion type when using setOperationAction Promote for INT_TO_FP and FP_TO_INT
Currently the promotion for these ignores the normal getTypeToPromoteTo and instead just tries to double the element width. This is because the default behavior of getTypeToPromote to just adds 1 to the SimpleVT, which has the affect of increasing the element count while keeping the scalar size the same.

If multiple steps are required to get to a legal operation type, int_to_fp will be promoted multiple times. And fp_to_int will keep trying wider types in a loop until it finds one that works.

getTypeToPromoteTo does have the ability to query a promotion map to get the type and not do the increasing behavior. It seems better to just let the target specify the promotion type in the map explicitly instead of letting the legalizer iterate via widening.

FWIW, it's worth I think for any other vector operations that need to be promoted, we have to specify the type explicitly because the default behavior of getTypeToPromote isn't useful for vectors. The other types of promotion already require either the element count is constant or the total vector width is constant, but neither happens by incrementing the SimpleVT enum.

Differential Revision: https://reviews.llvm.org/D40664

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321629 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-01 19:21:35 +00:00
Benjamin Kramer
66f3fb9fac Use phi ranges to simplify code. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321585 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-30 15:27:33 +00:00
Geoff Berry
39064346e3 [MachineOperand] Fix LiveDebugVariables code after isRenamable change.
Fix code in LiveDebugVariables that was changing def MachineOperands to
uses, which will hit an assert for dead operands after the change to add
the renamable bit to MachineOperands.  Avoid the assert by clearing the
dead bit before changing the operand to a use.

Fixes issue reported in out of tree target by Jesper Antonsson at Ericsson.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321571 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-29 21:01:09 +00:00
Dimitry Andric
d08f4172a2 Avoid modifying DbgInfo while looping in salvageDebuginfo
Summary:
I have been getting rather difficult to reproduce SIGBUS crashes when
compiling certain FreeBSD sources, and their stack traces pointed
squarely at `SelectionDAG::salvageDebugInfo()`:

```
Core was generated by `/usr/obj/share/dim/src/freebsd/clang600-import/amd64.amd64/tmp/usr/bin/cc -cc1 -'.
Program terminated with signal SIGBUS, Bus error.
#0  isInvalidated () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h:115
115       bool isInvalidated() const { return Invalid; }
(gdb) bt
#0  isInvalidated () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h:115
#1  salvageDebugInfo () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7116
#2  0x00000000033b2516 in operator() () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:3595
#3  __invoke<(lambda at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:3593:59) &, llvm::SDNode *, llvm::SDNode *> () at /usr/include/c++/v1/type_traits:4323
#4  __call<(lambda at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:3593:59) &, llvm::SDNode *, llvm::SDNode *> () at /usr/include/c++/v1/__functional_base:349
#5  operator() () at /usr/include/c++/v1/functional:1562
#6  0x00000000033b0817 in operator() () at /usr/include/c++/v1/functional:1916
#7  NodeDeleted () at /share/dim/src/freebsd/clang600-import/contrib/llvm/include/llvm/CodeGen/SelectionDAG.h:293
#8  0x0000000003529dde in RemoveDeadNodes () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:610
#9  0x00000000035556df in MorphNodeTo () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6794
#10 0x00000000033a9acc in MorphNode () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:2594
#11 0x00000000033ac80b in SelectCodeCommon () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:3601
#12 0x00000000023d464b in SelectCode () at /usr/obj/share/dim/src/freebsd/clang600-import/amd64.amd64/tmp/obj-tools/lib/clang/libllvm/X86GenDAGISel.inc:282902
#13 Select () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:3072
#14 0x00000000033a5afa in DoInstructionSelection () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:988
#15 0x00000000033a4e1a in CodeGenAndEmitDAG () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:868
#16 0x00000000033a2643 in SelectAllBasicBlocks () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1624
#17 0x000000000339f158 in runOnMachineFunction () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:466
#18 0x00000000023d03c4 in runOnMachineFunction () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:175
#19 0x00000000035cc8c2 in runOnFunction () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/MachineFunctionPass.cpp:62
#20 0x00000000030dca9a in runOnFunction () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/IR/LegacyPassManager.cpp:1520
#21 0x00000000030dccf3 in runOnModule () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/IR/LegacyPassManager.cpp:1541
#22 0x00000000030dd228 in runOnModule () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/IR/LegacyPassManager.cpp:1597
#23 run () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/IR/LegacyPassManager.cpp:1700
#24 0x00000000014db578 in EmitAssembly () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/lib/CodeGen/BackendUtil.cpp:815
#25 EmitBackendOutput () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/lib/CodeGen/BackendUtil.cpp:1181
#26 0x00000000014d5b26 in HandleTranslationUnit () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/lib/CodeGen/CodeGenAction.cpp:292
#27 0x0000000001c4c332 in ParseAST () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/lib/Parse/ParseAST.cpp:159
#28 0x00000000015d546c in Execute () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/lib/Frontend/FrontendAction.cpp:897
#29 0x0000000001cec311 in ExecuteAction () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/lib/Frontend/CompilerInstance.cpp:991
#30 0x00000000014b4f81 in ExecuteCompilerInvocation () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp:252
#31 0x00000000014aa73f in cc1_main () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/tools/driver/cc1_main.cpp:221
#32 0x00000000014b2928 in ExecuteCC1Tool () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/tools/driver/driver.cpp:309
#33 main () at /share/dim/src/freebsd/clang600-import/contrib/llvm/tools/clang/tools/driver/driver.cpp:388
(gdb) frame 1
#1  salvageDebugInfo () at /share/dim/src/freebsd/clang600-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7116
7116        if (DV->isInvalidated())
(gdb) disassemble
Dump of assembler code for function salvageDebugInfo():
[...]
   0x0000000003557348 <+744>:   nopl   0x0(%rax,%rax,1)
   0x0000000003557350 <+752>:   mov    (%r12),%r13
=> 0x0000000003557354 <+756>:   cmpb   $0x0,0x31(%r13)
   0x0000000003557359 <+761>:   jne    0x35573b0 <salvageDebugInfo()+848>
(gdb) info registers
[...]
r13            0x5a5a5a5a5a5a5a5a       6510615555426900570
```

The `0x5a5a5a5a5a5a5a5a` value in `r13` indicates the memory was either
uninitialized, or already freed.

Unfortunately I do not have a simple self-contained test case for this.
However, it seems pretty clear that the call to `AddDbgValue()` in
`salvageDebugInfo()` causes the problems, since it modifies
`SelectionDag::DbgInfo` while looping through one of its DenseMaps:

```
void SelectionDAG::salvageDebugInfo(SDNode &N) {
[...]
  for (auto DV : GetDbgValues(&N)) {
    if (DV->isInvalidated())
      continue;
[...]
        AddDbgValue(Clone, N0.getNode(), false);
[...]
  }
}
```

At least, if I comment out the `AddDbgValue()` call, the crashes go
away.  I propose to change this function slightly, similar to the
`SelectionDAG::transferDbgValues()` function just above it, to save the
cloned SDDbgValues in a separate SmallVector, and only call
AddDbgValue() on them after the for loop is done.

Reviewers: aprantl, bogner, bkramer, davide

Reviewed By: davide

Subscribers: davide, krytarowski, JDevlieghere, emaste, llvm-commits

Differential Revision: https://reviews.llvm.org/D41589


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321545 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-28 23:42:44 +00:00
Craig Topper
beb40ba025 [SelectionDAG] Add creating new node debug messages for load, store, gather, and scatter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321540 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-28 19:46:16 +00:00
Craig Topper
c2dcb7f2db [SelectionDAG] Add some debug print messages to LegalizeVectorOps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321535 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-28 19:46:01 +00:00
Simon Pilgrim
58a0346050 [DAGCombine] foldBinOpIntoSelect can fail to constant fold in some cases.
For example, float operations may fail to constant fold under certain circumstances (inf/nan/denormal creation etc.)

Reduced from oss-fuzz #4802 test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321488 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-27 11:36:18 +00:00
Simon Pilgrim
ff53894326 [DAGCombine] visitANDLike - ensure APInt is is in range for getSExtValue/getZExtValue
Reduced from oss-fuzz #4782 test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321464 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-26 23:27:44 +00:00
Simon Pilgrim
03438cb38e [DAGCombine] Don't combine (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2) for i1
Reduced from oss-fuzz #4773 test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321455 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-26 14:48:28 +00:00
Craig Topper
c8e5ca820e [DAGCombiners] Don't turn ANDs to shuffles with zero so early. Give some other combines a chance to run.
This moves the combine for turning ANDs into shuffle with zero out of SimplifyVBinOps and places it only in visitAND below the reassociate handling. This fixes the specific case I noticed where we failed to combine two ands with constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321417 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-24 02:05:18 +00:00
Craig Topper
59bac370ba [SelectionDAG] Teach SelectionDAG::getNode to constant fold zext/aext/sext of constant build vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321414 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-23 20:21:29 +00:00
Craig Topper
3a056544bb [SelectionDAG][X86] Don't use ->getValueType(0) after a call to getOperand to get the type of the operand.
getOperand returns an SDValue that contains the node and the result number. There is no guarantee that the result number if 0. By using the -> operator we are calling SDNode::getValueType rather than SDValue::getValueType. This requires supplying a result number and we shouldn't assume it was 0.

I don't have a test case. Just noticed while cleaning up some other code and saw that it occurred in other places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321397 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-23 02:54:50 +00:00
Nirav Dave
e1b8f14c6d [DAG] Add missing case check from findbaseoffset merge from r321389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321391 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 22:06:56 +00:00
Nirav Dave
5d9f5f4088 Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI.
BaseIndexOffset supercedes findBaseOffset analysis save only Constant
Pool addresses. Migrate analysis to BaseIndexOffset.

Relanding after correcting base address matching check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321389 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 21:20:55 +00:00
Nirav Dave
ecdc6849ca Revert "[DAG] Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI."
which was causing miscompilations in for some test-suite components.

This reverts commit 3e9de9ff0f3162920a2a3cba51c7dc14b54b4d16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321380 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 19:33:56 +00:00
Sanjoy Das
b166e6723e (Re-landing) Expose a TargetMachine::getTargetTransformInfo function
Re-land r321234.  It had to be reverted because it broke the shared
library build.  The shared library build broke because there was a
missing LLVMBuild dependency from lib/Passes (which calls
TargetMachine::getTargetIRAnalysis) to lib/Target.  As far as I can
tell, this problem was always there but was somehow masked
before (perhaps because TargetMachine::getTargetIRAnalysis was a
virtual function).

Original commit message:

This makes the TargetMachine interface a bit simpler.  We still need
the std::function in TargetIRAnalysis to avoid having to add a
dependency from Analysis to Target.

See discussion:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html

I avoided adding all of the backend owners to this review since the
change is simple, but let me know if you feel differently about this.

Reviewers: echristo, MatzeB, hfinkel

Reviewed By: hfinkel

Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D41464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321375 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 18:21:59 +00:00
Craig Topper
15c5ab82da [SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left.
This seems to improve X86's ability to match this into an address computation. Otherwise the other operand gets assigned to the base register and the stack pointer + frame index ends up in the index register. But index registers can't encode ESP/RSP so we end up having to move it into another register to meet the constraint.

I could try to improve the address matcher in X86, but swapping the producer seemed easier. Several other places already have the operands in this order so this is at least consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321370 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 17:18:13 +00:00
Nirav Dave
24bf4ab201 [DAG] Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI.
BaseIndexOffset supercedes findBaseOffset analysis save only Constant
Pool addresses. Migrate analysis to BaseIndexOffset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321364 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 16:59:09 +00:00
Sam Parker
6a32f89109 [DAGCombine] Revert r321259
Improve ReduceLoadWidth for SRL Patch is causing an issue on the
PPC64 BE santizer.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321349 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 08:36:25 +00:00
Easwaran Raman
fe7b9dc2d2 Add hasProfileData() to check if a function has profile data. NFC.
Summary:
This replaces calls to getEntryCount().hasValue() with hasProfileData
that does the same thing. This refactoring is useful to do before adding
synthetic function entry counts but also a useful cleanup IMO even
otherwise. I have used hasProfileData instead of hasRealProfileData as
David had earlier suggested since I think profile implies "real" and I
use the phrase "synthetic entry count" and not "synthetic profile count"
but I am fine calling it hasRealProfileData if you prefer.

Reviewers: davidxl, silvas

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41461

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321331 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 01:33:52 +00:00
Simon Pilgrim
c46700a6d5 [DAGCombiner] Remove (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) fold. NFCI.
More general cases are already handled by constant canonicalization and then the ReassociateOps call at line 5327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321280 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 16:54:03 +00:00
Simon Pilgrim
c218ca8072 [DAGCombiner] Generalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) combine to work on non-splat vectors
The knownbits_mask_or_shuffle_uitofp change is interesting - shuffle combines manage to kick in, removing the AND constant mask load. For targets with fast-variable-shuffle this should reduce further to VPOR+VPSHUFB+VCVTDQ2PS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321279 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 16:34:46 +00:00
Simon Pilgrim
9d06ec6ce5 [DAGCombiner] Generalize (and (or x, C), D) -> D iff (C & D) == D combine to work on non-splat vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321275 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 15:17:29 +00:00
Sam Parker
153f2e3851 [DAGCombine] Improve ReduceLoadWidth for SRL
If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.

Differential Revision: https://reviews.llvm.org/D41350


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321259 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 12:55:04 +00:00
Sanjoy Das
0a1aae823b Revert "Expose a TargetMachine::getTargetTransformInfo function"
This reverts commit r321234.  It breaks the -DBUILD_SHARED_LIBS=ON build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321243 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 02:34:39 +00:00
Sanjoy Das
0950f32a89 Expose a TargetMachine::getTargetTransformInfo function
Summary:
This makes the TargetMachine interface a bit simpler.  We still need
the std::function in TargetIRAnalysis to avoid having to add a
dependency from Analysis to Target.

See discussion:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html

I avoided adding all of the backend owners to this review since the
change is simple, but let me know if you feel differently about this.

Reviewers: echristo, MatzeB, hfinkel

Reviewed By: hfinkel

Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D41464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321234 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 01:06:58 +00:00
Matt Arsenault
37489f4c21 DAG: Tolerate non-MemSDNodes for OPC_RecordMemRef
When intrinsics are allowed to have mem operands, there
are two ways this can happen. First is an intrinsic
that is marked has having a mem operand, but is not handled
by getTgtMemIntrinsic.

The second way can occur even for intrinsics which do not
have a mem operand. It seems the selector table does
some kind of sorting based on the opcode, and the
mem ref recording can happen in the same scope for
intrinsics that both do and do not have mem refs.
I haven't been able to figure out exactly why this happens
(although it happens even with the matcher optimizations disabled).
I'm not sure if it's worth trying to avoid hitting this for
these nodes since I think it's still reasonable to handle
this in case getTgtMemIntrinic is not implemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321208 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-20 19:11:59 +00:00
Nirav Dave
3c80c06a63 [DAG] Fix condition on overlapping store check.
Prevent overlapping store elision when overlapping store is
pre-inc/dec as analysis is wrong in these cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321204 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-20 19:06:47 +00:00
Teresa Johnson
9274a9b246 [PGO] Function section hotness prefix should look at all blocks
Summary:
The function section prefix for PGO based layout (e.g. hot/unlikely)
should look at the hotness of all blocks not just the entry BB.
A function with a cold entry but a very hot loop should be placed in the
hot section, for example, so that it is located close to other hot
functions it may call. For SamplePGO it was already looking at the
branch weights on calls, and I made that code conditional on whether
this is SamplePGO since it was essentially a noop for instrumentation
PGO anyway.

Reviewers: davidxl

Subscribers: eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D41395

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321197 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-20 17:53:10 +00:00
Krzysztof Parzyszek
44ef9b61ca Add optional SelectionDAG* parameter to SValue::dump and SDValue::dumpr
These functions simply call their counterparts in the associated SDNode,
which do take an optional SelectionDAG. This change makes the legalization
debug trace a little easier to read, since target-specific nodes will
now have their names shown instead of "Unknown node #123".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321180 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-20 15:15:04 +00:00