24 Commits

Author SHA1 Message Date
Eugene Zelenko
e74c436b70 [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304839 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-06 22:22:41 +00:00
Matthias Braun
c1fa0731c3 MIRParser: Allow regclass specification on operand
You can now define the register class of a virtual register on the
operand itself avoiding the need to use a "registers:" block.

Example: "%0:gr64 = COPY %rax"

Differential Revision: https://reviews.llvm.org/D22398

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292321 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 00:59:19 +00:00
Tom Stellard
5b9e507366 MIRParser: Add support for parsing vreg reg alloc hints
Reviewers: qcolombet, MatzeB

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D26573

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286911 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-15 00:03:14 +00:00
Matthias Braun
8ee2011aa7 MIRParser: Rewrite register info initialization; mostly NFC
This changes MachineRegisterInfo to be initializes after parsing all
instructions. This is in preparation for upcoming commits that allow the
register class specification on the operand or deduce them from the
MCInstrDesc.

This commit removes the unused feature of having nonsequential register
numbers. This was confusing anyway as the vreg numbers would be
different after parsing when you had "holes" in your numbering.

This patch also introduces the concept of an incomplete virtual
register. An incomplete virtual register may be used during .mir parsing
to construct MachineOperands without knowing the exact register class
(or register bank) yet.

NFC except for some error messages.

Differential Revision: https://reviews.llvm.org/D22397

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283848 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-11 03:13:01 +00:00
Matthias Braun
67cca86db4 MIRParser: Move SlotMapping and SourceMgr refs to PFS; NFC
Code cleanup: Move references to SlotMapping and SourceMgr into the
PerFunctionMIParsingState to avoid unnecessary passing around in
parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275342 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-13 23:27:50 +00:00
Matthias Braun
13b86678de MIRParser: Move MachineFunction reference into PFS; NFC
Code cleanup: The PerFunctionMIParsingState is per function, moving a
reference into PFS we can avoid passing around the MachineFunction in an
extra parameter most of the time.

Also change most signatures to consistently pass PFS reference first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275329 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-13 22:23:23 +00:00
Quentin Colombet
c4f21c06ed [MIR] Check that generic virtual registers get a size.
Without that check it was possible to write test cases where the size
was not specified and we ended up with weird asserts down the road,
because the default value (1) would not make sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272226 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-08 23:27:46 +00:00
Mehdi Amini
f6071e14c5 [NFC] Header cleanup
Removed some unused headers, replaced some headers with forward class declarations.

Found using simple scripts like this one:
clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap'

Patch by Eugene Kosov <claprix@yandex.ru>

Differential Revision: http://reviews.llvm.org/D19219

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266595 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-18 09:17:29 +00:00
Alex Lorenz
a80c044041 MIR Serialization: Serialize MMI's variable debug information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245396 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-19 00:13:25 +00:00
Alex Lorenz
07c6bd8492 MIR Serialization: Serialize the frame information's stack protector index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245372 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-18 22:26:26 +00:00
Alex Lorenz
5d09c2f25d MIR Serialization: Change MIR syntax - use custom syntax for MBBs.
This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.

This is an example of a function's body that uses the old syntax:

    body:
      - id: 0
        name: entry
        instructions:
          - '%eax = MOV32r0 implicit-def %eflags'
          - 'RETQ %eax'
    ...

The same body is now written like this:

    body: |
      bb.0.entry:
        %eax = MOV32r0 implicit-def %eflags
        RETQ %eax
    ...

This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:

   BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
      t2IT 1, 24, implicit-def %itstate
      %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
   }

This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244982 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-13 23:10:16 +00:00
Alex Lorenz
01b5d5b27f MIR Serialization: Serialize the unnamed basic block references.
This commit serializes the references from the machine basic blocks to the
unnamed basic blocks.

This commit adds a new attribute to the machine basic block's YAML mapping
called 'ir-block'. This attribute contains the actual reference to the
basic block.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243340 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 22:42:41 +00:00
Alex Lorenz
a5da4f1f8d MIR Serialization: Serialize the machine function's liveins.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243288 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 17:42:45 +00:00
Alex Lorenz
0e4484f44d MIR Serialization: Initial serialization of machine constant pools.
This commit implements the initial serialization of machine constant pools and
the constant pool index machine operands. The constant pool is serialized using
a YAML sequence of YAML mappings that represent the constant values.
The target-specific constant pool items aren't serialized by this commit.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242707 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 20:51:18 +00:00
Alex Lorenz
ed2032f17a MIR Serialization: Serialize the frame index machine operands.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242487 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 23:37:45 +00:00
Alex Lorenz
a2e819fb09 MIR Serialization: Serialize the jump table index operands.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242358 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 23:38:35 +00:00
Alex Lorenz
6e50c921d0 MIR Serialization: Serialize the machine basic block live in registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242204 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 21:24:41 +00:00
Alex Lorenz
1cca87a981 MIR Serialization: Serialize the virtual register operands.
Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D11005


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241959 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:51:20 +00:00
Alex Lorenz
ddc6f0a433 MIR Parser: wrap 'MBBSlots' from the MI parsing functions in a struct. NFC.
This commit modifies the interface for the machine instruction parsing
functions by wrapping the parameter 'MBBSlots' in a new structure called
'PerFunctionMIParsingState'. This change is useful as in the future I will be
able to pass new parameters to the machine instruction parser just by modifying
the 'PerFunctionMIParsingState' structure instead of adding a new parameter to
each function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241607 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 17:46:43 +00:00
Alex Lorenz
73d2cc5b8e MIR Serialization: Serialize MBB successors.
This commit implements serialization of the machine basic block successors. It
uses a YAML flow sequence that contains strings that have the MBB references.
The MBB references in those strings use the same syntax as the MBB machine
operands in the machine instruction strings.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10699


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241093 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 18:16:42 +00:00
Alex Lorenz
939f023bf9 MIR Parser: make the machine instruction parsing interface more consistent. NFC.
This commit refactors the interface for machine instruction parser. It adopts
the pattern of returning a bool and passing in the result in the first argument
that is used by the other parsing methods for the the method 'parse' and the
function 'parseMachineInstr'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241085 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 17:47:50 +00:00
Alex Lorenz
d986612a1a MIR Serialization: Serialize global address machine operands.
This commit serializes the global address machine operands.
This commit doesn't serialize the operand's offset and target
flags, it serializes only the global value reference.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10671


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240851 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:56:48 +00:00
Alex Lorenz
438a4919fd MIR Serialization: Serialize machine basic block operands.
This commit serializes machine basic block operands. The
machine basic block operands use the following syntax:

  %bb.<id>[.<name>]

This commit also modifies the YAML representation for the
machine basic blocks - a new, required field 'id' is added
to the MBB YAML mapping.

The id is used to resolve the MBB references to the
actual MBBs. And while the name of the MBB can be
included in a MBB reference, this name isn't used to
resolve MBB references - as it's possible that multiple
MBBs will reference the same BB and thus they will have the
same name. If the name is specified, the parser will verify
that it is equal to the name of the MBB with the specified id.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10608


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240792 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 16:46:11 +00:00
Alex Lorenz
2f801faafb MIR Serialization: Serialize machine instruction names.
This commit implements initial machine instruction serialization. It
serializes machine instruction names. The instructions are represented
using a YAML sequence of string literals and are a part of machine
basic block YAML mapping.

This commit introduces a class called 'MIParser' which will be used to
parse the machine instructions and operands.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10481


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240295 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 17:02:30 +00:00